1 MEG x 16 FPM DRAM FPM DRAM MT4C1M16C3, MT4LC1M16C3 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets FEATURES • JEDEC- and industry-standard x16 timing, functions, pinouts, and packages • High-performance, low-power CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or 5V ±0.5V) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN • Optional self refresh (S) for low-power data retention • BYTE WRITE and BYTE READ access cycles • 1,024-cycle refresh (10 row, 10 column addresses) • FAST-PAGE-MODE (FPM) access OPTIONS • PIN ASSIGNMENT (Top View) 42-Pin SOJ VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC WE# RAS# NC NC A0 A1 A2 A3 VCC MARKING Voltage 1 3.3V 5V LC C • Packages Plastic SOJ (400 mil) Plastic TSOP (400 mil) DJ TG • Timing 50ns access 60ns access -5 -6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 44/50-Pin TSOP VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC CASL# CASH# OE# A9 A8 A7 A6 A5 A4 VSS VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC NC NC WE# RAS# NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC CASL# CASH# OE# A9 A8 A7 A6 A5 A4 VSS NOTE: The # symbol indicates signal is active LOW. 1 MEG x 16 FPM DRAM PART NUMBERS • Refresh Rates Standard Refresh (16ms period) Self Refresh (128ms period) None S2 • Operating Temperature Range Commercial (0oC to +70oC) Extended (-20oC to +80oC) None ET 3 PART NUMBER MT4LC1M16C3DJ-6 MT4LC1M16C3DJ-6 S MT4LC1M16C3TG-6 MT4LC1M16C3TG-6 S MT4C1M16C3DJ-6 MT4C1M16C3TG-6 SUPPLY PACKAGE REFRESH 3.3V SOJ Standard 3.3V SOJ Self 3.3V TSOP Standard 3.3V TSOP Self 5V SOJ Standard 5V TSOP Standard Part Number Example: MT4LC1M16C3DJ-5 GENERAL DESCRIPTION The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#. The CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition LOW and NOTE: 1. The third field distinguishes the low voltage offering: LC designates VCC = 3.3V and C designates VCC = 5V. 2. Contact factory for availability. 3. Available only on MT4C1M16C3 (5V) KEY TIMING PARAMETERS SPEED -5 -6 tRC tRAC tPC tAA tCAC tRP 84ns 110ns 50ns 60ns 20ns 35ns 25ns 30ns 15ns 15ns 30ns 40ns 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM GENERAL DESCRIPTION (continued) the last CAS# to transition back HIGH. Use of only one of the two results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15). Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are entered ten bits (A0-A9) at a time. RAS# is used to latch the first ten bits and CAS# the latter ten bits. The CAS# function is determined by the first CAS# (CASL# or CASH#) to transition LOW and the last one to transition back HIGH. The CAS# function also determines whether the cycle will be a refresh cycle (RAS#-ONLY) or an active cycle (READ, WRITE, or READ-WRITE) once RAS# goes LOW. The CASL# and CASH# inputs internally generate a CAS# signal that functions identically to a single CAS# input on other DRAMs. The key difference is that each CAS# input (CASL# and CASH#) controls its corre- sponding DQ tristate logic (in conjunction with OE# and WE#). CASL# controls DQ0-DQ7 and CASH# controls DQ8-DQ15. The two CAS# controls give the 1 Meg x 16 DRAM BYTE WRITE cycle capabilities. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS, whichever occurs last. Taking WE# LOW will initiate a WRITE cycle, selecting DQ0-DQ15. If WE# goes LOW prior to CAS# going LOW, the output pin(s) remain open (High-Z) until the next CAS# cycle. If WE# goes LOW after CAS# goes LOW and data reaches the output pins, data-out (Q) is activated and retains the selected cell data as long as CAS# and OE# remain LOW (regardless of WE# or RAS#). This late WE# pulse results in a READ-WRITE cycle. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O. Pin direction is controlled by OE# and WE#. FUNCTIONAL BLOCK DIAGRAM WE# CASL# DATA-IN BUFFER CAS# CASH# DQ0 16 NO. 2 CLOCK GENERATOR 10 DQ15 DATA-OUT BUFFER COLUMNADDRESS BUFFER 10 COLUMN DECODER OE# 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1,024 REFRESH CONTROLLER 16 SENSE AMPLIFIERS I/O GATING REFRESH COUNTER 1,024 x 16 10 RAS# ROWADDRESS BUFFERS (10) 10 ROW DECODER 10 NO. 1 CLOCK GENERATOR 1,024 1,024 x 1,024 x 16 MEMORY ARRAY VDD VSS 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM GENERAL DESCRIPTION (continued) and executing anyRAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that all 1,024 combinations of RAS# addresses (A0-A9) are executed at least every 16ms (128ms on the “S” version), regardless of sequence. The CBR REFRESH cycle will also invoke the refresh counter and controller for row-address control. The MT4LC1M16C3 must be refreshed periodically in order to retain stored data. FAST PAGE MODE ACCESS FAST-PAGE-MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row-address-defined (A0-A9) page boundary. The FAST-PAGE-MODE cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation. Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standbylevel. The chip is also preconditioned for the next cycle during the RAS# HIGH time. Memory cell data is retained in its correct state by maintaining power BYTE ACCESS CYCLE The BYTE WRITEs and BYTE READs are determined by the use of CASL# and CASH#. Enabling CASL# will select a lower byte access (DQ0-DQ7), while enabling CASH# will select an upper byte access (DQ0-DQ15). Enabling both CASL# and CASH# selects a WORD WRITE cycle. The 1 Meg x 16 DRAM may be viewed as two 1 Meg x 8 DRAMs that have common input controls, with the exception of the CAS# inputs. Figure 1 illustrates the BYTE WRITE and WORD WRITE cycles. Figure 2 illustrates BYTE READ and WORD READ cycles. WORD WRITE LOWER BYTE WRITE RAS# CASL# CASH# WE# STORED DATA 1 1 LOWER BYTE (DQ0-DQ7) OF WORD 0 1 1 1 1 1 0 UPPER BYTE (DQ8-DQ15) OF WORD 1 0 1 0 0 0 0 INPUT DATA 0 INPUT DATA 0 1 0 0 0 0 0 STORED DATA 0 STORED DATA 0 0 1 0 0 1 0 0 0 0 0 INPUT DATA 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 X X X X X X X X 0 0 0 0 X X 1 0 X X X X 1 0 1 1 X X 1 1 1 0 1 0 1 1 1 1 INPUT DATA STORED DATA 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 ADDRESS 1 ADDRESS 0 X = NOT EFFECTIVE (DON'T CARE) Figure 1 WORD and BYTE WRITE Example 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 125µs per row, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOWto-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst CBR refresh sequence, all 1,024 rows must be refreshed using a minimum tRC refresh rate prior to resuming normal operation. DRAM REFRESH Preserve correct memory cell data by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all 1,024 combinations of RAS# addresses are executed within tREF (MAX), regardless of sequence. The CBR and EXTENDED and SELF REFRESH cycles will invoke the internal refresh counter for automatic RAS# addressing. An optional self refresh mode is available on the “S” version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The “S” option allows the user STANDBY Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time. WORD READ LOWER BYTE READ RAS# CASL# CASH# WE# LOWER BYTE (DQ0-DQ7) OF WORD UPPER BYTE (DQ8-DQ15) OF WORD STORED DATA OUTPUT DATA OUTPUT DATA STORED DATA STORED DATA OUTPUT DATA OUTPUT DATA STORED DATA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 ADDRESS 0 ADDRESS 1 Z = High-Z Figure 2 WORD and BYTE READ Example 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Pin Relative to VSS 3.3V ..................................................... -1V to +4.6V 5V ........................................................... -1V TO +7V Voltage on NC, Inputs or I/O Pins Relative to VSS 3.3V ..................................................... -1V to +5.5V 5V ........................................................... -1V TO +7V Operating Temperature TA (commercial) ...................................... 0°C to +70°C TA (extended "ET") ............................ -20°C to +80°C Storage Temperature (plastic) ............ -55°C to +150°C Power Dissipation ........................................................ 1W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX) 3.3V PARAMETER/CONDITION 5V SYMBOL MIN MAX MIN SUPPLY VOLTAGE VCC 3 3.6 4.5 5.5 V INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC VIH 2 5.5 2.4 VCC + 1 V INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC VIL -1.0 0.8 -0.5 0.8 V II -2 2 -2 2 µA OUTPUT HIGH VOLTAGE: IOUT = -2mA VOH 2.4 – 2.4 – V OUTPUT LOW VOLTAGE: IOUT = 2mA VOL – 0.4 – 0.4 V IOZ -5 5 -5 5 µA INPUT LEAKAGE CURRENT: Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); All other pins not under test = 0V OUTPUT LEAKAGE CURRENT: Any output at VOUT [0V ≤ VOUT ≤ VCC (MAX)]; DQ is disabled and in High-Z state 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 5 MAX UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 6; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX) PARAMETER/CONDITION SYMBOL SPEED 3.3V 5V UNITS NOTES STANDBY CURRENT: TTL (RAS# = CAS# = VIH) ICC1 ALL 1 2 mA STANDBY CURRENT: CMOS (non-“S” version only) (RAS# = CAS# = other inputs = VCC - 0.2V) ICC2 ALL 500 500 µA STANDBY CURRENT: CMOS (“S” version only) (RAS# = CAS# = other inputs = VCC - 0.2V) ICC2 ALL 150 150 µA OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC3 -5 -6 180 170 190 180 mA 23 OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) ICC4 -5 -6 110 90 120 110 mA 23 REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) ICC5 -5 -6 180 170 190 180 mA REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC6 -5 -6 180 170 180 180 mA 4, 7 ICC7 ALL 300 300 µA 4, 7 ICC8 ALL 300 300 µA 4, 7 REFRESH CURRENT: Extended (“S” version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with RAS# ž tRASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) CAPACITANCE (Note: 2; notes can be found on page 9); PARAMETER SYMBOL MAX UNITS Input Capacitance: Addresses CI1 5 pF Input Capacitance: RAS#, CASL#, CASH#, WE#, OE# CI2 7 pF Input/Output Capacitance: DQ CIO 7 pF 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX) AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) Last CAS# going LOW to first CAS# to return HIGH CAS# to output in Low-Z CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN Refresh cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) RAS# pulse width (Self Refresh) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS) READ command setup time Refresh period (1,024 cycles) Refresh period (1,024 cycles) “S” version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time (Self Refresh) READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLCH tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH MIN tOFF 0 0 20 47 tORD tPC tPRWC -6 MAX 25 38 0 0 42 MIN 45 0 0 49 15 8 8 15 8 10 0 8 10,000 15 10 10 15 10 10 0 5 28 5 38 5 28 8 8 0 0 12 12 8 tRAC 9 9 50 50 100 84 11 0 0 tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tRP 30 5 90 0 13 116 tRPC tRPS tRRH tRSH tRWC 7 15 15 10 12 0 0 25 56 10,000 125,000 15 60 12 10 60 60 100 104 14 0 0 16 128 tREF 10,000 35 5 45 5 35 10 10 0 0 50 tRAD MAX 30 10,000 125,000 16 128 40 5 105 0 15 140 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ms ms ns ns ns ns ns ns NOTES 27 18 29 27 32, 35 4, 28 30 26, 29 30 28 28 28 4, 27 18, 27 23, 29 19, 29 19, 29 17, 26, 29 22 20 11, 17, 23 31 31 20 14, 27 16, 28 27 16 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX) AC CHARACTERISTICS PARAMETER RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 -5 SYMBOL tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP 8 MIN 67 13 2 8 38 0 5 8 8 -6 MAX 50 MIN 79 15 2 10 45 0 5 10 10 MAX 50 UNITS ns ns ns ns ns ns ns ns ns NOTES 18 36 18, 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM NOTES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 18. tWCS, tRWD, tAWD, and tCWD are restrictive operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If tWCS ≥ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data out-put will remain an open circuit throughout the entire cycle. If tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of Q (at access time and until CAS# or OE# goes back to VIH) is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. During a READ cycle, if OE# is LOW then taken HIGH before CAS# goes HIGH, Q goes open. If OE# is tied permanently LOW, LATE WRITE and READ-MODIFY-WRITE operations are not permissible and should not be attempted. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 22. All other inputs at 0.2V or VCC - 0.2V. 23. Column address changed once each cycle. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after tOEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 25. The DQs open during READ cycles once tOD or tOFF occur. 26. The 3ns minimum is a parameter guaranteed by design. 27. The first CASx edge to transition LOW. 28. The last CASx edge to transition HIGH. 29. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 30. Last falling CASx edge to first rising CASx edge. 31. Last rising CASx edge to next cycle’s last rising CASx edge. All voltages referenced to VSS. This parameter is sampled. VCC = +3.3V or 5.0V; f = 1 MHz. ICC is dependent on output loading. Specified values are obtained with minimum cycle time and the output open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ 70°C) for commercial and (-20°C ≤ TA ≤ 80°C) for extended “ET” is ensured. An initial pause of 100µs is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 5ns. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. If CAS# = VIH, data output is High-Z. If CAS# = VIL, data output may contain data from the last valid READ cycle. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2V. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the Q buffer, CAS# must be pulsed HIGH for tCP. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. Either tRCH or tRRH must be satisfied for a READ cycle. 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM NOTES (continued) 32. 33. 34. 35. 36. Last rising CASx edge to first falling CASx edge. First DQs controlled by the first CASx to go LOW. Last DQs controlled by the last CASx to go HIGH. Each CASx must meet minimum pulse width. Last CASx to go LOW. 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 37. All DQs controlled, regardless CASL# and CASH#. 38. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not permissible and should not be attempted. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM READ CYCLE tRC tRP tRAS RAS# V IH V IL tCSH tRSH tRCD tCRP CASL#/CASH# tRRH tCAS tCLCH V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH ROW COLUMN tRCH tRCS WE# V IH V IL tAA tRAC tOFF tCAC tCLZ V DQ V IOH IOL OPEN t OE OE# OPEN VALID DATA t OD V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR tASC tASR tCAS tCLCH tCLZ tCRP tCSH tOD MIN 25 38 45 0 0 0 0 tCAC tCAH -6 MAX 15 8 8 10,000 10 10 -5 MAX UNITS SYMBOL 30 ns ns tOFF tRAD 15 ns ns ns tRC 10,000 ns ns tRAS tRCD 10 0 5 10 0 5 ns ns ns tRCH 38 0 45 0 tRRH 15 ns ns 15 ns tOE 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 12 12 MAX MIN MAX UNITS 0 12 50 0 15 60 ns ns 10,000 ns ns ns tRAC tRAH tRCS tRP tRSH 11 -6 MIN 9 9 50 10,000 12 10 60 84 11 104 14 ns ns 0 0 30 0 0 40 ns ns ns 0 13 0 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM EARLY WRITE CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tCRP CASL#/CASH# tRCD tCAS tCLCH V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH ROW COLUMN tCWL tRWL tWCR tWCH tWCS tWP WE# V IH V IL tDH tDS V DQ V IOH IOL OE# VALID DATA V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCLCH tCRP tCSH MIN 38 0 -6 MAX 0 8 8 10 5 MIN 45 0 -5 MAX 0 10 10,000 10 10 5 10,000 UNITS ns ns SYMBOL tRAH tRAS ns ns tRC ns ns ns tRP tRCD tRSH tRWL 38 8 45 10 ns ns tWCH 8 0 10 0 ns ns tWCS tDS tRAD 9 12 ns tCWL tDH 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 tWCR tWP 12 MIN 9 50 -6 MAX 10,000 MIN 10 60 MAX 10,000 UNITS ns ns 84 11 104 14 ns ns 30 13 13 40 15 15 ns ns ns 8 38 10 45 ns ns 0 5 0 5 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRWC tRAS RAS# V IH V IL tCRP CASL#/CASH# tCSH tRSH tCAS tRCD tCLCH V IH V IL tAR tRAD tRAH tASR ADDR tRP V IH V IL tASC tCAH ROW COLUMN tRCS ROW tRWD tCWD tCWL tRWL tAWD tWP V IH V IL WE# tAA tRAC tCAC tDS tCLZ V DQ V IOH IOL VALID D OUT OPEN tOE OE# tDH VALID D IN tOD OPEN tOEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD MIN tCAS tCLCH MIN 15 15 ns ns 60 ns ns ns tRAC tRAD 9 ns ns ns tRAH 9 50 8 8 10,000 15 10 10 10,000 tOEH tRAS tRCD 5 38 5 45 ns ns tRSH 35 10 10 ns ns ns tRWD tDH 28 8 8 tDS 0 0 ns tCWL 0 ns ns tRCS tCWD UNITS 12 12 0 49 ns ns tCSH MAX 0 0 42 10 0 tCRP MIN tOE 10 0 tCLZ MAX 45 0 tOD 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 tRP tRWC tRWL tWP 13 -6 MIN 38 0 15 MAX 30 SYMBOL UNITS ns ns ns tCAC tCAH -5 -6 MAX 25 8 10 50 12 10,000 10 60 10,000 ns ns 11 0 30 14 0 40 ns ns ns 13 116 15 140 ns ns 67 13 5 79 15 5 ns ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM FAST-PAGE-MODE READ CYCLE tRASP RAS# V IH V IL tCSH tCRP CASL#/CASH# tRP tPC tCP tCAS, tCLCH tRCD tCAS, tCLCH tRSH tCAS, tCLCH tCP tCP V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH COLUMN tRCS WE# tASC tCAH COLUMN tRCH COLUMN ROW tRCS tRRH tRCH V IH V IL tAA tCPA tCAC tOFF tCLZ V IOH V IOL tCAC tAA tCPA tOFF tCLZ tCAC tOFF tCLZ VALID DATA tOD OPEN tOE OE# tCAH tRCS tRCH tAA tRAC DQ tASC tOE VALID DATA tOD tOE VALID DATA tOD OPEN V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN 45 0 0 0 0 15 tCAH 8 tCAS 8 10 tCLCH tCLZ tCP 15 10,000 10 10 tCSH tOD 0 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 10,000 0 5 28 5 38 MAX 30 10 0 8 tCPA tCRP MIN 38 tCAC -5 -6 MAX 25 35 5 45 12 0 15 SYMBOL UNITS ns ns MAX 0 12 12 tOE tOFF ns ns ns ns tPC ns ns tRASP ns ns ns tRCH ns ns tRRH 20 tRAC tRAD tRAH tRCD tRCS tRP tRSH -6 MIN MIN MAX UNITS 0 15 15 ns ns 25 50 9 9 50 11 60 12 10 125,000 60 14 125,000 ns ns ns ns ns ns 0 0 30 0 0 40 ns ns ns 0 13 0 15 ns ns ns 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM FAST-PAGE-MODE EARLY WRITE CYCLE tRP tRASP RAS# V IH V IL tCSH tCRP CASL#/CASH# tCAS, tCLCH tRCD tPC tCP tCAS, tCLCH tRSH tCAS, tCLCH tCP tCP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH tASC COLUMN tWCS tWP WE# tASC COLUMN tCWL tWCH tWCS tCAH tCAH COLUMN tCWL tWCH tWCS tWP ROW tCWL tWCH tWP V IH V IL tRWL tWCR tDS V DQ V IOH IOL OE# tDH tDS VALID DATA tDH tDS VALID DATA tDH VALID DATA V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCLCH tCP MIN 38 0 0 8 8 10 -5 -6 MAX MIN 45 MAX 0 0 10,000 10 10 10 10,000 SYMBOL UNITS ns tPC ns ns tRAD ns ns ns tRASP tRAH tRCD tRP 8 5 5 5 ns ns tRSH 45 10 10 ns ns ns tWCH tDH 38 8 8 tDS 0 0 ns tWP tCRP tCSH tCWL 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 tRWL tWCR tWCS 15 MIN -6 MAX MIN MAX UNITS 20 25 ns 9 9 12 10 ns ns 50 11 30 125,000 60 14 40 125,000 ns ns ns 13 13 15 15 ns ns 8 38 0 10 45 0 ns ns ns 5 5 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP tRP V IH V IL RAS# tCSH tCRP CASL#/CASH# NOTE 1 tRCD tPRWC tPC tCP tCAS, tCLCH tRSH tCP tCAS, tCLCH tCP tCAS, tCLCH V IH V IL tAR tRAD tRAH tASR V IH V IL ADDR tASC tCAH ROW tASC COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRWD tRCS WE# tRWL tCWL tWP tAWD tCWD tCWL tWP tAWD tCWD tAWD tCWD V IH V IL tAA tAA tRAC tDH tCPA tDS tCAC tCLZ DQ tCWL tWP V IOH V IOL tAA tDH tCPA tDS tCAC tCLZ tCAC tCLZ tOD tOE VALID VALID D OUT D IN VALID VALID D OUT D IN VALID VALID D OUT D IN OPEN tDH tDS tOD OPEN tOD tOE OEH tOE V IH V IL OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD MIN 38 45 0 0 0 0 ns ns tOE ns ns ns tPC ns ns tRAD ns ns ns tRASP 42 8 tCAS 8 10 tCP tCRP tCSH tCWD tCWL tDH 15 10 10,000 0 8 tCPA MAX 30 49 15 tCAH tCLZ MIN -5 UNITS ns ns tCAC tCLCH -6 MAX 25 10 10 10,000 0 5 28 35 SYMBOL tDS tOD tOEH tPRWC MIN 0 0 tRCD tRCS 5 38 5 45 ns ns tRP 28 8 35 10 ns ns tRWD 8 10 ns tWP tRSH tRWL 12 MIN 0 0 12 10 20 47 25 56 50 9 9 50 11 0 MAX 15 15 8 tRAC tRAH -6 MAX 60 12 10 125,000 60 14 0 UNITS ns ns ns ns ns ns ns ns ns 125,000 ns ns ns 30 13 40 15 ns ns 67 13 79 15 ns ns 5 5 ns NOTE: 1. tPC is for LATE WRITE only. 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) tRASP RAS# tRP V IH V IL tRSH tCSH tCRP CASL#/CASH# tPC tRCD tCAS tCP tCAS tCP V IH V IL tAR tRAD tASR ADDR V IH V IL ROW tASC tCAH tASC tRAH COLUMN tCAH tCWL tRWL tRCS tWP tWCH tWCS WE# V IH V IL tCAC NOTE 1 t OFF tDS t CLZ Q V OH V OL ROW COLUMN VALID DATA OPEN tDH VALID DATA tAA tRAC OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN 38 0 0 tCAC 8 tCAS 8 0 8 tCLZ tCP tCRP MIN MAX 30 45 0 0 15 tCAH -5 -6 MAX 25 15 10 10,000 10 0 5 10,000 SYMBOL UNITS ns tOFF MAX MIN MAX UNITS 0 12 0 15 ns 60 ns ns ns ns ns ns tPC tRAD 9 ns ns tRAH 9 50 ns ns ns tRCD 20 tRAC tRASP tRCS tRP -6 MIN 25 50 12 125,000 10 60 125,000 ns ns 11 0 30 14 0 40 ns ns ns 13 13 15 15 ns ns 5 38 5 45 ns ns tRSH 8 8 10 10 ns ns tWCH tDH tWCS 8 0 10 0 ns ns tDS 0 0 ns tWP 5 5 ns tCSH tCWL tRWL NOTE: 1. tPC is for LATE WRITE only. 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) tRC tRAS RAS# tRP V IH V IL tCRP CASL#/CASH# tRPC V IH V IL tASR ADDR tRAH V IH V IL ROW ROW V Q V OH OL OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP RAS# tRAS tRP NOTE 1 tRAS V IH V IL tRPC tCP CASL#/CASH# V IH V IL DQ V OH V OL tCSR tCSR tCHR OPEN tWRP WE# tRPC tCHR tWRH tWRP tWRH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR tCHR tCP tCRP tCSR tRAH MIN 0 8 -5 -6 MAX MIN 0 10 MAX SYMBOL UNITS ns ns tRAS tRC 8 5 5 5 ns ns tRP 5 9 5 10 ns ns tWRH tRPC tWRP MIN -6 MAX MIN MAX UNITS 50 84 60 104 10,000 ns ns 30 5 40 5 ns ns 8 8 10 10 ns ns NOTE: 1. End of CBR REFRESH cycle. 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW) tRAS RAS# tRAS V IH V IL tCRP CASL#/CASH# tRP tRSH tRCD tCHR V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH COLUMN tAA tRAC tCAC tCLZ V DQx V IOH IOL tOFF OPEN VALID DATA OPEN t OE tOD t ORD OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN 38 0 0 tCAC tCAH tCHR tCLZ tCRP tOD -6 MAX 25 MIN -5 MAX 30 UNITS ns tOFF 15 ns ns ns ns tRAD 9 9 50 45 0 0 15 SYMBOL tOE tORD 10 10 ns ns tRAH 0 5 0 0 5 0 ns ns ns tRCD 12 15 MAX 12 MIN MAX 15 UNITS ns 0 0 12 0 0 15 ns ns ns ns tRAC 8 8 tRAS tRP tRSH -6 MIN 50 11 30 13 60 12 10,000 10 60 10,000 14 40 15 ns ns ns ns ns NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) RAS# V IH V IL (( )) tRPC tCSR tRPS NOTE 2 tRPC (( )) tCP CAS# NOTE 1 tRASS tRP (( )) tCP tCHD (( )) (( )) V IH V IL V DQ V OH OL (( )) tWRP OPEN tWRP tWRH tWRH (( )) (( )) V WE# V IH IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tCHD tCLCH tCP tCSR tRASS MIN 15 10 8 5 100 -5 -6 MAX MIN 15 10 5 5 100 MAX UNITS ns ns ns ns µs SYMBOL tRP tRPC tRPS tWRH tWRP MIN 30 5 90 8 8 -6 MAX MIN 40 5 105 10 10 MAX UNITS ns ns ns ns ns NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used. 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM 42-PIN PLASTIC SOJ (400 mil) 1.079 (27.41) 1.073 (27.25) .405 (10.29) .399 (10.13) .445 (11.30) .435 (11.05) PIN #1 INDEX .050 (1.27) TYP 1.000 (25.40) .148 (3.76) .138 (3.51) .032 (0.81) .026 (0.66) .095 (2.40) .080 (2.02) SEATING PLANE .037 (0.94) MAX DAMBAR PROTRUSION .020 (0.51) .015 (0.38) .380 (9.65) .360 (9.14) NOTE: .030 (0.76) MIN 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 1 MEG x 16 FPM DRAM 44/50-PIN PLASTIC TSOP (400 mil) .828 (21.04) .822 (20.88) SEE DETAIL A .029 (0.75) TYP 50 .467 (11.86) .459 (11.66) .402 (10.21) .398 (10.11) 1 25 .007 (0.18) .005 (0.13) PIN #1 INDEX .031 (0.80) TYP .018 (0.45) .012 (0.30) .010 (0.25) .004 (0.10) .047 (1.20) MAX SEATING PLANE .008 (0.20) .002 (0.05) DETAIL A NOTE: .024 (0.60) .016 (0.40) .032 (0.80) TYP 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. 1 Meg x 16 FPM DRAM D51_5V_B.p65 – Rev. B; Pub 3/01 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc.