LH75401/LH75411 System-on-Chip Preliminary data sheet DESCRIPTION • JTAG Debug Interface and Boundary Scan The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices. • Single 3.3 V Supply • LH75401 — contains the superset of features. • 144-pin LQFP Package • LH75411 — similar to LH75401, without CAN 2.0B. • −40°C to +85°C Operating Temperature COMMON FEATURES Unique Features of the LH75401 • Highly Integrated System-on-Chip • Color and Grayscale Liquid Crystal Display (LCD) Controller – 12-bit (4,096) Direct Mode Color, up to VGA – 8-bit (256) Direct or Palettized Color, up to SVGA – 4-bit (16) Direct Mode Color/Grayscale, up to XGA – 12-bit Video Bus – Supports STN, TFT, HR-TFT, and AD-TFT Displays. • ARM7TDMI-S™ Core • High Performance (84 MHz CPU Speed) – Internal PLL Driven or External Clock Driven – Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20 MHz • 32 kB On-chip SRAM – 16 kB Tightly Coupled Memory (TCM) SRAM – 16 kB Internal SRAM • Clock and Power Management – Low Power Modes: Standby, Sleep, Stop • Eight Channel, 10-bit Analog-to-Digital Converter • Integrated Touch Screen Controller • Serial interfaces – Two 16C550-type UARTs supporting baud rates up to 921,600 baud (requires crystal frequency of 14.756 MHz). – One 82510-type UART supporting baud rates up to 3,225,600 baud (requires a system clock of 70 MHz). • 5 V Tolerant Digital I/O – XTALIN and XTAL32IN inputs are 1.8 V ± 10 % • CAN Controller that supports CAN version 2.0B. Unique Features of the LH75411 • Color and Grayscale LCD Controller (LCDC) – 12-bit (4,096) Direct Mode Color, up to VGA – 8-bit (256) Direct or Palettized Color, up to SVGA – 4-bit (16) Direct Mode Color/Grayscale, up to XGA – 12-bit Video Bus – Supports STN, TFT, HR-TFT, and AD-TFT Displays. • Synchronous Serial Port – Motorola SPI™ – National Semiconductor Microwire™ – Texas Instruments SSI • Real-Time Clock (RTC) • Three Counter/Timers – Capture/Compare/PWM Compatibility – Watchdog Timer (WDT) • Low-Voltage Detector Preliminary data sheet 1 LH75401/LH75411 System-on-Chip NXP Semiconductors ORDERING INFORMATION Table 1. Ordering information Package Type number Version Name Description LH75401N0Q100C0 LQFP144 plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 LH75411N0Q100C0 LQFP144 plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 2 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors LH75401 BLOCK DIAGRAM LH75401 14 to 20 MHz 32.768 kHz OSCILLATOR, PLL, POWER MANAGEMENT, and RESET CONTROL INTERNAL 16KB SRAM ARM7TDMI-S AHB INTERFACE TCM 16KB SRAM VECTORED INTERRUPT CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE COLOR LCD CONTROLLER BROWNOUT DETECTOR ADVANCED LCD INTERFACE LINEAR REGULATOR 76-BIT GENERAL PURPOSE I/O I/O CONFIGURATION SYNCHRONOUS SERIAL PORT 4 CHANNEL DMA CONTROLLER STATIC MEMORY CONTROLLER REAL TIME CLOCK TIMER (3) WATCHDOG TIMER CAN 2.0B UART (3) 8 CHANNEL 10-BIT ADC TOUCH PANEL INTERFACE ADVANCED HIGH PERFORMANCE BUS (AHB) ADVANCED PERPHERAL BUS (APB) LH75401-1 Figure 1. LH75401 Block Diagram Preliminary data sheet Rev. 01 — 16 July 2007 3 LH75401/LH75411 System-on-Chip NXP Semiconductors LH75411 BLOCK DIAGRAM LH75411 14 to 20 MHz 32.768 kHz OSCILLATOR, PLL, POWER MANAGEMENT, and RESET CONTROL INTERNAL 16KB SRAM ARM 7TDMI-S AHB INTERFACE TCM 16KB SRAM VECTORED INTERRUPT CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE COLOR LCD CONTROLLER BROWNOUT DETECTOR ADVANCED LCD INTERFACE LINEAR REGULATOR ADVANCED HIGH PERFORMANCE BUS (AHB) 76-BIT GENERAL PURPOSE I/O I/O CONFIGURATION SYNCHRONOUS SERIAL PORT 4 CHANNEL DMA CONTROLLER STATIC MEMORY CONTROLLER REAL TIME CLOCK TIMER (3) WATCHDOG TIMER UART (3) 8 CHANNEL 10-BIT ADC TOUCH PANEL INTERFACE ADVANCED PERPHERAL BUS (APB) LH75411-1 Figure 2. LH75411 Block Diagram 4 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors 109 144 PIN CONFIGURATION 1 108 LH75401/ LH75411 72 73 37 36 002aad207 Figure 3. LH75401/LH75411 pin configuration Preliminary data sheet Rev. 01 — 16 July 2007 5 LH75401/LH75411 System-on-Chip NXP Semiconductors LH75401 Numerical Pin Listing Table 2. LH75401 Numerical Pin List PIN NO. FUNCTION AT RESET FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE BUFFER TYPE BEHAVIOR DURING RESET NOTES 1 PA7 D15 I/O 8 mA Bidirectional Pull-up 1 2 PA6 D14 I/O 8 mA Bidirectional Pull-up 1 3 VDD Power None 4 PA5 D13 I/O 8 mA Bidirectional Pull-up 1 5 PA4 D12 I/O 8 mA Bidirectional Pull-up 1 6 PA3 D11 I/O 8 mA Bidirectional Pull-up 1 7 PA2 D10 Bidirectional Pull-up 1 8 VSS 9 PA1 10 PA0 11 I/O 8 mA Ground None D9 I/O 8 mA Bidirectional Pull-up 1 D8 I/O 8 mA Bidirectional Pull-up 1 VDDC Power None 12 D7 I/O 8 mA Bidirectional Pull-up 13 D6 I/O 8 mA Bidirectional Pull-up 14 VSSC Ground None 15 D5 I/O 8 mA Bidirectional Pull-up 16 D4 I/O 8 mA Bidirectional Pull-up 17 VDD Power None 18 D3 I/O 8 mA Bidirectional Pull-up 19 D2 I/O 8 mA Bidirectional Pull-up 20 D1 I/O 8 mA Bidirectional Pull-up 21 D0 I/O 8 mA Bidirectional Pull-up 22 nWE 8 mA Output HIGH 3 23 nOE 8 mA Output HIGH 3 24 PB5 nWAIT 8 mA Bidirectional Pull-up 1, 3 25 PB4 nBLE1 8 mA Bidirectional Pull-up 1, 3 26 VSS 27 PB3 nBLE0 8 mA Bidirectional Pull-up 1, 3 28 PB2 nCS3 8 mA Bidirectional Pull-up 1, 3 29 PB1 nCS2 8 mA Bidirectional Pull-up 1, 3 30 PB0 nCS1 8 mA Bidirectional Pull-up 1, 3 31 nCS0 8 mA Output Pull-up 3 1 Ground None 32 PC7 A23 8 mA Bidirectional Pull-down 33 PC6 A22 8 mA Bidirectional Pull-down 1 34 VDD 35 PC5 A21 8 mA Bidirectional Pull-down 1 36 PC4 A20 8 mA Bidirectional Pull-down 1 37 PC3 A19 8 mA Bidirectional Pull-down 1 38 PC2 A18 8 mA Bidirectional Pull-down 1 6 Power None Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors Table 2. LH75401 Numerical Pin List (Cont’d) PIN NO. FUNCTION AT RESET FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE BUFFER TYPE BEHAVIOR DURING RESET NOTES 39 PC1 A17 8 mA Bidirectional Pull-down 1 40 PC0 A16 8 mA Bidirectional Pull-down 1 41 VSS Ground None 42 VDD Power None 43 A15 8 mA Output LOW 44 A14 8 mA Output LOW 45 A13 8 mA Output LOW 46 A12 8 mA Output LOW 47 A11 8 mA Output LOW 48 VSS 49 A10 8 mA Output LOW 50 A9 8 mA Output LOW 51 A8 8 mA Output LOW 52 A7 8 mA Output LOW 53 A6 8 mA Output LOW 54 VDD 55 A5 8 mA Output LOW 56 A4 8 mA Output LOW 57 A3 8 mA Output LOW 8 mA Output LOW Ground Power None None 58 A2 59 VSS 60 A1 8 mA Output LOW 61 A0 8 mA Output LOW 62 nRESETIN None Input Pull-up 2, 3 63 TEST2 None Input Pull-up 2 64 TEST1 None Input Pull-up 2 65 TMS None Input Pull-up 2 66 RTCK 8 mA Output 67 TCK None Input 68 TDI None Input Pull-up 2 69 TDO 4 mA Output 70 LINREGEN None Input 5 71 nRESETOUT 8 mA Output 3 72 PD6 INT6 DREQ 6 mA Bidirectional 73 PD5 INT5 DACK 6 mA Bidirectional 74 PD4 INT4 UARTRX1 8 mA Bidirectional Pull-up 1 75 VDDC 76 PD3 INT3 8 mA Bidirectional Pull-up 1 77 PD2 INT2 2 mA Bidirectional Pull-up 1 Ground Power UARTTX1 None Pull-down 1 1, 2 None 78 PD1 INT1 6 mA Bidirectional 1, 2 79 PD0 INT0 2 mA Bidirectional 1 80 VSSC Preliminary data sheet Ground None Rev. 01 — 16 July 2007 7 LH75401/LH75411 System-on-Chip NXP Semiconductors Table 2. LH75401 Numerical Pin List (Cont’d) PIN NO. FUNCTION AT RESET 81 nPOR 82 FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE BUFFER TYPE BEHAVIOR DURING RESET NOTES None Input Pull-up 2, 3 XTAL32IN None Input 83 XTAL32OUT None Output 84 VSSA_PLL Ground None 85 VDDA_PLL Power None 4 86 XTALIN None Input 87 XTALOUT None Output 88 VSSA_ADC 89 AN3 (LR/Y-) PJ7 None Input 90 AN4 (Wiper) PJ6 None Input 91 AN9 PJ5 None Input 92 AN2 (LL/Y+) PJ4 None Input 93 AN8 PJ3 None Input 94 AN1 (UR/X-) PJ2 None Input 95 AN6 PJ1 None Input 96 AN0 (UL/X+) PJ0 None Input 97 VDDA_ADC 98 VDD 99 PE7 SSPFRM 4 mA Bidirectional Pull-up 1 100 PE6 SSPCLK 4 mA Bidirectional Pull-down 1 101 PE5 SSPRX 4 mA Bidirectional Pull-up 1 Ground 4 None Power None Power None 102 PE4 SSPTX 4 mA Bidirectional Pull-down 1 103 PE3 CANTX UARTTX0 8 mA Bidirectional Pull-up 1 104 PE2 CANRX UARTRX0 2 mA Bidirectional Pull-up 1 105 PE1 UARTTX2 4 mA Bidirectional Pull-up 1 106 VSS 107 PE0 UARTRX2 4 mA Bidirectional Pull-up 1 108 PF6 CTCAP2B CTCMP2B 4 mA Bidirectional 109 PF5 CTCAP2A CTCMP2A 4 mA Bidirectional Ground None 110 PF4 CTCAP1B CACMP1B 4 mA Bidirectional 111 PF3 CTCAP1A CTCMP1A 4 mA Bidirectional 112 VDD 113 PF2 CTCAP0E 4 mA Bidirectional 114 PF1 CTCAP0D 4 mA Bidirectional 115 PF0 CTCAP0C 4 mA Bidirectional 116 PG7 CTCAP0B CTCMP0B 4 mA Bidirectional 117 PG6 CTCAP0A CTCMP0A 4 mA Bidirectional 118 PG5 CTCLK 4 mA Bidirectional 119 VSS 120 PG4 LCDVEEEN 121 PG3 LCDVDDEN 122 PG2 LCDDSPLEN 8 Power Ground LCDMOD LCDREV 2 2 None 2 2 2 None 8 mA Bidirectional 8 mA Bidirectional 8 mA Bidirectional Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors Table 2. LH75401 Numerical Pin List (Cont’d) PIN NO. FUNCTION AT RESET FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE BUFFER TYPE 123 PG1 LCDCLS 8 mA Bidirectional 124 PG0 LCDPS 8 mA Bidirectional 125 PH7 LCDDCLK 8 mA Bidirectional 126 VDD Power None 127 VSS Ground None 128 PH6 LCDLP LCDHRLP 8 mA Bidirectional 129 PH5 LCDFP LCDSPS 8 mA Bidirectional LCDSPL 130 PH4 LCDEN 8 mA Bidirectional 131 PH3 LCDVD11 8 mA Bidirectional 132 PH2 LCDVD10 8 mA Bidirectional 133 PH1 LCDVD9 8 mA Bidirectional 134 VDD 135 PH0 LCDVD8 8 mA Bidirectional 136 PI7 LCDVD7 8 mA Bidirectional 137 PI6 LCDVD6 8 mA Bidirectional 138 PI5 LCDVD5 8 mA Bidirectional 139 PI4 LCDVD4 8 mA Bidirectional 140 VSS 141 PI3 LCDVD3 8 mA Bidirectional 142 PI2 LCDVD2 8 mA Bidirectional 143 PI1 LCDVD1 8 mA Bidirectional 144 PI0 LCDVD0 8 mA Bidirectional Power Ground BEHAVIOR DURING RESET NOTES None None NOTES: 1. 2. 3. 4. 5. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. CMOS Schmitt trigger input. Signals preceded with ‘n’ are active LOW. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) LINREGEN activation requires a 0 Ω pull-up to VDD. Preliminary data sheet Rev. 01 — 16 July 2007 9 LH75401/LH75411 NXP Semiconductors System-on-Chip LH75401 Signal Descriptions Table 3. LH75401 Signal Descriptions PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES MEMORY INTERFACE (MI) 1 2 4 5 6 7 9 10 12 13 15 16 18 19 20 21 D[15:0] 22 nWE Output Static Memory Controller Write Enable 23 nOE Output Static Memory Controller Output Enable 24 nWAIT Input 25 nBLE1 27 nBLE0 28 29 Input/Output Data Input/Output Signals 1 2 2 Static Memory Controller External Wait Control 1, 2 Output Static Memory Controller Byte Lane Strobe 1, 2 Output Static Memory Controller Byte Lane Strobe 1, 2 nCS3 Output Static Memory Controller Chip Select 1, 2 nCS2 Output Static Memory Controller Chip Select 1, 2 30 nCS1 Output Static Memory Controller Chip Select 1, 2 31 nCS0 Output Static Memory Controller Chip Select 2 32 33 35 36 37 38 39 40 43 44 45 46 47 49 50 51 52 53 55 56 57 58 60 61 A[23:0] Output Address Signals 1 72 DREQ Input 73 DACK Output DMA CONTROLLER (DMAC) 10 DMA Request 1 DMA Acknowledge 1 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES LCDMOD Output Signal Used by the Row Driver (AD-TFT, HR-TFT only) 1 COLOR LCD CONTROLLER (CLCDC) 120 120 LCDVEEEN Output Analog Supply Enable (AC Bias SIgnal) 1 121 LCDVDDEN Output Digital Supply Enable 1 122 LCDDSPLEN Output LCD Panel Power Enable 1 122 LCDREV Output Reverse Signal (AD-TFT, HR-TFT only) 1 123 LCDCLS Output Clock to the Row Drivers (AD-TFT, HR-TFT only) 1 124 LCDPS Output Power Save (AD-TFT, HR-TFT only) 1 125 LCDDCLK Output LCD Panel Clock 1 128 LCDLP Output Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) 1 128 LCDHRLP Output Latch Pulse (AD-TFT, HR-TFT only) 1 129 LCDFP Output Frame Pulse (STN), Vertical Synchronization Pulse (TFT) 1 129 LCDSPS Output Row Driver Counter Reset Signal (AD-TFT, HR-TFT only) 1 130 LCDEN Output LCD Data Enable 1 130 LCDSPL Output Start Pulse Left (AD-TFT, HR-TFT only) 1 131 132 133 135 136 137 138 139 141 142 143 144 LCDVD[11:0] Output LCD Panel Data bus 1 SYNCHRONOUS SERIAL PORT (SSP) 99 SSPFRM Output SSP Serial Frame 1 100 SSPCLK Output SSP Clock 1 101 SSPRX Input SSP RXD 1 102 SSPTX Output SSP TXD 1 103 UARTTX0 Output UART0 Transmitted Serial Data Output 1 104 UARTRX0 Input UART0 Received Serial Data Input 1 UART0 (U0) UART1 (U1) 74 UARTRX1 Input UART1 Received Serial Data Input 1 76 UARTTX1 Output UART1 Transmitted Serial Data Output 1 105 UARTTX2 Output UART2 Transmitted Serial Data Output 1 107 UARTRX2 Input UART2 Received Serial Data Input 1 UART2 (U2) CONTROLLER AREA NETWORK (CAN) 103 CANTX Output 104 CANRX Input Preliminary data sheet CAN Transmitted Serial Data Output 1 CAN Received Serial Data Input 1 Rev. 01 — 16 July 2007 11 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES ANALOG-TO-DIGITAL CONVERTER (ADC) 89 90 91 92 93 94 95 96 AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) Input ADC Inputs 1 TIMER 0 117 116 115 114 113 CTCAP0[A:E] Input 117 116 CTCMP0[A:B] Output 118 CTCLK Input Timer 0 Capture Inputs 1 Timer 0 Compare Outputs 1 Common External Clock 1 TIMER 1 111 110 CTCAP1[A:B] Input 111 110 CTCMP1[A:B] Output 118 CTCLK Input Timer 1 Capture Inputs 1 Timer 1 Compare Outputs 1 Common External Clock 1 TIMER 2 109 108 CTCAP2[A:B] Input Timer 2 Capture Inputs 1 109 108 CTCMP2[A:B] Input Timer 2 Compare Outputs 1 118 CTCLK Input Common External Clock 1 1 2 4 5 6 7 9 10 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Input/Output General Purpose I/O Signals - Port A 1 24 25 27 28 29 30 PB5 PB4 PB3 PB2 PB1 PB0 Input/Output General Purpose I/O Signals - Port B 1 32 33 35 36 37 38 39 40 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Input/Output General Purpose I/O Signals - Port C 1 GENERAL PURPOSE INPUT/OUTPUT (GPIO) 12 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME 72 73 74 76 77 78 79 PD6 PD5 PD4 PD3 PD2 PD1 PD0 89 90 91 92 93 94 95 96 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 99 100 101 102 103 104 105 107 TYPE DESCRIPTION Input/Output General Purpose I/O Signals - Port D Input NOTES 1 General Purpose I/O Signals - Port J 1 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Input/Output General Purpose I/O Signals - Port E 1 108 109 110 111 113 114 115 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Input/Output General Purpose I/O Signals - Port F 1 116 117 118 120 121 122 123 124 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Input/Output General Purpose I/O Signals - Port G 1 125 128 129 130 131 132 133 135 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Input/Output General Purpose I/O Signals - Port H 1 136 137 138 139 141 142 143 144 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 Input/Output General Purpose I/O Signals - Port I 1 62 nRESETIN RESET, CLOCK, AND POWER CONTROLLER (RCPC) 71 nRESETOUT 72 INT6 Preliminary data sheet Input Output Input User Reset Input 2 System Reset Output 2 External Interrupt Input 6 1 Rev. 01 — 16 July 2007 13 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 73 INT5 Input External Interrupt Input 5 1 74 INT4 Input External Interrupt Input 4 1 76 INT3 Input External Interrupt Input 3 1 77 INT2 Input External Interrupt Input 2 1 78 INT1 Input External Interrupt Input 1 1 79 INT0 Input External Interrupt Input 0 1 81 nPOR Input Power-on Reset Input 2 82 XTAL32IN Input 32.768 kHz Crystal Clock Input 83 XTAL32OUT 86 XTALIN 87 XTALOUT Output Input Output DESCRIPTION NOTES 32.768 kHz Crystal Clock Output Crystal Clock Input Crystal Clock Output TEST INTERFACE 63 TEST2 Input Test Mode Pin 2 64 TEST1 Input Test Mode Pin 1 Input JTAG Test Mode Select Input 65 TMS 66 RTCK Output Returned JTAG Test Clock Output 67 TCK Input JTAG Test Clock Input 68 TDI Input JTAG Test Serial Data Input 69 TDO Output JTAG Test Data Serial Output POWER AND GROUND (GND) 3 17 34 42 54 98 112 126 134 VDD Power I/O Ring VDD 8 26 41 48 59 106 119 127 140 VSS Power I/O Ring VSS 11 75 VDDC Power Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input) 14 80 VSSC Power Core VSS 70 LINREGEN Input Linear Regulator Enable 84 VSSA_PLL Power PLL Analog VSS 85 VDDA_PLL Power PLL Analog VDD Supply 88 VSSA_ADC Power A-to-D converter Analog VSS 97 VDDA_ADC Power A-to-D converter Analog VDD Supply NOTES: 1. These pin numbers have multiplexed functions. 2. Signals preceded with ‘n’ are active LOW. 14 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors LH75411 Numerical Pin Listing Table 4. LH75411 Numerical Pin List PIN NO. FUNCTION AT RESET FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE BUFFER TYPE BEHAVIOR DURING RESET NOTES 1 PA7 D15 I/O 2 PA6 D14 I/O 8 mA Bidirectional Pull-up 1 8 mA Bidirectional Pull-up 1 3 VDD Power None 4 PA5 D13 I/O 8 mA Bidirectional Pull-up 1 5 PA4 D12 I/O 8 mA Bidirectional Pull-up 1 6 PA3 7 PA2 D11 I/O 8 mA Bidirectional Pull-up 1 D10 I/O 8 mA Bidirectional Pull-up 1 8 VSS Ground None 9 PA1 D9 I/O 8 mA Bidirectional Pull-up 1 10 PA0 D8 11 VDDC I/O 8 mA Bidirectional Pull-up 1 Power None 12 D7 I/O 8 mA Bidirectional Pull-up 13 D6 I/O 8 mA Bidirectional Pull-up 14 15 VSSC Ground None D5 I/O 8 mA Bidirectional Pull-up 16 D4 I/O 8 mA Bidirectional Pull-up 17 VDD Power None 18 D3 I/O 8 mA Bidirectional Pull-up 19 D2 I/O 8 mA Bidirectional Pull-up 20 D1 I/O 8 mA Bidirectional Pull-up 21 D0 I/O 8 mA Bidirectional Pull-up 22 nWE 8 mA Output HIGH 3 23 nOE 8 mA Output HIGH 3 24 PB5 nWAIT 8 mA Bidirectional Pull-up 1, 3 25 PB4 nBLE1 8 mA Bidirectional Pull-up 1, 3 26 VSS 27 PB3 nBLE0 8 mA Bidirectional Pull-up 1, 3 28 PB2 nCS3 8 mA Bidirectional Pull-up 1, 3 29 PB1 nCS2 8 mA Bidirectional Pull-up 1, 3 30 PB0 nCS1 8 mA Bidirectional Pull-up 1, 3 31 nCS0 8 mA Output Pull-up 3 32 PC7 A23 8 mA Bidirectional Pull-down 1 33 PC6 A22 8 mA Bidirectional Pull-down 1 34 VDD 35 PC5 A21 8 mA Bidirectional Pull-down 1 36 PC4 A20 8 mA Bidirectional Pull-down 1 37 PC3 A19 8 mA Bidirectional Pull-down 1 38 PC2 A18 8 mA Bidirectional Pull-down 1 39 PC1 A17 8 mA Bidirectional Pull-down 1 40 PC0 A16 8 mA Bidirectional Pull-down 1 41 VSS Ground Preliminary data sheet Power Ground None None None Rev. 01 — 16 July 2007 15 LH75401/LH75411 System-on-Chip NXP Semiconductors Table 4. LH75411 Numerical Pin List (Cont’d) PIN NO. FUNCTION AT RESET 42 VDD 43 A15 44 FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE BUFFER TYPE BEHAVIOR DURING RESET 8 mA Output LOW A14 8 mA Output LOW 45 A13 8 mA Output LOW 46 A12 8 mA Output LOW 47 A11 8 mA Output LOW 48 VSS 49 A10 8 mA Output LOW 50 A9 8 mA Output LOW 51 A8 8 mA Output LOW 52 A7 8 mA Output LOW 53 A6 8 mA Output LOW 54 VDD 55 A5 8 mA Output LOW 56 A4 8 mA Output LOW 57 A3 8 mA Output LOW 8 mA Output LOW Power Ground Power NOTES None None None 58 A2 59 VSS 60 A1 8 mA Output LOW 61 A0 8 mA Output LOW 62 nRESETIN None Input Pull-up 2, 3 63 TEST2 None Input Pull-up 2 64 TEST1 None Input Pull-up 2 65 TMS None Input Pull-up 2 66 RTCK 8 mA Output 67 TCK None Input 68 TDI None Input Pull-up 2 69 TDO 4 mA Output 70 LINREGEN None Input 5 71 nRESETOUT 8 mA Output 3 72 PD6 INT6 DREQ 6 mA Bidirectional 73 PD5 INT5 DACK 6 mA Bidirectional 74 PD4 INT4 UARTRX1 8 mA Bidirectional Pull-up 1 75 VDDC 76 PD3 INT3 8 mA Bidirectional Pull-up 1 77 PD2 INT2 2 mA Bidirectional Pull-up 1 78 PD1 INT1 6 mA Bidirectional 1, 2 79 PD0 INT0 2 mA Bidirectional 1 80 VSSC 81 nPOR None Input 82 XTAL32IN None Input 83 XTAL32OUT None Output 16 Ground Power UARTTX1 Ground None Pull-down 1 1, 2 None None Rev. 01 — 16 July 2007 Pull-up 2, 3 4 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors Table 4. LH75411 Numerical Pin List (Cont’d) PIN NO. FUNCTION AT RESET FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE 84 VSSA_PLL Ground None 85 VDDA_PLL Power None 86 XTALIN BUFFER TYPE None Input None Output 87 XTALOUT 88 VSSA_ADC 89 AN3 (LR/Y-) PJ7 None Input 90 AN4 (Wiper) PJ6 None Input Ground BEHAVIOR DURING RESET NOTES 4 None 91 AN9 PJ5 None Input 92 AN2 (LL/Y+) PJ4 None Input 93 AN8 PJ3 None Input 94 AN1 (UR/X-) PJ2 None Input 95 AN6 PJ1 None Input 96 AN0 (UL/X+) PJ0 None Input 97 VDDA_ADC Power None 98 VDD Power None 99 PE7 SSPFRM 4 mA Bidirectional Pull-up 1 100 PE6 SSPCLK 4 mA Bidirectional Pull-down 1 101 PE5 SSPRX 4 mA Bidirectional Pull-up 1 102 PE4 SSPTX 4 mA Bidirectional Pull-down 1 103 PE3 UARTTX0 8 mA Bidirectional Pull-up 1 104 PE2 UARTRX0 2 mA Bidirectional Pull-up 1 105 PE1 UARTTX2 4 mA Bidirectional Pull-up 1 106 VSS 107 PE0 UARTRX2 4 mA Bidirectional Pull-up 108 PF6 CTCAP2B CTCMP2B 4 mA Bidirectional 109 PF5 CTCAP2A CTCMP2A 4 mA Bidirectional 110 PF4 CTCAP1B CACMP1B 4 mA Bidirectional 111 PF3 CTCAP1A CTCMP1A 4 mA Bidirectional 112 VDD 113 PF2 CTCAP0E 4 mA Bidirectional 114 PF1 CTCAP0D 4 mA Bidirectional 115 PF0 CTCAP0C 4 mA Bidirectional 116 PG7 CTCAP0B CTCMP0B 4 mA Bidirectional 117 PG6 CTCAP0A CTCMP0A 4 mA Bidirectional 118 PG5 CTCLK 4 mA Bidirectional 119 VSS 120 PG4 LCDVEEEN 121 PG3 LCDVDDEN 122 PG2 LCDDSPLEN 123 PG1 LCDCLS 8 mA Bidirectional 124 PG0 LCDPS 8 mA Bidirectional 125 PH7 LCDDCLK 8 mA Bidirectional Ground Power Ground Preliminary data sheet LCDMOD LCDREV None 1 2 2 None 2 2 2 None 8 mA Bidirectional 8 mA Bidirectional 8 mA Bidirectional Rev. 01 — 16 July 2007 17 LH75401/LH75411 System-on-Chip NXP Semiconductors Table 4. LH75411 Numerical Pin List (Cont’d) PIN NO. FUNCTION AT RESET FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE 126 VDD Power None 127 VSS Ground None 128 PH6 129 130 LCDLP LCDHRLP PH5 LCDFP PH4 LCDEN 131 PH3 132 BUFFER TYPE 8 mA Bidirectional LCDSPS 8 mA Bidirectional LCDSPL 8 mA Bidirectional LCDVD11 8 mA Bidirectional PH2 LCDVD10 8 mA Bidirectional 133 PH1 LCDVD9 8 mA Bidirectional 134 VDD 135 PH0 LCDVD8 8 mA Bidirectional 136 PI7 LCDVD7 8 mA Bidirectional 137 PI6 LCDVD6 8 mA Bidirectional 138 PI5 LCDVD5 8 mA Bidirectional 139 PI4 LCDVD4 8 mA Bidirectional 140 VSS 141 PI3 LCDVD3 8 mA Bidirectional 142 PI2 LCDVD2 8 mA Bidirectional 143 PI1 LCDVD1 8 mA Bidirectional 144 PI0 LCDVD0 8 mA Bidirectional Power Ground BEHAVIOR DURING RESET NOTES None None NOTES: 1. 2. 3. 4. 5. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. CMOS Schmitt trigger input. Signals preceded with ‘n’ are active LOW. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) LINREGEN activation requires a 0 Ω pull-up to VDD. 18 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 LH75411 Signal Descriptions Table 5. LH75411 Signal Descriptions PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES MEMORY INTERFACE (MI) 1 2 4 5 6 7 9 10 12 13 15 16 18 19 20 21 D[15:0] 22 nWE Output Static Memory Controller Write Enable 23 nOE Output Static Memory Controller Output Enable 24 nWAIT Input 25 nBLE1 27 nBLE0 28 29 Input/Output Data Input/Output Signals 1 2 2 Static Memory Controller External Wait Control 1, 2 Output Static Memory Controller Byte Lane Strobe 1, 2 Output Static Memory Controller Byte Lane Strobe 1, 2 nCS3 Output Static Memory Controller Chip Select 1, 2 nCS2 Output Static Memory Controller Chip Select 1, 2 30 nCS1 Output Static Memory Controller Chip Select 1, 2 31 nCS0 Output Static Memory Controller Chip Select 2 32 33 35 36 37 38 39 40 43 44 45 46 47 49 50 51 52 53 55 56 57 58 60 61 A[23:0] Output Address Signals 1 72 DREQ Input 73 DACK Output DMA CONTROLLER (DMAC) Preliminary data sheet DMA Request 1 DMA Acknowledge 1 Rev. 01 — 16 July 2007 19 LH75401/LH75411 System-on-Chip NXP Semiconductors Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES LCDMOD Output Signal Used by the Row Driver (AD-TFT, HR-TFT only) 1 COLOR LCD CONTROLLER (CLCDC) 120 120 LCDVEEEN Output Analog Supply Enable (AC Bias SIgnal) 1 121 LCDVDDEN Output Digital Supply Enable 1 122 LCDDSPLEN Output LCD Panel Power Enable 1 122 LCDREV Output Reverse Signal (AD-TFT, HR-TFT only) 1 123 LCDCLS Output Clock to the Row Drivers (AD-TFT, HR-TFT only) 1 124 LCDPS Output Power Save (AD-TFT, HR-TFT only) 1 125 LCDDCLK Output LCD Panel Clock 1 128 LCDLP Output Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) 1 128 LCDHRLP Output Latch Pulse (AD-TFT, HR-TFT only) 1 129 LCDFP Output Frame Pulse (STN), Vertical Synchronization Pulse (TFT) 1 129 LCDSPS Output Row Driver Counter Reset Signal (AD-TFT, HR-TFT only) 1 130 LCDEN Output LCD Data Enable 1 130 LCDSPL Output Start Pulse Left (AD-TFT, HR-TFT only) 1 131 132 133 135 136 137 138 139 141 142 143 144 LCDVD[11:0] Output LCD Panel Data bus 1 SYNCHRONOUS SERIAL PORT (SSP) 99 SSPFRM Output SSP Serial Frame 1 100 SSPCLK Output SSP Clock 1 101 SSPRX Input SSP RXD 1 102 SSPTX Output SSP TXD 1 104 UARTRX0 Input 103 UARTTX0 Output UART0 (U0) UART0 Received Serial Data Input 1 UART0 Transmitted Serial Data Output 1 UART1 (U1) 74 UARTRX1 Input UART1 Received Serial Data Input 1 76 UARTTX1 Output UART1 Transmitted Serial Data Output 1 105 UARTTX2 Output UART2 Transmitted Serial Data Output 1 107 UARTRX2 Input UART2 Received Serial Data Input 1 UART2 (U2) ANALOG-TO-DIGITAL CONVERTER (ADC) 89 90 91 92 93 94 95 96 20 AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) Input ADC Inputs Rev. 01 — 16 July 2007 1 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES TIMER 0 117 116 115 114 113 CTCAP0[A:E] Input 117 116 CTCMP0[A:B] Output 118 CTCLK Input Timer 0 Capture Inputs 1 Timer 0 Compare Outputs 1 Common External Clock 1 TIMER 1 111 110 CTCAP1[A:B] Input 111 110 CTCMP1[A:B] Output 118 CTCLK Input Timer 1 Capture Inputs 1 Timer 1 Compare Outputs 1 Common External Clock 1 TIMER 2 109 108 CTCAP2[A:B] Input Timer 2 Capture Inputs 1 109 108 CTCMP2[A:B] Input Timer 2 Compare Outputs 1 118 CTCLK Input Common External Clock 1 GENERAL PURPOSE INPUT/OUTPUT (GPIO) 1 2 4 5 6 7 9 10 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Input/Output General Purpose I/O Signals - Port A 1 24 25 27 28 29 30 PB5 PB4 PB3 PB2 PB1 PB0 Input/Output General Purpose I/O Signals - Port B 1 32 33 35 36 37 38 39 40 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Input/Output General Purpose I/O Signals - Port C 1 72 73 74 76 77 78 79 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Input/Output General Purpose I/O Signals - Port D 1 Preliminary data sheet Rev. 01 — 16 July 2007 21 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 89 90 91 92 93 94 95 96 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Input 99 100 101 102 103 104 105 107 DESCRIPTION NOTES General Purpose I/O Signals - Port J 1 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Input/Output General Purpose I/O Signals - Port E 1 108 109 110 111 113 114 115 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Input/Output General Purpose I/O Signals - Port F 1 116 117 118 120 121 122 123 124 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Input/Output General Purpose I/O Signals - Port G 1 125 128 129 130 131 132 133 135 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Input/Output General Purpose I/O Signals - Port H 1 136 137 138 139 141 142 143 144 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 Input/Output General Purpose I/O Signals - Port I 1 RESET, CLOCK, AND POWER CONTROLLER (RCPC) 22 62 nRESETIN 71 nRESETOUT 72 INT6 73 INT5 74 76 Input User Reset Input 2 System Reset Output 2 Input External Interrupt Input 6 1 Input External Interrupt Input 5 1 INT4 Input External Interrupt Input 4 1 INT3 Input External Interrupt Input 3 1 77 INT2 Input External Interrupt Input 2 1 78 INT1 Input External Interrupt Input 1 1 79 INT0 Input External Interrupt Input 0 1 Output Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE 81 nPOR Input Power-on Reset Input 82 XTAL32IN Input 32.768 kHz Crystal Clock Input 83 XTAL32OUT 86 XTALIN 87 XTALOUT Output Input Output DESCRIPTION NOTES 2 32.768 kHz Crystal Clock Output Crystal Clock Input Crystal Clock Output TEST INTERFACE 63 TEST2 Input Test Mode Pin 2 64 TEST1 Input Test Mode Pin 1 Input JTAG Test Mode Select Input 65 TMS 66 RTCK Output Returned JTAG Test Clock Output 67 TCK Input JTAG Test Clock Input 68 TDI Input JTAG Test Serial Data Input 69 TDO Output JTAG Test Data Serial Output POWER AND GROUND (GND) 3 17 34 42 54 98 112 126 134 VDD Power I/O Ring VDD 8 26 41 48 59 106 119 127 140 VSS Power I/O Ring VSS 11 75 VDDC Power Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input) 14 80 VSSC Power Core VSS 70 LINREGEN Input Linear Regulator Enable 84 VSSA_PLL Power PLL Analog VSS 85 VDDA_PLL Power PLL Analog VDD Supply 88 VSSA_ADC Power A-to-D converter Analog VSS 97 VDDA_ADC Power A-to-D converter Analog VDD Supply NOTES: 1. These pin numbers have multiplexed functions. 2. Signals preceded with ‘n’ are active LOW. Preliminary data sheet Rev. 01 — 16 July 2007 23 LH75401/LH75411 System-on-Chip NXP Semiconductors TOUCH SCREEN LCD CAN TRANSCEIVER CAN NETWORK CAN 2.0B STN/TFT, AD-TFT/HR-TFT A/D FLASH LH75401 SRAM A/D UART SENSOR ARRAY GPIO 1 2 4 5 7 8 9 * 0 # SSP BOOT ROM 3 6 SERIAL EEPROM KEY MATRIX LH754xx-2A Figure 4. LH75401 System Application Example FUNCTIONAL OVERVIEW ARM7TDMI-S Processor Power Supplies The LH75401/LH75411 microcontrollers feature the ARM7TDMI-S core with an Advanced High-Performance Bus (AHB) 2.0 interface. The ARM7TDMI-S is a 16/32-bit embedded RISC processor and a member of the ARM7 Thumb family of processors. For more information, visit the ARM Web site at www.arm.com. Bus Architecture The LH75401/LH75411 microcontrollers use the ARM Advanced Microcontroller Bus Architecture (AMBA) 2.0 internal bus protocol. Three AHB masters control access to external memory and on-chip peripherals: • The ARM processor fetches instructions and transfers data Five-Volt-tolerant 3.3 V I/Os are employed. The LH75401/LH75411 microcontrollers require a single 3.3 V supply. The core logic requires 1.8 V, supplied by an on-chip linear regulator. Core logic power may also be supplied externally to achieve higher system speeds. See the Electrical Specifications. Clock Sources The LH75401/LH75411 microcontrollers may use two crystal oscillators, or an externally supplied clock. There are two clock trees: • One clock tree drives an internal Phase Lock Loop (PLL) and the three UARTs. It supports a crystal oscillator frequency range from 14 MHz to 20 MHz. • The Direct Memory Access Controller (DMAC) transfers from memory to memory, from peripheral to memory, and from memory to peripheral • The other is a 32.768 kHz oscillator that generates a 1 Hz clock for the RTC. (Use of the 32.768 kHz crystal for the Real Time Clock is optional. If not using the crystal, tie XTAL32IN to VSS and allow XTAL32OUT to float.) • The LCDC refreshes an LCD panel with data from the external memory or from internal memory if the frame buffer is 16 kB or less. The 14-to-20 MHz crystal oscillator drives the UART clocks, so an oscillator frequency of 14.7456 MHz is recommended to achieve modem baud rates. The ARM7TDMI-S processor is the default bus master. An Advanced Peripheral Bus (APB) bridge is provided to access to the various APB peripherals. Generally, APB peripherals are serviced by the ARM core. However, if they are DMA-enabled, they are also serviced by the DMAC to increase system performance while the ARM core runs from local internal memory. The PLL may be bypassed and an external clock supplied at XTALIN; the SoC will operate to DC with the PLL disabled. When doing so, allow XTALOUT to float. The input clock with the PLL bypassed will be twice the desired system operating frequency, and care must be taken not to exceed the maximum input clock voltage. Maximum values for system speeds and input voltages are given in the Electrical Specifications. 24 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors Reset Generation Memory Interface Architecture EXTERNAL RESETS Two external signals generate resets to the ARM7TDMI-S core: The LH75401/LH75411 microcontrollers provide the following data-path management resources on chip: • nPOR sets all internal registers to their default state when asserted. It is used as a Power-On Reset. • 16 kB of zero-wait-state TCM SRAM accessible via processor • nRESETIN sets all internal registers, except the JTAG circuitry, to their default state when asserted. • 16 kB of internal SRAM accessible via processor, DMAC, and LCDC When nPOR is asserted, nRESETIN defines the microcontroller Test Mode. When nPOR is released, nRESETIN behaves during Reset as described previously. • A Static Memory Controller (SMC) that controls access to external memory INTERNAL RESETS There are two types of Internal Resets generated: • System Reset • RTC Reset. System and RTC Resets are asserted by: • An External Reset (a logic LOW signal on the external nRESETIN or nPOR input pin) • A signal from the internal Watchdog Timer • A Soft Reset. The reset latency depends on the PLL lock state. • AHB and APB data buses • A 4-stream general-purpose DMAC. All external and internal system resources are memory-mapped. This memory map partition has three views, based on the setting of the REMAP bits in the Reset, Clock, and Power Controller (RCPC). The second partitioning of memory space is the dividing of the segments into sections. The external memory segment is divided into eight 64 MB sections, of which the first four are used, each having a chip select associated with it. Access to any of the last four sections does not result in an external bus access and does not cause a memory abort. The peripheral register segment is divided into 4 kB peripheral sections, 21 of which are assigned to peripherals. AHB Master Priority and Arbitration The LH75401/LH75411 microcontrollers have three AHB masters: • ARM processor Table 7. Memory Mapping ADDRESS 0x00000000 External Memory Internal SRAM TCM SRAM 0x20000000 Reserved Reserved Reserved 0x40000000 External Memory External Memory External Memory 0x60000000 Internal SRAM Internal SRAM Internal SRAM 0x80000000 TCM SRAM TCM SRAM TCM SRAM • DMAC • LCD Controller. Each AHB master has a priority level that is permanent and cannot change. Table 6. Bus Master Priority PRIORITY BUS MASTER PRIORITY 0xA0000000 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 (Highest) Color LCDC (LH75401 and LH75411) 0xC0000000 2 DMAC 3 (Lowest) ARM7TDMI-S Core (Default) 0xE0000000 0xFFFBFFFF Preliminary data sheet REMAP = 00 REMAP = 01 REMAP = 10 (DEFAULT) Rev. 01 — 16 July 2007 25 LH75401/LH75411 Table 8. APB Peripheral Register Mapping ADDRESS RANGE DEVICE 0xFFFC0000 - 0xFFFC0FFF UART0 (16550) 0xFFFC2000 - 0xFFFC2FFF UART2 (82510) 0xFFFC3000 - 0xFFFC3FFF Analog-to-Digital Converter 0xFFFC4000 - 0xFFFC4FFF Timer Module CAN (LH75401) Reserved (LH75411) 0xFFFC6000 - 0xFFFC6FFF Synchronous Serial Port 0xFFFC7000 - 0xFFFDAFFF Reserved 0xFFFDB000 - 0xFFFDBFFF GPIO4 • Supports Asynchronous Burst Mode read access for Burst Mode ROM devices, with up to 32 independent wait states for read and write accesses • Supports indefinite extended wait states via an external hardware pin (nWAIT) • Supports varied bus turnaround cycles (1 to 16) between a read and write operation Direct Memory Access Controller (DMAC) 0xFFFDC000 - 0xFFFDCFFF GPIO3 One central DMAC services all peripheral DMA requirements for the DMA-capable peripherals listed in Table 9. 0xFFFDD000 - 0xFFFDDFFF GPIO2 0xFFFDE000 - 0xFFFDEFFF GPIO1 0xFFFDF000 - 0xFFFDFFFF GPIO0 The DMA is controlled by the system clock. It has an APB slave port for programming of its registers and an AHB port for data transfers. 0xFFFE0000 - 0xFFFE0FFF Real Time Clock 0xFFFE1000 - 0xFFFE1FFF DMAC 0xFFFE2000 - 0xFFFE2FFF • Supports memory-mapped devices, including Random Access Memory (RAM), Read Only Memory (ROM), Flash, and burst ROM • Supports external bus and external device widths of 8 and 16 bits 0xFFFC1000 - 0xFFFC1FFF UART1 (16550) 0xFFFC5000 - 0xFFFC5FFF System-on-Chip NXP Semiconductors Reset Clock and Power Controller 0xFFFE3000 - 0xFFFE3FFF Watchdog Timer 0xFFFE4000 - 0xFFFE4FFF Advanced LCD Interface 0xFFFE5000 - 0xFFFE5FFF I/O Configuration Peripheral 0xFFFE6000 - 0xFFFEFFFF Reserved Static Random Access Memory Controller The LH75401/LH75411 microcontrollers have 32 kB of Static Random Access Memory (SRAM) organized into two 16 kB blocks: Table 9. DMAC Stream Assignments DMA REQUEST SOURCE DMA STREAM UART1RX (highest priority) Stream0 UART1TX Stream1 UART0RX/External Request (DREQ) Stream2 UART0TX (lowest priority) Stream3 • 16 kB of internal SRAM is available as an AHB slave and accessible via processor, DMAC, and LCDC. DMAC FEATURES • Four data streams that can be used to service: – Four peripheral data streams (peripheral-tomemory or memory-to-peripheral) – Three peripheral data streams and one memoryto-memory data stream. Each memory segment is 512 MB, though the TCM and internal SRAMs are 16 kB each in size. Any access beyond the first 16 kB is mapped to the lower 16 kB, but does not cause a data or prefetch abort. • Three transfer modes: – Memory to Memory (selectable on Stream3) – Peripheral to Memory (all streams) – Memory to Peripheral (all streams). • 16 kB of TCM 0 Wait State SRAM is available to the processor as an ARM7TDMI-S bus slave. • Built-in data stream arbiter Static Memory Controller (SMC) The Static Memory Controller (SMC) is an AMBA AHB slave peripheral that provides the interface between the LH75401/LH75411 microcontrollers and external memory devices. SMC FEATURES • Provides four banks of external memory, each with a maximum size of 16 MB. • Seven programmable registers for each stream • Ability for each stream to indicate a transfer error via an interrupt • 16-word First-In, First Out (FIFO) array, with pack and unpack logic to handle all input/output combinations of byte, half-word, and word transfers • APB slave port allows the ARM core to program DMAC registers • AHB port for data transfers. 26 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors Color LCD Controller (CLCDC) The CLCDC is an AMBA master-slave module that connects to the AHB. It translates pixel-coded data into the required formats and timings to drive single/dual monochrome and color LCD panels. Packets of pixelcoded data are fed, via the AHB interface, to two independently programmable, 32-bit-wide DMA FIFOs. Each FIFO is 16 words deep by 32 bits wide. The CLCDC generates a single combined interrupt to the Vectored Interrupt Controller (VIC) when an interrupt condition becomes true for upper/lower panel DMA FIFO underflow, base address update signification, vertical compare, or bus error. NOTE: LH75401 and LH75411 microcontrollers support full-color operation. CLCDC FEATURES • STN, Color STN, TFT, HR-TFT, and AD-TFT – Fully Programmable Timing Controls – Advanced LCD Interface for displays with a low level of integration, such as HR-TFT and AD-TFT • Programmable Resolution – Up to VGA (640 × 480 DPI), 12-bit Direct Mode Color – Up to SVGA (800 × 600 DPI), 8-bit Direct/Palettized Color – Up to XGA (1,024 × 768 DPI), 4-bit Direct Color/ Grayscale – Direct or Palettized Colors LH75401/LH75411 ADVANCED LCD INTERFACE The Advanced LCD Interface (ALI) allows for direct connection to ultra-thin panels that do not include a timing ASIC. It converts TFT signals from the Color LCD controller to provide the proper signals, timing and levels for direct connection to a panel’s Row and Column drivers for AD-TFT, HR-TFT, or any technology of panel that allows for a connection of this type. The ALI also provides a bypass mode that allows interfacing to the builtin timing ASIC in standard TFT and STN panels. NOTES: 1. The Advanced LCD Interface pertains to the LH75401 and LH75411 microcontrollers. 2. VGA and XGA modes require 66 MHz core speed. Universal Asynchronous Receiver Transmitters (UARTs) The LH75401/LH75411 microcontrollers incorporate three UARTs, designated UART0, UART1, and UART2. UART 0 AND 1 FEATURES • Similar functionality to the industry-standard 16C550 • Supported baud rates up to 921,600 baud (given an external crystal frequency of 14.756 MHz) • Supported character formats: – Data bits per character: 5, 6, 7, or 8 – Parity generation and detection: Even, odd, stick, or none – Stop bit generation: 1 or 2 • Single and Dual Panels • Full-duplex operation • Supports Sharp and non-Sharp Panels • Separate transmit and receive FIFOs, with: – Programmable depth (1 to 16) – Programmable-service ‘trigger levels’ (1/8, 1/4, 1/2, 3/4, and 7/8) – Overrun protection. • CLCDC Outputs Available as General Purpose Inputs/Outputs (GPIOs) if LCDC is Not Needed • Additional Features – Fully programmable horizontal and vertical timing for different display panels – 256-entry, 16-bit palette RAM physically arranged as a 128 × 32-bit RAM – AC bias signal for STN panels and a data-enable signal for TFT panels. • Programmable Panel-related Parameters – STN mono/color or TFT display – Bits-per-pixel – STN 4- or 8-bit Interface Mode – STN Dual or Single Panel Mode – AC panel bias – Panel clock frequency – Number of panel clocks per line – Signal polarity, active HIGH or LOW – Little Endian data format – Interrupt-generation event. Preliminary data sheet • Programmable baud-rate generator that: – Enables the UART input clock to be divided by 16 to 65,535 × 16 – Generates an internal clock common to both transmit and receive portions of the UART. • DMA support • Support for generating and detecting breaks during UART transactions • Loopback testing. Rev. 01 — 16 July 2007 27 LH75401/LH75411 NXP Semiconductors UART 2 FEATURES • Similar functionality to the industry-standard 82510 • Supported baud rates up to 3,225,600 baud (given a system clock of 51.6096 MHz) • 5, 6, 7, 8, or 9 data bits per character • Even, odd, HIGH, LOW, software, or no parity-bit generation and detection • 3/4, 1, 1-1/4, 1-1/2, 1-3/4, or 2 stop-bit generation • µLAN address flag • Full-duplex operation • Separate transmit and receive FIFOs, with programmable depth (1 or 4). Each FIFO has overrun protection and: – Programmable receive trigger levels: 1/4, 1/2, 3/4, or full – Programmable transmit trigger levels: empty, 1/4, 1/2, 3/4. • Two 16-bit baud-rate generators. • One interrupt that can be triggered by transmit and receive FIFO thresholds, receive errors, control character or address marker reception, or timer timeout • Generation and detection of breaks during UART transactions • Support for local loopback, remote loopback, and auto-echo modes • µLAN Address Mode. Timers The LH75401/LH75411 microcontrollers have three 16-bit timers. The timers are clocked by the system clock, but have an internal scaled-down system clock that is used for the Pulse Width Modulator (PWM) and compare functions. All counters are incremented by an internal prescaled counter clock or external clock and can generate an overflow interrupt. All three timers have separate internal prescaled counter clocks, with either a common external clock or a prescaled version of the system clock. • Timer 0 has five Capture Registers and two Compare Registers. • Timer 1 and Timer 2 have two Capture and two Compare Registers each. System-on-Chip The timers support a PWM Mode that uses the two Timer Compare Registers associated with a timer to create a PWM. Each timer can generate a separate interrupt. The interrupt becomes active if any enabled compare, capture, or overflow interrupt condition occurs. The interrupt remains active until all compare, capture, and overflow interrupts are cleared. Real Time Clock (RTC) The RTC is an AMBA slave module that connects to the APB. The RTC provides basic alarm functions or acts as a long-time base counter by generating an interrupt signal after counting for a programmed number of cycles of an RTC input. Counting in 1-second intervals is achieved using a 1 Hz clock input to the RTC. RTC FEATURES • 32-bit up-counter with programmable load • Programmable 32-bit match Compare Register • Software-maskable interrupt that is set when the Counter and Compare Registers have identical values. Controller Area Network (CAN) The CAN 2.0B Controller is an AMBA-compliant peripheral that connects as a slave to the APB. The CAN Controller is located between the processor core and a CAN Transceiver, and is accessed through the AMBA port. CAN communications are performed serially, at a maximum frequency of 1 MB/s, using the TX (transmit) and RX (receive) lines. The TX and RX signals for data transmission and reception provide the communications interface between the CAN Controller and the CAN bus. All peripherals share the TX and RX lines, and always see the common incoming and outgoing data. Bus arbitration follows the CAN 2.0A and CAN 2.0B specifications. The bus is always controlled by the node with the highest priority (lowest ID). Only after the bus has been released can the next highest priority node control it. Transmit and receive errors are handled according to the CAN protocol. Bus timing is critical to the CAN protocol. Therefore, the CAN Controller has two programmable Bus Timing Registers that define timing parameters. NOTE: The CAN Controller pertains to the LH75401 microcontrollers. The Capture Registers have edge-selectable inputs and can generate an interrupt. The Compare Registers can force the compare output pin either HIGH or LOW upon a match. 28 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors CAN 2.0B FEATURES • Full compliance with 2.0A and 2.0B Bosch specifications • Supports 11-bit and 29-bit identifiers • Supports bit rates up to 1Mbit/s LH75401/LH75411 • Touch-pressure sensing circuits • Pen-down sensing circuit and interrupt generator • Voltage-reference generator that is independently controlled • 64-byte receive FIFO • Conversion automation function to minimize controller interrupt overhead • Software-driven bit-rate detection for hot plug-in support • Brownout Detector. • Single-shot transmission option Synchronous Serial Port (SSP) • Acceptance filtering The SSP is a master-only interface for synchronous serial communication with slave peripheral devices that have a Motorola SPI, National Semiconductor Microwire, or Texas Instruments DSP-compatible Synchronous Serial Interface (SSI). • Listen Only Mode • Reception of ‘own’ messages • Error interrupt generated for each CAN bus error • Arbitration-lost interrupt with record of bit position • Read/write error counters • Last error register • Programmable error-limit warning. The SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories. These memories store eight 16-bit values independently in both transmit and receive modes. During transmission: Analog-to-Digital Converter (ADC)/ Brownout Detector • Data writes to the transmit FIFO via the APB interface. The ADC is an AMBA-compliant peripheral that connects as a slave to the APB. The ADC block consists of an 8-channel, 10-bit Analog-to-Digital Converter with integrated Touch Screen Controller. The complete Touch Screen interface is achieved by combining the front-end biasing, control circuitry with analog-to-digital conversion, reference generation, and digital control. • The transmit data is queued for parallel-to-serial conversion onto the transmit interface. The ADC also has a programmable measurement clock derived from the system clock. The clock drives the measurement sequencer and the successiveapproximation circuitry. The ADC includes a Brownout Detector. The Brownout Detector is an asynchronous comparator that compares a divided version of the 3.3 V supply and a bandgap-derived reference voltage. If the supply dips below a Trip point, the Brownout Detector sets a status register bit. The status bit is wired to the VIC and can interrupt the processor core. This allows the Host Controller to warn users of an impending shutdown and may provide the ADC with sufficient time to save its state. ADC/BROWNOUT DETECTOR FEATURES • 10-bit fully differential Successive Approximation Register (SAR) with integrated sample/hold • 8-channel multiplexer for routing user-selected inputs to the ADC in Single Ended and Differential Modes • 16-entry × 16-bit-wide FIFO that holds the 10-bit ADC output and a 4-bit tag number • Front bias-and-control network for Touch Screen interface and support functions compatible with industry-standard 4- and 5-wire touch-sensitive panels Preliminary data sheet • The transmit logic formats the data into the appropriate frame type: – Motorola SPI – National Semiconductor Microwire – Texas Instruments DSP-compatible SSI. SSP FEATURES • SSI in Master Only Mode. The SSP performs serial communications as a master device in one of three modes: – Motorola SPI – Texas Instruments DSP-compatible synchronous serial interface – National Semiconductor Microwire. • Two 16-bit-wide, 8-entry-deep FIFOs, one for data transmission and one for data reception. • Supports interrupt-driven data transfers that are greater than the FIFO watermark. • Programmable clock bit rate. • Programmable data frame size, from 4 to 16 bits long, depending on the size of data programmed. Each frame transmits starting with the most-significant bit. • Four interrupts, each of which can be individually enabled or disabled using the SSP Control Register bits. A combined interrupt is also generated as an OR function of the individual interrupt requests. • Loopback Test Mode. Rev. 01 — 16 July 2007 29 LH75401/LH75411 System-on-Chip NXP Semiconductors Table 10. SSP Modes MODE DESCRIPTION DATA TRANSFERS Motorola SPI For communications with Motorola SPI-compatible Full-duplex, 4-wire devices. Clock polarity and phase are programmable. synchronous SSI For communications with Texas Instruments DSPcompatible Serial Synchronous Interface devices. National Semiconductor For communications with National Semiconductor Microwire Microwire-compatible devices. Watchdog Timer (WDT) The WDT consists of a 32-bit down-counter that allows a selectable time-out interval to detect malfunctions. The timer must be reset by software periodically. Otherwise, a time-out occurs, interrupting the system. If the interrupt is not serviced within the timeout period, the WDT triggers the RCPC to generate a System Reset. If the WDT times out, it sets a bit in the RCPC Reset Status Register. The WDT supports 16 selectable time intervals, for a time-out of 216 through 231 system clock cycles. All Control and Status Registers for the Watchdog Timer are accessed through the APB. 30 Full-duplex, 4-wire synchronous Half-duplex synchronous, using 8-bit control messages WDT FEATURES • Counter generates an interrupt at a set interval and the count reloads from the pre-set value after reaching zero. • Default timeout period is set to the minimum timeout of 216 system clock cycles. • WDT is driven by the APB. • Built-in protection mechanism interrupt-service failure. guards against • WDT can be programmed to trigger a System Reset on a timeout. • WDT can be programmed to trigger an interrupt on the first timeout; then, if the service routine fails to clear the interrupt, the next WDT timeout triggers a System Reset. Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors Vectored Interrupt Controller (VIC) All internal and external interrupts are routed to the VIC, where hardware determines the interrupt priority (see Table 11). The VIC is also where the appropriate signal to the processor (IRQ or FIQ) is generated. The processor services the interrupt as either a vectored interrupt or a default-vectored interrupt. The VIC also accepts software-generated interrupts. Software-generated interrupts use the same enabling control as hardware-generated interrupts. The VIC provides 32 interrupts: • 16 vectored interrupts • 16 or more default-vectored interrupts. • Two used as software interrupts. Any of the 32 interrupt source lines can be assigned to any of the 16 interrupt vectors. Any line not explicitly assigned to an interrupt vector is processed as a default-vectored interrupt. At reset, all 32 lines become default-vectored interrupts. All 32 interrupt source lines can be enabled, disabled, and cleared individually, and individual status can be determined. On reset, all interrupts are disabled. Each interrupt line can be explicitly identified as an IRQ (default) or FIQ interrupt. Vectored-interrupt servicing is only available for IRQ interrupts. The VIC accepts inputs from 32 interrupt source lines: • Seven external • Twenty-three internal Table 11. Interrupt Channels POSITION DESCRIPTION SOURCE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 WDT Not Used ARM7 DBGCOMMRX ARM7 DBGCOMMTX Timer0 Combined Timer1 Combined Timer2 Combined External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 Not Used RTC_ALARM ADC TSCIRQ (combined) ADC BrownOutINTR ADC PenIRQ LCD SSPTXINTR SSPRXINTR SSPRORINTR SSPRXTOINTR SSPINTR UART1 UARTRXINTR UART1 UARTTXINTR UART1 UARTINTR UART0 UARTINTR UART2 Interrupt DMA 31 CAN Watchdog Timer Available as a software interrupt Sourced by the ARM7TDMI-S Core Sourced by the ARM7TDMI-S Core Timer0 Timer1 Timer2 Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Available as a software interrupt Real Time Clock Analog-to-Digital Converter Brown Out Detector Analog-to-Digital Converter LCD Controller Synchronous Serial Port Synchronous Serial Port Synchronous Serial Port Synchronous Serial Port Synchronous Serial Port UART1 UART1 UART1 UART0 UART2 DMA CAN (LH75401) Reserved (LH75411) Preliminary data sheet Rev. 01 — 16 July 2007 31 LH75401/LH75411 System-on-Chip NXP Semiconductors Reset, Clock, and Power Controller (RCPC) The RCPC lets users control System Reset, clocks, power management, and external interrupt conditioning via the AMBA APB interface. This control includes: The state of the TEST1, TEST2, and nRESETIN signals determines the operating mode entered at Poweron Reset (see Table 12). Table 12. Device Operating Modes • Enabling and disabling various clocks • Managing power-down sequencing OPERATING MODE TEST2 TEST1 nRESETIN • Selecting the sources for various clocks. Reserved 0 0 0 The RCPC provides for an orderly start-up until the crystal oscillator stabilizes and the PLL acquires lock. If users want to change the system clock frequency during normal operation, the RCPC ensures a seamless transition between the old and new frequencies. PLL Bypass 0 0 1 Reserved 0 1 x Reserved 1 0 0 EmbeddedICE 1 0 1 Normal 1 1 x RCPC FEATURES • Manages five Power Modes for minimizing power consumption: Active, Standby, Sleep, Stop1, and Stop2 • Generates the system clock (HCLK) from either the PLL clock or the PLL-bypassed (oscillator) clock, divided by 2, 4, 6, 8, … 30 NOTE: TEST1, TEST2, and nRESETIN are latched on the rising edge of nPOR. The microcontroller stays in that operating mode until power is removed or nPOR transitions from LOW to HIGH. General Purpose Input/Output (GPIO) • Generates three UART clocks from oscillator clock The LH75401/LH75411 microcontrollers have 10 GPIO ports: • Generates the 1 Hz RTC clock • Seven 8-bit ports • Generates the SSP and LCD clocks from HCLK, divided by 1, 2, 4, 8, 16, 32, or 64 • Two 7-bit ports • Provides a selectable external clock output The GPIO ports are designated A through J and provide 76 bits of programmable input/output (see Table 13). Pins of all ports, except Port J, can be configured as inputs or outputs. Port J is input only. Upon System Reset, all ports default to inputs. • Generates system and RTC Resets based on an external reset, Watchdog Timer reset, or soft reset • Configures seven HIGH/LOW-level or rising/falling edge-trigger external interrupts and converts them to HIGH-level trigger interrupt outputs required by the VIC • Generates remap outputs used by the memory map decoder • One 6-bit port. Table 13. GPIO Ports PORT PROGRAMMABLE PINS • Provides an identification register A 8 Input/Output Pins • Supports external or watchdog reset status. B 6 Input/Output Pins C 8 Input/Output Pins D 7 Input/Output Pins E 8 Input/Output Pins F 7 Input/Output Pins G 8 Input/Output Pins H 8 Input/Output Pins I 8 Input/Output Pins J 8 Input Pins Operating Modes The LH75401/LH75411 microcontrollers support three operating modes: • Normal Mode • PLL Bypass Mode, where the internal PLL is bypassed and an external clock source is used; otherwise the chip operates normally • EmbeddedICE Mode, where the JTAG port accesses the TAP Controller in the core and the core is placed in Debug Mode. 32 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors Device Pin Multiplexing Table 14. LCD Panel Signal Multiplexing 4-BIT STN (MONOCHROME) EXTERNAL PIN LVCVD11 SINGLE PANEL DUAL PANEL 8-BIT STN SINGLE PANEL (MONOCHROME) Reserved MLSTN3 Reserved LVCVD10 Reserved MLSTN2 Reserved LVCVD9 Reserved MLSTN1 Reserved LVCVD8 Reserved MLSTN0 Reserved LVCVD7 Reserved Reserved MUSTN7 LVCVD6 Reserved Reserved MUSTN6 LVCVD5 Reserved Reserved MUSTN5 LVCVD4 Reserved Reserved MUSTN4 LVCVD3 MUSTN3 MUSTN3 MUSTN3 LVCVD2 MUSTN2 MUSTN2 MUSTN2 LVCVD1 MUSTN1 MUSTN1 MUSTN1 LVCVD0 MUSTN0 MUSTN0 MUSTN0 NOTES: 1. MUSTN = Mono upper panel STN, dual and/or single panel. 2. MLSTN = Mono lower panel STN, dual panel only. Table 15. LCD External Pin Multiplexing (LH75401 and LH75411) EXTERNAL PIN DEFAULT MODE (NO LCD) 4-BIT MONO STN MODE SINGLE DUAL 8-BIT STN MODE TFT MODE ALI MODE PG4/LCDVEEEN/LCDMOD PG4 LCDVEEEN LCDVEEEN LCDVEEEN LCDVEEEN LCDMOD PG3/LCDVDDEN PG3 LCDVDDEN LCDVDDEN LCDVDDEN LCDVDDEN LCDVDDEN PG2/LCDDSPLEN/LCDREV PG2 LCDDSPLEN LCDDSPLEN LCDDSPLEN LCDDSPLEN LCDREV PG1/LCDCLS PG1 PG1 PG1 PG1 PG1 LCDCLS PG0/LCDPS PG0 PG0 PG0 PG0 PG0 LCDPS PH7/LCDDCLK PH7 LCDDCLK LCDDCLK LCDDCLK LCDDCLK LCDDCLK PH6/LCDLP/LCDHRLP PH6 LCDLP LCDLP LCDLP LCDLP LCDLP PH5/LCDFP/LCDSPS PH5 LCDFP LCDFP LCDFP LCDFP LCDFP PH4/LCDEN/LCDEN PH4 LCDEN LCDEN LCDEN LCDEN LCDEN PH3/LCDVD11 PH3 PH3 MLSTN3 PH3 LCDVD11 LCDVD11 PH2/LCDVD10 PH2 PH2 MLSTN2 PH2 LCDVD10 LCDVD10 PH1/LCDVD9 PH1 PH1 MLSTN1 PH1 LCDVD9 LCDVD9 PH0/LCDVD8 PH0 PH0 MLSTN0 PH0 LCDVD8 LCDVD8 PI7/LCDVD7 PI7 PI7 PI7 STN7 LCDVD7 LCDVD7 PI6/LCDVD6 PI6 PI6 PI6 STN6 LCDVD6 LCDVD6 PI5/LCDVD5 PI5 PI5 PI5 STN5 LCDVD5 LCDVD5 PI4/LCDVD4 PI4 PI4 PI4 STN4 LCDVD4 LCDVD4 PI3/LCDVD3 PI3 MUSTN3 MUSTN3 STN3 LCDVD3 LCDVD3 PI2/LCDVD2 PI2 MUSTN2 MUSTN2 STN2 LCDVD2 LCDVD2 PI1/LCDVD1 PI1 MUSTN1 MUSTN1 STN1 LCDVD1 LCDVD1 PI0/LCDVD0 PI0 MUSTN0 MUSTN0 STN0 LCDVD0 LCDVD0 Preliminary data sheet Rev. 01 — 16 July 2007 33 LH75401/LH75411 System-on-Chip NXP Semiconductors ELECTRICAL SPECIFICATIONS Table 16. Absolute Maximum Ratings PARAMETER MINIMUM MAXIMUM DC Core Supply Voltage (VDDC) -0.3 V 2.4 V DC I/O Supply Voltage (VDD) -0.3 V 4.6 V DC Analog Supply Voltage for ADC (VDDA0) -0.3 V 4.6 V DC Analog Supply Voltage for PLL (VDDA1) -0.3 V 2.4 V Storage Temperature (TSTG) -55°C 125°C NOTE: These ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Table 17. Recommended Operating Conditions PARAMETER MINIMUM TYP. MAXIMUM NOTES DC Core Supply Voltage (VDDC) (Linear Regulator disabled) 1.7 V 1.8 V 1.98 V 1 DC Analog Supply Voltage for ADC (VDDA0) 3.0 V 3.3 V 3.6 V DC I/O Supply Voltage (VDD) 3.0 V 3.3 V 3.6 V 1 DC Analog Supply Voltage for PLL (VDDA1) 1.7 V 1.8 V 1.98 V 2 Clock Frequency (ƒHCLK) 4.375 MHz 84 MHz 3, 4, 5 Clock Period (tHCLK) 11.9047 ns 228.571 ns 3, 4, 5 14 MHz 20 MHz 4, 5 Crystal Frequency −40°C Industrial Operating Temperature 25°C 85°C NOTES: 1. Core Voltage should never exceed I/O Voltage after initial power up. See the section titled ‘Power Supply Sequencing’. 2. Connect VDDA1 to VDDC when using the on-chip linear regulator. 3. On-chip Linear regulator enabled. When the on-chip linear regulator is enabled, Core power is drawn from VDD – allow VDDC pins to float. 4. Will operate to DC with PLL disabled. Core frequencies greater than 84 MHz require external clock and VDDC. Core frequencies faster than 70 MHz require an externally-supplied clock. 5. Processor is functional at minimum frequency, but not all peripherals may be enabled. 6. The maximum operating frequency is the crystal frequency × 3.5. Table 18. Clock Frequency vs. Voltages (VDDC) vs. Temperature PARAMETER 25°C 70°C 85°C 1.7 V 1.8 V 1.9 V Clock Frequency (ƒHCLK) 91.3 MHz 97 MHz 103.7 MHz Clock Period (tHCLK) 10.952 ns 10.309 ns 9.643 ns Clock Frequency (ƒHCLK) Clock Period (tHCLK) Clock Frequency (ƒHCLK) Clock Period (tHCLK) 86 MHz 92 MHz 97.4 MHz 11.627 ns 10.869 ns 10.266 ns 84 MHz 90 MHz 95.2 MHz 11.9047 ns 11.111 ns 10.504 ns NOTES: 1. On-chip Linear regulator and PLL disabled; VDDC supplied externally. 2. Core speeds greater than 84 MHz require external VDDC and may not yield proper UART baud rates. 3. Core speeds greater than 70 MHz require an external clock. 4. Additional performance may be achieved in accordance with Figure 5. 34 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors 110 105 100 Frequency (MHz) 2V 1.95 V 95 1.9 V 1.85 V 90 1.8 V 1.75 V 85 1.7 V 1.65 V 80 1.6 V 75 70 25 35 45 55 65 75 85 Temp (˚Celsius) LH754xx-106 Figure 5. Maximum Core Frequency versus Voltage and Temperature Very Low Operating Temperatures and Noise Immunity The junction temperature, Tj, is the operating temperature of the transistors in the integrated circuit. The switching speed of the CMOS circuitry within the SoC depends partly on Tj, and the lower the operating temperature, the faster the CMOS circuits will switch. Increased switching noise generated by faster switching circuits could affect the overall system stability. The amount of switching noise is directly affected by the application executed on the SoC. NXP recommends that users implementing a system to meet low industrial temperature standards should use an external oscillator rather than a crystal to drive the system clock input of the System-on-Chip. This change from crystal to oscillator will increase the robustness (i.e., noise immunity of the clock input to the SoC. Preliminary data sheet Rev. 01 — 16 July 2007 35 LH75401/LH75411 System-on-Chip NXP Semiconductors DC Characteristics All characteristics are specified over an operating temperature of −40°C to +85°C, and at minimum and maximum supply voltages. Table 19. DC Characteristics SYMBOL PARAMETER MIN. TYP. MAX. UNIT VIH CMOS Input HIGH Voltage VIL CMOS Input LOW Voltage VT+ Schmitt Trigger Positive Going Threshold VT- Schmitt Trigger Negative Going Threshold Vhst Schmitt Trigger Hysteresis 0.35 V Output Drive 1 2.6 V IOH = -2 mA Output Drive 2 2.6 V IOH = -4 mA Output Drive 3 2.6 V IOH = -6 mA Output Drive 4 2.6 V IOH = -8 mA VOH VOL 2.0 CONDITIONS NOTES V 0.8 V 2.0 1 V 0.8 V Output Drive 1 0.4 V IOL = 2 mA Output Drive 2 0.4 V IOL = 4 mA Output Drive 3 0.4 V IOL = 6 mA Output Drive 4 0.4 V IOL = 8 mA XTAL32IN External Clock Input 1.62 1.8 1.98 V Externally supplied XTALIN External Clock Input 1.62 1.8 1.98 V Externally supplied IIN Input Leakage Current -10 10 µA VIN = VDD or GND IACTIVE Active Current 70 mA 2 2 50 ISTANDBY Standby Current 45 mA ISLEEP Sleep Current 4.0 mA ISTOP1 Stop1 Current 3.0 mA ISTOP2 Stop2 Current (RTC ON) 35 µA 3 120 µA 4 ISTOP2 Stop2 Current (RTC OFF) 23 µA 3 100 µA 4 3. Using external 1.8 V supply, internal regulator disabled. 4. Using Internal linear regulator. NOTES: 1. VIL MAX. = 0.5 V for pin TCK with 50 pF load. 2. Running a Typical Application at 51.6 MHz. Table 20. Linear Regulator DC Characteristics SYMBOL IQUIESCENT PARAMETER MIN. Quiescent Current MAX. Current when Regulator is Disabled IOLR Output Current Range VOLR Output Voltage RPULL Pull-up Resistor µA 8 0.0 UNIT µA 75 ISLEEPLR 36 TYP. 100 1.84 V 0 Rev. 01 — 16 July 2007 mA Ω Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors Analog-To-Digital Converter Electrical Characteristics Table 21 shows the derated specifications for extended temperature operation. See Figure 6 for the ADC transfer characteristics. Table 21. ADC Electrical Characteristics at Industrial Operating Range PARAMETER MIN. TYP. MAX. UNITS 10 Bits A/D Resolution 10 Throughput Conversion 17 CLK Cycles Acquisition Time 3 CLK Cycles Clk Period NOTES 1 500 5,000 ns Differential Non-Linearity -0.99 4.5 LSB Integral Non-Linearity -3.5 +3.5 LSB Offset Error -35 +35 mV Gain Error -4.0 4.0 LSB On-chip Voltage Reference (VREF) 1.85 2.0 2.15 V Negative Reference Input (VREF-) VSSA VSSA (VREF+) -1.0 V 2 Positive Reference Input (VREF+) (VREF-) +1.0 VREF VDDA V 2 Crosstalk between channels Analog Input Voltage Range -60 VDDA V Analog Input Current 5 µA Reference Input Current 5 µA Analog input capacitance 15 pF 3.6 V Operating Supply Voltage 0 dB 3.0 Operating Current, VDDA 590 µA Standby Current 180 µA Stop Current, VDDA <1 µA Brown Out Trip Point 2.63 V Brown Out Hysterisis 120 mV Operating Temperature −40 85 3 4 °C NOTES: 1. The analog section of the ADC takes 16 × A2DCLK cycles per conversion, plus 1 × A2DCLK cycles to be made available in the PCLK domain. An additional 3 × PCLK cycles are required before being available on the APB. 2. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer, alternative low impedance (RS < 500) voltages can be selected as reference voltages. The range of voltages allowed are specified above. However, the on-chip reference cannot drive the ADC unless the reference buffer is switched on. 3. The analog input pins can be driven anywhere between the power supply rails. If the voltage at the input to the ADC exceeds VREF+ or is below VREF-, the A/D result will saturate appropriately at positive or negative full scale. Trying to pull the analog input pins above or below the power supply rails will cause protection diodes to be forward-biased, resulting in large current source/sink and possible damage to the ADC. 4. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down. Preliminary data sheet Rev. 01 — 16 July 2007 37 LH75401/LH75411 NXP Semiconductors System-on-Chip OFFSET GAIN ERROR ERROR 1024 1023 1022 1021 1020 1019 1018 IDEAL TRANSFER CURVE 9 8 CENTER OF A STEP OF THE ACTUAL TRANSFER CURVE 7 ACTUAL TRANSFER CURVE 6 5 INTEGRAL NON-LINEARITY 4 3 2 1 1 OFFSET ERROR 2 3 4 5 6 7 8 9 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 LSB DNL 754xx-54 Figure 6. ADC Transfer Characteristics 38 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors POWER SUPPLY SEQUENCING When using an external 1.8 V supply (instead of the internal 1.8 V regulator), the external 1.8 V power supply must be energized before the 3.3 V supply. Otherwise, the 1.8 V supply may not lag the 3.3 V supply by more than 10 µs. If a longer delay time is needed, the voltage difference between the two power supplies must be within 1.5 V during power supply ramp up. To avoid a potential latchup condition, voltage should be applied to input pins only after the device is powered-on as described above. LINEAR REGULATOR Although this device contains an on-board regulator, using its output to power external devices is not recommended. External loads can affect the regulator’s stability and introduce noise into the supply. NXP cannot guarantee device performance at rated speeds and temperatures with external loads connected to this supply. CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make this data more usable, the values presented in Table 22 were derived under the conditions presented here. PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 23 shows the typical current consumption for each of the on-board peripheral blocks. The values were determined with the peripheral clock running at maximum frequency, typical conditions, and no I/O loads. This current is supplied by the 1.8 V power supply. Table 22. Current Consumption by Mode SYMBOL PARAMETER ACTIVE MODE ICHIP Chip Current with Linear Regulator 50.2 mA ICORE Core Current without Linear Regulator 42.1 mA 5 mA 1.3 mA IIO I/O Current without Linear Regulator IANALOG Analog Current STANDBY MODE (TYPICAL CONDITIONS ONLY) ICHIP Core Current with Linear Regulator 42.7 mA ICORE Core Current without Linear Regulator 34.6 mA Current drawn by I/O 0.8 mA 1.3 mA IIO IANALOG Analog Current SLEEP MODE (TYPICAL CONDITIONS ONLY) ICHIP Core Current with Linear Regulator 3.9 mA ICORE Core Current without Linear Regulator 2.5 mA Current drawn by I/O 400 µA 1.2 mA 2.96 mA 34 µA 18 µA IIO Maximum Specified Value TYP. UNITS IANALOG Analog Current The values specified in the MAXIMUM column were determined using these operating characteristics: STOP1 MODE ISTOP Core Current with Linear Regulator, I/O, and 14.7456 MHz osc. ILEAK Leakage Current, Core and I/O • All IP blocks either operating or enabled at maximum frequency and size configuration • Core operating at maximum power configuration STOP2 MODE (RTC ON) STOP2 MODE (RTC OFF) • All I/O loads at maximum (50 pF) ILEAK • All voltages at maximum specified values • Maximum specified ambient temperature. Typical The values in the TYPICAL column were determined using a ‘typical’ application under ‘typical’ environmental conditions and the following operating characteristics: Leakage Current, Core and I/O NOTES: 1. ICHIP = Chip Current with Linear Regulator (Core + I/O) 2. ICORE, IIO, IANALOG are the respective current consumption specifications for VDDC, VDD, and VDDA. Table 23. Peripheral Current Consumption • SPI, Timer, and UART peripherals operating; all other peripherals disabled PERIPHERAL TYPICAL UNITS UARTs 200 µA • LCD enabled with 320 × 240 × 16-bit color, 60 Hz refresh rate RTC 5 µA DMA 4.1 mA • I/O loads at nominal • FCLK = 51.6 MHz; HCLK = 51.6 MHz SSP 500 µA Counter/Timers 200 µA LCD 2.2 mA • All voltages at typical values • Nominal case temperature. Preliminary data sheet Rev. 01 — 16 July 2007 39 LH75401/LH75411 System-on-Chip NXP Semiconductors AC Characteristics All signal transitions are measured from the 50 % point of the signal. Table 24. Memory Interface Signals SIGNAL I/O LOAD PARAMETER D[15:0] Out 50 pF tOVD D[15:0] Out 50 pF tOHD MINIMUM MAXIMUM COMMENTS tHCLK + 8 ns Data output valid following address valid 3 × tHCLK – 6 ns Data output invalid following address valid 2 tHCLK – 18 ns Data input valid following address valid D[15:0] In nCS3 - nCS0 tIDD 2 × tHCLK – 18 ns Data Input Valid, following + (nWAIT –1) Address Valid (nWAIT states) × tHCLK Out 30 pF tOVCS tHCLK + 6 ns nCS output valid following address valid nCS3 -nCS0 Out 30 pF tOHCS nOE Out 30 pF tOVOE tHCLK + 10 ns nOE output valid following address valid nOE Out 30 pF tOHOE nBLE1 - nBLE0 Out 30 pF tOVBE nBLE1 - nBLE0 Out 30 pF tOHBER 3 × tHCLK – 6 ns nBLE output invalid following address valid, read cycle nBLE1 - nBLE0 Out 30 pF tOHBEW 2 × tHCLK – 6 ns nBLE output invalid following address valid, write cycle 3 × tHCLK – 6 ns nCS output invalid following address valid 3 × tHCLK – 6 ns nOE output invalid following address valid tHCLK + 10 ns nWE Out 30 pF tOVWE nWE Out 30 pF tOHWE 2 × tHCLK – 6 ns 2 tHCLK – 2.2 ns nWE output invalid following address valid tIVWAIT 2 tHCLK – 18 ns nWAIT input valid following address valid nWAIT In tHCLK + 10 ns nBLE output valid following address valid nWE output valid following address valid NOTE: The values in Table 24 represent the timing with no internal arbitration delay and 1 wait state memory access. This is the worst case (fastest) timing. Table 25. Synchronous Serial Port SIGNAL I/O LOAD PARAMETER SSPFRM Out 50 pF tOVSSPFRM SSPTX Out 50 pF tOVSSPTX SSPRX In tISSPRX MIN. MAX. COMMENT 14 ns SSPFRM output valid, referenced to SSPCLK 12 ns SSPTX output valid, referenced to SSPCLK 22 ns SSPRX input valid, referenced to SSPCLK Table 26. Power-up Stabilization PARAMETER 40 DESCRIPTION TYP. MAX. UNIT tLREG Linear regulator stabilization time after power-up 200 µs tOSC32 Oscillator stabilization time after Power Up (VDDC = VDDCMIN) 550 ms tOSC14 Oscillator stabilization time after Power Up (VDDC = VDDCMIN) 2.5 ms tRSTOV nPOR LOW to nPOR valid (once sampled LOW) tPORH nPOR hold extend to allow PLL to lock once XTAL is stable Rev. 01 — 16 July 2007 3.5 HCLK 10 µs Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 VDDmin VDD tOSC32 PLL XTAL32 XTAL14 tOSC14 LREG tPORH VDDCmin tLREG nPOR LH754xx-100 Figure 7. Power-up Stabilization MEMORY CONTROLLER WAVEFORMS Static Memory Controller Waveforms Figure 8 shows the waveform and timing for an External Static Memory Write, with one Wait State. Figure 9 shows the waveform and timing for an External Static Memory Write, with two Wait States. Figure 10 shows the waveform and timing for an External Static Memory Read, with one Wait State. The SMC supports an nWAIT input that can be used by an external device to extend the wait time during a memory access. The SMC samples nWAIT at the beginning of at the beginning of each system clock cycle. The system clock cycle in which the nCSx signal is asserted counts as the first wait state. See Figure 11. The SMC recognizes that nWAIT is active within 2 clock cycles after it has been asserted. To assure that the current access (read or write) will be extended by nWAIT, program at least two wait states for this bank of Preliminary data sheet memory. If N wait states are programmed, the SMC holds this state for N system clocks or until the SMC detects that nWAIT is inactive, whichever occurs last. As the number of wait states programmed increases, the amount of delay before nWAIT must be asserted also increases. If only 2 wait states are programmed, nWAIT must be asserted in the clock cycle immediately following the clock cycle during which the nCSx signal is asserted. Once the SMC detects that the external device has deactivated nWAIT, the SMC completes its access in 3 system clock cycles. The formula for the allowable delay between asserting nCSx and asserting nWAIT is: tASSERT = (system clock period) × (Wait States - 1) (where Wait States is from 2 to 31.) The signal tIDD is shown without a setup time, as measurements are made from the Address Valid point and HCLK is an internal signal, shown for reference only. Rev. 01 — 16 July 2007 41 42 HCLK Rev. 01 — 16 July 2007 tOHBEW tOHWE NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active. tOVBE tOVWE tOVCS tOVD tOHCS tOHD DATA ADDRESS LH754xx-40 NXP Semiconductors nOE (See Note 2) nBLE[1:0] nWAIT nWE nCSx D[15:0] A[23:0] (See Note 1) 1 WAIT STATE LH75401/LH75411 System-on-Chip Figure 8. External Static Memory Write, One Wait State Preliminary data sheet Preliminary data sheet Rev. 01 — 16 July 2007 NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active. tOVBE tOVWE tOVCS tOVD tOHBEW tOHWE tOHCS tOHD ADDRESS DATA LH754xx-42 NXP Semiconductors nOE nBLE[1:0] (See Note 2) nWAIT nWE nCSx D[15:0] A[23:0] HCLK (See Note 1) 2 WAIT STATES System-on-Chip LH75401/LH75411 Figure 9. External Static Memory Write, Two Wait States 43 44 HCLK Rev. 01 — 16 July 2007 tOVOE tOVBE tOVCS tIDD ADDRESS tOHOE tOHBER tOHCS DATA DATA CAPTURED LH754xx-45 NXP Semiconductors NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active. nOE (See Note 2) nBLE[1:0] nWAIT nWE nCSx D[15:0] A[23:0] (See Note 1) 1 WAIT STATE LH75401/LH75411 System-on-Chip Figure 10. External Static Memory Read, One Wait State Preliminary data sheet Preliminary data sheet HCLK Rev. 01 — 16 July 2007 tIVWAIT ADDRESS DATA CAPTURED DATA LH754xx-47 NXP Semiconductors NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active. nOE (See Note 2) nBLE[1:0] nWAIT nWE nCSx D[15:0] A[23:0] (See Note 1) System-on-Chip LH75401/LH75411 Figure 11. External Static Memory Read, nWAIT Active 45 LH75401/LH75411 System-on-Chip NXP Semiconductors SSPRX tISSPRX SSPTX SSPFRM SSPCLK tOVSSPTX tOVSSPFRM 754xx-49 Synchronous Serial Port Waveform Figure 12. Synchronous Serial Port Waveform 46 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors DMA Controller Timing Diagrams SoSize = DeSize and SoBurst = 4. Figure 13 and Figure 14 show examples of DMA timing diagrams. • Figure 14 shows the timing for a memory-to-peripheral data transfer, where SoSize = DeSize and SoBurst = 4. Md3 Md2 Md1 Md0 Pd3 Pd2 Pd1 nWE nCS1 nCS0 Pd0 D[15:0] A[23:0] DACK DREQ Pa0 Pa1 Pa2 Pa3 Ma0 Ma1 Ma2 Ma3 LH754xx-10 • Figure 13 shows the timing for a peripheral-to-memory data transfer, where Figure 13. Peripheral-to-Memory Data-Transfer Timing Preliminary data sheet Rev. 01 — 16 July 2007 47 LH75401/LH75411 System-on-Chip Pd3 Pd2 Pd1 Pd0 Md3 Md2 Md1 nWE nCS1 nCS0 Md0 D[15:0] A[23:0] DACK DREQ Ma0 Ma1 Ma2 Ma3 Pa0 Pa1 Pa2 Pa3 LH754xx-11 NXP Semiconductors Figure 14. Memory-to-Peripheral Data-Transfer Timing 48 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors Color LCD Controller Timing Waveforms This section describes typical output waveform diagrams for the CLCDC and the Advanced LCD Interface. STN HORIZONTAL TIMING Figure 15 shows typical horizontal timing waveforms for STN panels. In this figure, the CLCDC Clock (an input to the CLCDC) is scaled within the CLCDC and used to produce the LCDDCLK output. Programmable registers in the CLCDC set the timings (in terms of LCDDCLK pulses) to produce the other signals that control an STN display. For example, Figure 15 shows that the duration of the LCDLP signal is controlled by Timing0:HSW (the HSW bit field in the Timing0 Register). Figure 15 also shows that the polarity of the LCDLP signal is set by Timing2:IHS. LH75401/LH75411 TFT HORIZONTAL TIMING Figure 17 shows typical horizontal timing waveforms for TFT panels. TFT VERTICAL TIMING Figure 18 shows typical vertical timing waveforms for TFT panels. AD-TFT/HR-TFT HORIZONTAL TIMING WAVEFORMS Figure 19 shows typical horizontal timing waveforms for AD-TFT and HR-TFT panels. The ALI adjusts the normal TFT timing to accommodate these panels. AD-TFT/HR-TFT VERTICAL TIMING WAVEFORMS Figure 20 shows typical vertical timing waveforms for AD-TFT and HR-TFT panels. The power sequencing and register information is the same as for TFT vertical timing. STN VERTICAL TIMING Figure 16 shows typical vertical timing waveforms for STN panels. Preliminary data sheet Rev. 01 — 16 July 2007 49 50 Rev. 01 — 16 July 2007 LCDDCLK IS SUPPRESSED DURING LCDLP TIMING0:HSW ENUMERATED IN 'LCDDCLKS' HORIZONTAL BACK PORCH TIMING0:HBP D001 D002 ONE 'LINE' OF LCD DATA D.... 16 × (TIMING0:PPL+1) DNNN ENUMERATED IN 'LCDDCLKS' HORIZONTAL FRONT PORCH TIMING0:HFP LH754xx-77 NXP Semiconductors NOTES: 1. The CLCDC clock (from the RCPC) is scaled within the CLCDC and used to produce the LCDDCLK output. CLCDC registers set timing (in terms of LCDDCLK pulses) to produce the other signals that control an STN display. 2. The duration ot the LCDLP signal is controlled by TIMING0:HSW (the HSW bit field in the TIMING0 Register). 3. The polarity of the LCDLP signal is set by TIMING2:IHS. LCDVD[11:0] (PANEL DATA) THE ACTIVE DATA LINES WILL VARY WITH THE TYPE OF STN PANEL: 4-BIT, 8-BIT, COLOR, OR MONO LCDDCLK (PANEL CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDLP (LINE SYNCHRONIZATION PULSE) TIMING2:IHS CLCDC CLOCK (INTERNAL) APBPERIPHCLKCTRL1:LCD CLKPRESCALE:LCDPS 1 STN HORIZONTAL LINE LH75401/LH75411 System-on-Chip Figure 15. STN Horizontal Timing Diagram Preliminary data sheet Preliminary data sheet Rev. 01 — 16 July 2007 Timing1: VSW Timing1: VBP ENUMERATED IN HORIZONTAL 'LINES' BACK PORCH SEE 'STN HORIZONTAL TIMING DIAGRAM' ALL 'LINES' FOR ONE FRAME Timing1: LPP ENUMERATED IN HORIZONTAL 'LINES' FRONT PORCH Timing1: VFP LH754xx-82 DISPLAY DEPENDENT TURN-OFF DELAY NXP Semiconductors NOTES: 1. Signal polarties may vary for some displays. 2. See 'STN horizontal timing' diagram. 3. LCDFP with Timing1:VSW = 0 is only a single horizontal ine period. PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME LCDFP (VERTICAL SYNCHRONIZATION PULSE) Timing1: IVS (See Note 3) DATA ENABLE LCDEN (DATA ENABLE) Timing2:ACB Timing2: IOE PANEL LOGIC ACTIVE PANEL DATA CLOCK ACTIVE LCDVDDEN (DIGITAL SUPPLY ENABLE FOR HIGH-VOLTAGE SUPPLIES) PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE VSS LCDDCLK (PANEL CLOCK) Timing2:PCD Timing2: BCD Timing2: IPC Timing2: CPL See Note 2 PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE 1 STN FRAME VDD DISPLAY-DEPENDENT TURN-ON DELAY System-on-Chip LH75401/LH75411 Figure 16. STN Vertical Timing Diagram 51 52 Rev. 01 — 16 July 2007 Timing0:HSW ENUMERATED IN 'LCDDCLKS' HORIZONTAL BACK PORCH Timing0:HBP D001 D002 ONE 'LINE' OF LCD DATA D.... Timing0:PPL DNNN ENUMERATED IN 'LCDDCLKS' HORIZONTAL FRONT PORCH Timing0:HFP LH754xx-79 NXP Semiconductors NOTES: 1. The CLCDC clock (from the RCPC) is scaled within the CLCDC and used to produce the LCDDCLK output. CLCDC registers set timing (in terms of LCDDCLK pulses) to produce the other signals that control a TFT display. 2. The duration ot the LCDLP signal is controlled by Timing0:HSW (the HSW bit field in the Timing0 Register). 3. The polarity of the LCDLP signal is set by Timing2:IHS. LCDVD[11:0] (PANEL DATA) LCDDCLK (PANEL CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDTiming2:IHS CLCDC CLOCK (INTERNAL) APBPeriphClkCtrl1:LCD ClkPrescale:LCDPS 1 TFT HORIZONTAL LINE LH75401/LH75411 System-on-Chip Figure 17. TFT Horizontal Timing Diagram Preliminary data sheet Preliminary data sheet Rev. 01 — 16 July 2007 Timing1: VSW ENUMERATED IN HORIZONTAL 'LINES' BACK PORCH Timing1: VBP Timing1: LPP SEE 'TFT HORIZONTAL TIMING DIAGRAM' ALL 'LINES' FOR ONE FRAME DATA ENABLE ENUMERATED IN HORIZONTAL 'LINES' FRONT PORCH Timing1: VFP LH754xx-78 DISPLAY DEPENDENT TURN-OFF DELAY NXP Semiconductors NOTES: 1. Signal polarties may vary for some displays. 2. The use of LCDDSPLEN for high-voltage power control is optional on some TFT panels. PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME LCDFP (VERTICAL SYNCHRONIZATION PULSE) Timing1: IVS LCDEN (DATA ENABLE) Timing2:ACB Timing2: IOE PANEL DATA CLOCK ACTIVE PANEL LOGIC ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE VSS LCDVDDEN (DIGITAL SUPPLY ENABLE) LCDDCLK (PANEL CLOCK) Timing2:PCD Timing2: BCD Timing2: IPC See Note 2 PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE 1 TFT FRAME VDD DISPLAY-DEPENDENT TURN-ON DELAY System-on-Chip LH75401/LH75411 Figure 18. TFT Vertical Timing Diagram 53 LH75401/LH75411 System-on-Chip NXP Semiconductors 1 AD-TFT or HR-TFT HORIZONTAL LINE * CLCDCLK (INTERNAL) APBPeriphClkCtrl1:LCD ClkPrescale:LCDPS (SHOWN FOR REFERENCE) AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED INPUTS TO THE ALI FROM THE CLCDC Timing0:HSW LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDDCLK (PANEL CLOCK) Timing2:PCD Timing2:BCD Timing2:IPC Timing2:CPL 001 002 003 004 005 006 007 008 LCDVD[11:0] 320 PIXEL DATA Timing0:HSW + Timing0: HBP LCDEN (DATA ENABLE) LCDDCLK (DELAYED FOR AD-TFT, HR-TFT) OUTPUTS FROM THE ALI TO THE PANEL LCDVD[11:0] (DELAYED FOR AD-TFT, HR-TFT) 001 002 003 004 005 006 317 318 319 320 1 LCDDCLK LCDSPL (AD-TFT, HR-TFT START PULSE LEFT) 1 LCDDCLK Timing1:LPDEL LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) Timing1:CLSDEL Timing2:CLSDEL2 LCDCLS LCDPS Timing1:REVDEL LCDREV NOTE: * Source is RCPC. LH754xx-80 Figure 19. AD-TFT, HR-TFT Horizontal Timing Diagram Timing1:VSW LCDSPS (VERTICAL SYNCHRONIZATION) 1.5 µs - 4 µs LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDVD[11:0] (LCD VIDEO DATA) NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz. LH754xx-81 Figure 20. AD-TFT, HR-TFT Vertical Timing Diagram 54 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors SUGGESTED EXTERNAL COMPONENTS Figure 22 shows the suggested external components for the 14.7456 MHz crystal circuit to be used with the NXP LH75401/LH75411. The NAND gate represents the logic inside the SoC. See the chart for crystal specifics. Figure 21 shows the suggested external components for the 32.768 kHz crystal circuit to be used with the NXP LH75401/LH75411. The NAND gate represents the logic inside the SoC. See the chart for crystal specifics. INTERNAL TO THE LH75400, LH75401, LH75410, LH75411 ENABLE EXTERNAL TO THE LH75400, LH75401, LH75410, LH75411 XTAL32IN Y1 XTAL32OUT 32.768 kHz R1 18 MΩ NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 12.5 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is ≤ 5%. C1 15 pF C2 18 pF GND GND RECOMMENDED CRYSTAL SPECIFICATIONS PARAMETER DESCRIPTION 32.768 kHz Crystal Tolerance Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part Parallel Mode ±30 ppm ±3 ppm 12.5 pF 50 kΩ 1.0 µW (MAX.) MTRON SX1555 or equivalent LH754xx-101 Figure 21. Suggested External Components, 32.768 kHz Oscillator Preliminary data sheet Rev. 01 — 16 July 2007 55 LH75401/LH75411 System-on-Chip NXP Semiconductors INTERNAL TO THE LH75400, LH75401, LH75410, LH75411 ENABLE EXTERNAL TO THE LH75400, LH75401, LH75410, LH75411 XTALIN Y1 XTALOUT 14.7456 MHz R1 1 MΩ C1 18 pF C2 22 pF GND GND RECOMMENDED CRYSTAL SPECIFICATIONS NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 18 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is ≤ 5%. PARAMETER DESCRIPTION 14.7456 MHz Crystal Tolerance Stability Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part (AT-Cut) Parallel Mode ±50 ppm ±100 ppm ±5 ppm 18 pF 40 Ω 100 µW (MAX.) MTRON SX2050 or equivalent LH754xx-102 Figure 22. Suggested External Components, 14.7456 MHz Oscillator 56 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip LH75401/LH75411 NXP Semiconductors PACKAGE SPECIFICATIONS LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 73 72 108 109 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.5 HD HE 22.15 22.15 21.85 21.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 θ o 7 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT486-1 136E23 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-14 03-02-20 Figure 23. Package outline SOT486-1 (LQFP144) Preliminary data sheet Rev. 01 — 16 July 2007 57 LH75401/LH75411 System-on-Chip NXP Semiconductors 144LQFP 21.2 0.5 22.8 19.6 17.5 0.3 1.6 17.5 NOTE: Dimensions in mm. 144LQFP Figure 24. Recommended PCB Footprint 58 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 REVISION HISTORY Table 27. Revision history Document ID LH75401_411_N_1 Modifications: Release date 20070716 Data sheet status Preliminary data sheet Change notice - Supersedes LH754xx Data Sheet 5-10-07 • First NXP version based on the LH75400/01/10/11 data sheet of 20070510 Preliminary data sheet Rev. 01 — 16 July 2007 59 LH75401/LH75411 System-on-Chip NXP Semiconductors 1. Legal information 1.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 1.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 1.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 1.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] © NXP B.V. 2007. All rights reserved. IMPORTANT NOTICE Dear customer, As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use [email protected] (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Copyright © (year) by SHARP Corporation. is replaced with: - © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via [email protected]). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document. NXP Semiconductors ANNEX A: Disclaimers (11) 1. t001dis100.fm: General (DS, AN, UM) General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 2. t001dis101.fm: Right to make changes (DS, AN, UM) Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 3. t001dis102.fm: Suitability for use (DS, AN, UM) Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 4. t001dis103.fm: Applications (DS, AN, UM) Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 5. t001dis104.fm: Limiting values (DS) Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 6. t001dis105.fm: Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 7. t001dis106.fm: No offer to sell or license (DS) No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable) Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages. 9. t001dis108.2.fm: Bare die (DS; if applicable) Bare die (if applicable) — Products indicated as Bare Die are subject to separate specifications and are not tested in accordance with standard testing procedures. Product warranties and guarantees as stated in this document are not applicable to Bare Die Products unless such warranties and guarantees are explicitly stated in a valid separate agreement entered into by NXP Semiconductors and customer. 10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable) AEC unqualified products — This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. 11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if applicable) Suitability for use in automotive applications only — This NXP Semiconductors product has been developed for use in automotive applications only. The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.