PCF85133 Universal LCD driver for low multiplex rates Rev. 1 — 17 February 2009 Product data sheet 1. General description The PCF85133 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 80 segments and can easily be cascaded for larger LCD applications. The PCF85133 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremental addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). 2. Features n n n n n n n n n n n n n n n n n n n n Single-chip LCD controller and driver Selectable backplane drive configuration: static or 2, 3 or 4 backplane multiplexing Selectable display bias configuration: static, 1⁄2 or 1⁄3 Selectable frame frequency: 82 Hz or 110 Hz Internal LCD bias generation with voltage-follower buffers 80 segment drives: u Up to 40 7-segment numeric characters u Up to 21 14-segment alphanumeric characters u Any graphics of up to 320 elements 80 × 4 bit RAM for display data storage Auto-incremental display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide LCD supply range for low-threshold LCDs, for guest-host LCDs and high-threshold (automobile) twisted nematic LCDs: from 2.5 V to 6.5 V Low power consumption 400 kHz I2C-bus interface May be cascaded for large LCD applications (up to 5120 elements possible) May be cascaded with PCF8532 to gain more flexibility in the number of addressable segments No external components Compatible with Chip-On-Glass (COG) technology Manufactured using silicon gate CMOS process PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Type number Package PCF85133U/2DA/1 [1] Name Description Delivery form[1] Version PCF85133 bare die; 110 bumps; 4.16 × 1.07 × 0.38 mm chip with bumps in tray PCF85133 Bump hardness see Table 20. 4. Marking Table 2. Marking codes Type number Marking code PCF85133U/2DA/1 PC85133-1 5. Block diagram S0 to S79 BP0 BP1 BP2 BP3 80 VLCD BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY SEGMENT OUTPUTS DISPLAY REGISTER OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY CONTROL LCD BIAS GENERATOR VSS PCF85133 CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE OSCILLATOR POWER-ON RESET OSC FF SCL INPUT FILTERS SDA COMMAND DECODE WRITE DATA CONTROL I2C-BUS CONTROLLER SA0 Fig 1. DISPLAY RAM DATA POINTER AND AUTO INCREMENT SUBADDRESS COUNTER SDAACK VDD A0 A1 A2 001aaj583 Block diagram of PCF85133 PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 2 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 6. Pinning information 41 D2 S12 D6 D7 S67 96 D8 6.1 Pinning +y 0 +x 0 40 S11 D1 BP2 BP0 S0 VLCD VSS OSC FF A0 A1 A2 SA0 SYNC VDD CLK SCL SDA 1 110 S79 BP3 BP1 SDAACK 97 D9 S68 PCF85133 001aaj559 Top view. For mechanical details, see Figure 23. Fig 2. Pinning of PCF85133 6.2 Pin description Table 3. Pin description overview Symbol Pin Description SDAACK 1 to 3 I2C-bus acknowledge output SDA 4 to 6 I2C-bus serial data input SCL 7 to 9 I2C-bus serial clock input CLK 10 clock input/output VDD 11 to 13 supply voltage SYNC 14 cascade synchronization input/output OSC 15 oscillator select FF 16 frame frequency select A0, A1 and A2 17 to 19 subaddress input SA0 20 I2C-bus slave address input VSS 21 to 23 ground supply voltage VLCD 24 to 26 LCD supply voltage BP2, BP0, BP3 and BP1 27, 28, 109 and 110 LCD backplane output S0 to S79 29 to 108 LCD segment output D1 to D9 - dummy pads PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 3 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7. Functional description The PCF85133 is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 80 segments. The display configurations possible with the PCF85133 depend on the required number of active backplane outputs. A selection of display configurations is shown in Table 4. All of the display configurations can be implemented in a typical system as shown in Figure 3. Table 4. Possible display configurations Number of 7-segment numeric 14-segment numeric Backplanes Elements Digits Indicator symbols Characters Indicator symbols Dot matrix 4 320 40 40 20 40 320 (4 × 80) 3 240 30 30 16 16 240 (3 × 80) 2 160 20 20 10 20 160 (2 × 80) 1 80 10 10 5 10 80 (1 × 80) VDD R≤ tr 2Cb SDAACK VDD VLCD SDA HOST MICROPROCESSOR/ MICROCONTROLLER 80 segment drives LCD PANEL SCL PCF85133 OSC 4 backplanes FF A0 A1 A2 SA0 VSS 001aaj582 VSS Fig 3. (up to 320 elements) Typical system configuration The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF85133. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (VDD, VSS and VLCD) and the LCD panel selected for the application. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 4 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.1 Power-on reset At power-on the PCF85133 resets to the following starting conditions: • • • • • • • All backplane and segment outputs are set to VLCD The selected drive mode is 1:4 multiplex with 1⁄3 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) The display is disabled Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors between VLCD and VSS. The center resistor can be bypassed to provide a 1⁄ bias voltage level for the 1:2 multiplex configuration. 2 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by mode-set commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 5. Table 5. Discrimination ratios LCD drive mode Number of: static Backplanes Levels LCD bias configuration 1 2 static 0 1 ∞ V off ( RMS ) -------------------------V LCD V on ( RMS ) ------------------------V LCD V on ( RMS ) D = -------------------------V off ( RMS ) 1:2 multiplex 2 3 1⁄ 2 0.354 0.791 2.236 1:2 multiplex 2 4 1⁄ 3 0.333 0.745 2.236 4 1⁄ 3 0.333 0.638 1.915 4 1⁄ 3 0.333 0.577 1.732 1:3 multiplex 1:4 multiplex 3 4 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------- , where the values for a are 1+a a = 1 for 1⁄2 bias a = 2 for 1⁄3 bias PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 5 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation V on ( RMS ) = V LCD 2 1 1 --- + ( n – 1 ) × ------------- 1 + a n -----------------------------------------------------------n (1) where VLCD is the resultant voltage at the LCD segment and where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 3 for 1:3 multiplex n = 4 for 1:4 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with the equation: 2 V off ( RMS ) = V LCD a – ( 2a + n ) -------------------------------2 n × (1 + a) (2) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from the equation: V on ( RMS ) ----------------------- = V off ( RMS ) 2 (a + 1) + (n – 1) ------------------------------------------2 (a – 1) + (n – 1) (3) Using Equation 3, the discrimination for an LCD drive mode of • 1:3 multiplex with 1⁄2 bias is 3 = 1.732 21 3 • 1:4 multiplex with 1⁄2 bias is ---------- = 1.528 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • 1:3 multiplex (1⁄2 bias):V LCD = 6 × V off ( RMS ) = 2.449V off ( RMS ) 4 × 3) • 1:4 multiplex (1⁄2 bias): V LCD = (--------------------- = 2.309V off ( RMS ) 3 These compare with V LCD = 3V off ( RMS ) when 1⁄3 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 6 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 4. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. mgl745 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn+1)(t) − VBP0(t). Voff(RMS) = 0 V. Fig 4. Static drive mode waveforms PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 7 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2 1:2 multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85133 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 5 and Figure 6. Tfr VLCD BP0 LCD segments VLCD / 2 VSS state 1 VLCD BP1 state 2 VLCD / 2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V −VLCD / 2 −VLCD VLCD VLCD / 2 state 2 0V −VLCD / 2 −VLCD (b) Resultant waveforms at LCD segment. mgl746 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.354VLCD. Fig 5. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 8 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr VLCD BP0 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD BP1 state 2 2VLCD / 3 VLCD / 3 VSS VLCD Sn Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl747 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 6. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 9 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.3 1:3 multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Figure 7. Tfr VLCD BP0 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD BP1 BP2 state 2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 Sn+2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl748 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 7. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 10 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in Figure 8. Tfr VLCD BP0 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD BP1 state 2 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD BP3 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS VLCD Sn+3 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl749 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 8. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 11 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCF85133 are timed by a frequency fclk which either is derived from the built-in oscillator frequency fosc: f osc f clk = --------64 (4) or equals an external clock frequency fclk(ext): (5) f clk = f clk ( ext ) 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output from pin CLK provides the clock signal for cascaded PCF85133s in the system. After power-up, pin SDA must be HIGH to guarantee that the clock starts. 7.5.2 External clock Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the external clock input. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. 7.6 Timing The clock frequency fclk determines the LCD frame frequency ffr and is calculated as follows: f clk f fr = --------24 (6) The internal clock frequency fclk can be selected using pin FF. As a result 2 frame frequencies are available: 82 Hz or 110 Hz (typical), see Table 6. Table 6. LCD frame frequencies Pin FF tied to Typical clock frequency (Hz) LCD frame frequency (Hz) VDD 1970 82 VSS 2640 110 The timing of the PCF85133 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between all the PCF85133s in the system. 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display register, the LCD segment outputs and one column of the display RAM. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 12 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.8 Segment outputs The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. When less than 80 segment outputs are required the unused segment outputs must be left open-circuit. 7.9 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated in accordance with the selected LCD drive mode. • In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required the unused outputs can be left open-circuit. • In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. • In 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. • In static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is a static 80 × 4 bit RAM which stores LCD data. A logic 1 in the RAM bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off state. There is a one-to-one correspondence between the RAM addresses and the segment outputs and between the individual bits of a RAM word and the backplane outputs. The display RAM bit map Figure 9 shows rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively. When display data is transmitted to the PCF85133 the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 10; the RAM filling organization depicted applies equally to other LCD types. The following applies to Figure 10: • In static drive mode the eight transmitted data bits are placed into row 0 of eight successive 4-bit RAM words. • In 1:2 multiplex mode the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 13 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates • In 1:3 multiplex mode the eight bits are placed in triples into row 0, 1 and 2 of three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. • In the 1:4 multiplex mode the eight transmitted data bits are placed in quadruples into row 0, 1, 2 and 3 of two successive 4-bit RAM words. display RAM addresses (columns) / segment outputs (S) 0 1 2 3 4 75 76 77 78 79 0 display RAM bits 1 (rows) / backplane outputs 2 (BP) 3 mgl750 The display RAM bitmap shows the direct relationship between the display RAM addresses and the segment outputs; and between the bits in a RAM word and the backplane outputs. Fig 9. Display RAM bitmap 7.11 Data pointer The addressing mechanism for the display RAM is realized using a data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command. Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 10. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: • • • • In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two If an I2C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer must be re-written prior to further RAM accesses. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 14 of 41 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LCD segments LCD backplanes display RAM filling order NXP Semiconductors PCF85133_1 Product data sheet drive mode transmitted display byte display RAM addresses (columns)/segment outputs (S) byte1 Sn+2 Sn+3 static a b f Sn+4 Sn+5 Sn+1 BP0 display RAM bits (rows)/ backplane outputs (BP) g e Sn+6 Sn Sn+7 c DP d 0 1 2 3 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x Sn Sn+1 b f g BP1 c display RAM bits (rows)/ backplane outputs (BP) DP d Sn+1 Sn+2 f g e d DP b f multiplex BP1 c BP2 display RAM bits (rows)/ backplane outputs (BP) DP d n+2 n+3 a b x x f g x x e c x x d DP x x n Sn g e n+1 MSB a b LSB f g e c d DP display RAM addresses (columns)/segment outputs (S) byte1 byte2 byte3 BP0 a 0 1 2 3 n 0 b 1 DP 2 c 3 x n+1 n+2 a d g x f e x x MSB LSB b DP c a d g f e display RAM addresses (columns)/segment outputs (S) byte1 byte2 byte3 byte4 byte5 a Sn 1:4 b f BP0 g multiplex e c d DP BP3 display RAM bits (rows)/ backplane outputs (BP) 0 a 1 c 2 b 3 DP n+1 f e g d MSB a c b DP f LSB e g d 001aaj646 x = data bit unchanged Fig 10. Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus PCF85133 15 of 41 © NXP B.V. 2009. All rights reserved. Sn+1 BP1 n BP2 Universal LCD driver for low multiplex rates Rev. 1 — 17 February 2009 e Sn+3 1:3 c b a a multiplex Sn+2 LSB display RAM addresses (columns)/segment outputs (S) byte1 byte2 BP0 1:2 MSB PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.12 Subaddress counter The storage of display data is conditioned by the content of the subaddress counter. Storage is allowed only when the content of the subaddress counter match with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device-select command (see Table 12). If the content of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF85133 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 27th display data byte transmitted in 1:3 multiplex mode). The hardware subaddress must not be changed whilst the device is being accessed on the I2C-bus interface. 7.13 Output bank selector The output bank selector selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by the contents of row 1, row 2 and then row 3 • In 1:3 multiplex mode, rows 0, 1 and 2 are selected sequentially • In 1:2 multiplex mode, rows 0 and 1 are selected • In static mode, row 0 is selected The PCF85133 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.14 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The input bank selector functions independently to the output bank selector. 7.15 Blinker The display blinking capabilities of the PCF85133 are very versatile. The whole display can blink at frequencies selected by the blink-select command (see Table 14). The blink frequencies are fractions of the clock frequency. The ratios between the clock and blink frequencies depend on the blink mode in which the device is operating (see Table 7). PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 16 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates Table 7. Blink frequencies Blink mode Operating mode ratio Blink frequency with respect to fclk (typical) fclk = 1.970 kHz off Unit fclk = 2.640 kHz - blinking off blinking off Hz 1 f clk --------768 2.5 3.5 Hz 2 f clk -----------1536 1.3 1.7 Hz 3 f clk -----------3072 0.6 0.9 Hz An additional feature is for an arbitrary selection of LCD segments to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command. In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can blink by selectively changing the display RAM data at fixed time intervals. If the entire display can blink at a frequency other than the typical blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 10). 7.16 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. By connecting pin SDAACK to pin SDA on the PCF85133, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications1. In COG applications where the track resistance from the SDAACK pin to the system SDA line can be significant, possibly a voltage divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the PCF85133 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAACK pin to the system SDA line to guarantee a valid LOW level. The following definition assumes SDA and SDAACK are connected and refers to the pair as SDA. 1. For further information, please consider the NXP application note: AN10170, Design guidelines for COG modules with NXP monochrome LCD drivers. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 17 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.16.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 11). SDA SCL data line stable; data valid change of data allowed mba607 Fig 11. Bit transfer 7.16.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 12. SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 12. Definition of START and STOP conditions 7.16.2 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 13. MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL mga807 Fig 13. System configuration PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 18 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.16.3 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 14. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 14. Acknowledgement on the I2C-bus 7.16.4 I2C-bus controller The PCF85133 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF85133 are the acknowledge signals from the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. In a single device application, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 19 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.16.5 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.16.6 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF85133. The least significant bit of the slave address is bit R/W. The PCF85133 is a write-only device and will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defined by the level tied at input SA0. Two types of PCF85133 can be distinguished on the same I2C-bus which allows: • Up to 16 PCF85133s on the same I2C-bus for very large LCD applications • The use of two types of LCD multiplex on the same I2C-bus The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCF85133 slave addresses available. All PCF85133s with the corresponding SA0 level acknowledge in parallel to the slave address, but all PCF85133 with the alternative SA0 level ignore the whole I2C-bus transfer. After acknowledgement, a control byte follows which defines if the next byte is RAM or command information. The control byte also defines if the next byte is a control byte or further RAM or command data. In this way it is possible to configure the device and then fill the display RAM with little overhead. The command bytes and control bytes are also acknowledged by all addressed PCF85133s connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter; see Section 7.11 and Section 7.12. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF85133. After the last (display) byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be asserted to RESTART an I2C-bus access. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 20 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates R/W = 0 slave address control byte S C R S 0 1 1 1 0 0 A 0 A O S 0 RAM/command byte M A S B L S P B EXAMPLES a) transmit two bytes of RAM data S S 0 1 1 1 0 0 A 0 A 0 1 0 RAM DATA A RAM DATA A A COMMAND A 0 0 A COMMAND A P A COMMAND A 0 1 A RAM DATA A A P b) transmit two command bytes S S 0 1 1 1 0 0 A 0 A 1 0 0 c) transmit one command byte and two RAM date bytes S S 0 1 1 1 0 0 A 0 A 1 0 0 RAM DATA A P mgl752 Fig 15. I2C-bus protocol MSB 7 6 5 CO RS 4 3 2 LSB 0 1 not relevant mgl753 Fig 16. Control byte format Table 8. Load-data-pointer command bit description Bit Symbol 7 CO 6 5 to 0 Value continue bit 0 last control byte 1 control bytes continue RS - Description register selection 0 command register 1 data register not relevant PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 21 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 7.17 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. The commands available to the PCF85133 are defined in Table 9. Table 9. Definition of commands Command Operation code Reference mode-set 1 1 0 0 E B M1 M0 Table 10 load-data-pointer 0 P6 P5 P4 P3 P2 P1 P0 Table 11 device-select 1 1 1 0 0 A2 A1 A0 Table 12 bank-select 1 1 1 1 1 0 I O Table 13 blink-select 1 1 1 1 0 A BF1 BF0 Table 14 Table 10. Mode-set command bit description Bit Symbol Value Description 7 to 4 - 1100 fixed value 3 E 2 0 disabled (blank) 1 enabled B 1 to 0 [1] display status[1] LCD bias configuration 0 1⁄ 3 bias 1 1⁄ 2 bias M[1:0] LCD drive mode selection 01 static; 1 backplane 10 1:2 multiplex; 2 backplanes 11 1:3 multiplex; 3 backplanes 00 1:4 multiplex; 4 backplanes The possibility to disable the display allows implementation of blinking under external control. Table 11. Load-data-pointer command bit description See Section 7.11. Bit Symbol Value Description 7 - 0 fixed value 6 to 0 P[6:0] 0000000 to 0111011 immediate data 7-bit binary value of 0 to 79, transferred to the data pointer to define one of 80 display RAM addresses Table 12. Device-select command bit description See Section 7.12. Bit Symbol Value Description 7 to 3 - 11100 fixed value 2 to 0 A[2:0] 000 to 111 immediate data 3-bit binary value of 0 to 7, transferred to the subaddress counter to define one of 8 hardware subaddresses PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 22 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates Table 13. Bank-select command bit description[1] See Section 7.10, Section 7.11, Section 7.12, Section 7.13 and Section 7.14. Bit Symbol Value 7 to 2 - 111110 1 I Description Static Input bank selection: storage of arriving display data 0 1 0 [1] 1:2 multiplex fixed value O RAM bit 0 RAM bits 0 and 1 RAM bit 2 RAM bits 2 and 3 Output bank selection: retrieval of LCD display data 0 RAM bit 0 RAM bits 0 and 1 1 RAM bit 2 RAM bits 2 and 3 The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes. Table 14. Blink-select command bit description See Section 7.15. Bit Symbol Value Description 7 to 3 - 11110 fixed value 2 A 1 to 0 blink mode selection[1] 0 normal blinking 1 blinking by alternating display RAM banks blink mode selection[2] BF[1:0] 00 off 01 1 10 2 11 3 [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [2] For the blink frequencies see Table 7. 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the device’s status registers and co-ordinates their effects. The display controller is also responsible for loading display data into the display RAM as required by the filling order. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 23 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 8. Internal circuitry VDD VDD VSS VSS SA0, CLK, SYNC, OSC, FF, A0, A1, A2 SCL, SDA, SDAACK VSS VLCD VLCD VSS VSS BP0, BP1, BP2, BP3, S0 to S79 001aaj580 Fig 17. Device protection diagram PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 24 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Max Unit VDD supply voltage −0.5 +6.5 V VLCD LCD supply voltage −0.5 +9.0 V Vi(n) voltage on any input VDD related inputs −0.5 +6.5 V Vo(n) voltage on any output VLCD related outputs −0.5 +9.0 V II input current −10 +10 mA IO output current −10 +10 mA IDD supply current −50 +50 mA ISS ground supply current −50 +50 mA IDD(LCD) LCD supply current −50 +50 mA Ptot total power dissipation - 400 mW P/out power dissipation per output Vesd Ilu Tstg - 100 mW Human Body Model [1] - ±4500 V Machine Model [2] - ±250 V latch-up current [3] - 200 mA storage temperature [4] −65 +150 °C electrostatic discharge voltage [1] Pass level; Human Body Model (HBM) according to JESD22-A114. [2] Pass level; Machine Model (MM), according to JESD22-A115. [3] Pass level; latch-up testing, according to JESD78. [4] According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %. PCF85133_1 Product data sheet Min © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 25 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 10. Static characteristics Table 16. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 1.8 - 5.5 V VLCD LCD supply voltage 2.5 - 6.5 V VPOR power-on reset voltage IDD(LCD) LCD supply current supply current IDD 1.0 1.3 1.6 V fclk = 1536 Hz [1] - 16 60 µA fclk = 1536 Hz [1] - 2 20 µA Logic VSS − 0.5 - VDD + 0.5 V 0.7VDD - VDD VSS - 0.3VDD V 0.8VDD - - V - - 0.2VDD V HIGH-level output current at pin CLK; VOH = 4.6 V; VDD = 5 V 1 - - mA IOL LOW-level output current at pins CLK, SYNC; VOL = 0.4 V; VDD = 5 V - - −1 mA IL leakage current at pins OSC, CLK, SCL, SDA, A0 to A2, SA0, FF; VI = VDD or VSS −1 - +1 µA CI input capacitance - - 7 pF VI input voltage VIH HIGH-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, FF VIL LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, FF VOH HIGH-level output voltage VOL LOW-level output voltage IOH [2] V I2C-bus Input on pins SDA and SCL VI input voltage VSS − 0.5 - 5.5 V VIH HIGH-level input voltage 0.7VDD - 5.5 V VSS - 0.3VDD V - - 7 pF VOL = 0.4 V; VDD = 5 V - - −3 mA on pins BP0 to BP3; Cbpl = 35 nF −100 - +100 mV on pins S0 to S79; Csgm = 5 nF −100 - +100 mV VIL LOW-level input voltage CI input capacitance IOL(SDA) LOW-level output current on pin SDA [2] LCD outputs ∆VO output voltage variation output resistance RO VLCD = 5 V on pins BP0 to BP3 [3] - 1.5 10 kΩ on pins S0 to S79 [3] - 6.0 13.5 kΩ [1] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [2] Not tested, design specification only. [3] Outputs measured individually and sequentially. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 26 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 11. Dynamic characteristics Table 17. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Clock Internal: output pin CLK clock frequency fclk frame frequency ffr FF = VDD [1][2] 1440 1970 2640 Hz FF = VSS [1][2] 1920 2640 3600 Hz FF = VDD 60 82 110 Hz FF = VSS 80 110 150 Hz 800 - 3600 Hz External: input pin CLK [2] fclk(ext) external clock frequency tclk(H) HIGH-level clock time 130 - - µs tclk(L) LOW-level clock time 130 - - µs Synchronization: input pin SYNC tPD(SYNC_N) SYNC propagation delay - 30 - ns tSYNC_NL SYNC LOW time 1 - - µs - - 30 µs Outputs: pins BP0 to BP3 and S0 to S79 tPD(drv) I2C-bus: driver propagation delay VLCD = 5 V timing[3][4] Pin SCL fSCL SCL clock frequency - - 400 kHz tHIGH HIGH period of the SCL clock 0.6 - - µs tLOW LOW period of the SCL clock 1.3 - - µs tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - µs tSU;STO set-up time for STOP condition 0.6 - - µs tHD;STA hold time (repeated) START condition 0.6 - - µs tSU;STA set-up time for a repeated START condition 0.6 - - µs tr rise time of both SDA and SCL signals - - 0.3 µs tf fall time of both SDA and SCL signals - - 0.3 µs Cb capacitive load for each bus line - - 400 pF tw(spike) spike pulse width - - 50 ns on bus [1] Typical output duty cycle of 50 %. [2] The corresponding frame frequency is f fr = --------- . 24 [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. [4] For I2C-bus timings see Figure 19. f clk PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 27 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 1 / fCLK tclk(H) tclk(L) 0.7 VDD CLK 0.3 VDD 0.7 VDD SYNC 0.3 VDD tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3, and S0 to S79 (VDD = 5 V) 0.5 V tPD(drv) 001aag591 Fig 18. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 19. I2C-bus timing waveforms PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 28 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 12. Application information 12.1 Cascaded operation In large display configurations of up to sixteen PCF85133s can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). Table 18. Addressing cascaded PCF85133 Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device 1 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 0 0 0 8 0 0 1 9 0 1 0 10 0 1 1 11 1 0 0 12 1 0 1 13 1 1 0 14 1 1 1 15 2 1 When cascaded PCF85133s are synchronized, they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF85133s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 20). For display sizes that are not multiple of 320 elements, a mixed cascaded system can be considered containing only devices like PCF85133 and PCF8532. Depending on the application, one must take care of the software commands compatibility and pin connection compatibility. In a cascade only one master but multiple slaves are allowed. No external clock should be used; the slaves get the clock from the master. The SYNC line is provided to maintain the correct synchronization between all cascaded PCF85133s. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments, or by the definition of a multiplex mode when PCF85133s with different SA0 levels are cascaded). PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 29 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates SYNC is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF85133 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCF85133 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC signal for the various drive modes of the PCF85133 are shown in Figure 21. SDAACK VDD VLCD SDA 80 segment drives SCL SYNC PCF85133 CLK (2) BP0 to BP3 (open-circuit) OSC FF LCD PANEL A0 A1 A2 SA0 VSS (up to 5120 elements) VLCD VDD R≤ SDAACK tr 2Cb VDD VLCD 80 segment drives SDA HOST MICROPROCESSOR/ MICROCONTROLLER SCL SYNC PCF85133 CLK 4 backplanes (1) BP0 to BP3 OSC FF A0 VSS A1 A2 SA0 VSS 001aaj581 (1) Is master (OSC connected to VSS). (2) Is slave (OSC connected to VDD). Fig 20. Cascaded PCF85133 configuration The contact resistance between the SYNC bumps of cascaded devices must be controlled. If the resistance is too high then the device will not be able to synchronize properly. This is particularly applicable to COG applications. Table 19 shows the limiting values for contact resistance. Table 19. SYNC contact resistance Number of devices Maximum contact resistance 2 6000 Ω 3 to 5 2200 Ω 6 to 10 1200 Ω 11 to 16 700 Ω PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 30 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Fig 21. Synchronization of the cascade for the various PCF85133 drive modes PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 31 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 13. Bare die description 13.1 General description Table 20. Gold bump hardness Type number Min Max Unit[1] PCF85133U/2DA/1 60 120 HV [1] Pressure of diamond head: 10 g to 50 g. 13.2 Alignment marks REF REF S1 C1 001aah849 The approximate positions of the alignment marks are shown in Figure 23. Fig 22. Alignment marks of PCF85133 Table 21. Alignment mark locations Symbol X (µm) Y (µm) S1 −1916.1 45 C1 1855.8 45 13.3 Bump locations Table 22. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 23. Symbol Bump X (µm) Y (µm) SDAACK 1 −1022.67 −436.5 SDAACK 2 −968.67 −436.5 SDAACK 3 −914.67 −436.5 SDA 4 −712.17 −436.5 SDA 5 −658.17 −436.5 SDA 6 −604.17 −436.5 SCL 7 −433.17 −436.5 SCL 8 −379.17 −436.5 SCL 9 −325.17 −436.5 CLK 10 −173.52 −436.5 Description [1] I2C-bus acknowledge output [1] I2C-bus serial data input PCF85133_1 Product data sheet I2C-bus serial clock input clock input/output © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 32 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates Table 22. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 23. Symbol Bump X (µm) Y (µm) Description VDD 11 −61.47 −436.5 supply voltage VDD 12 −7.47 −436.5 VDD 13 46.53 −436.5 SYNC 14 149.58 −436.5 cascade synchronization input/output OSC 15 262.08 −436.5 oscillator select FF 16 345.78 −436.5 frame frequency select A0 17 429.48 −436.5 subaddress input A1 18 513.18 −436.5 A2 19 596.88 −436.5 SA0 20 680.58 −436.5 I2C-bus slave address input; bit 0 VSS 21 765.63 −436.5 ground supply voltage VSS 22 819.63 −436.5 VSS 23 873.63 −436.5 VLCD 24 979.83 −436.5 VLCD 25 1033.83 −436.5 VLCD 26 1087.83 −436.5 BP2 27 1176.03 −436.5 BP0 28 1230.03 −436.5 S0 29 1284.03 −436.5 S1 30 1338.03 −436.5 S2 31 1392.03 −436.5 S3 32 1446.03 −436.5 S4 33 1500.03 −436.5 S5 34 1554.03 −436.5 S6 35 1608.03 −436.5 S7 36 1662.03 −436.5 S8 37 1716.03 −436.5 S9 38 1770.03 −436.5 S10 39 1824.03 −436.5 S11 40 1878.03 −436.5 S12 41 1423.53 436.5 S13 42 1369.53 436.5 S14 43 1315.53 436.5 S15 44 1261.53 436.5 S16 45 1207.53 436.5 S17 46 1153.53 436.5 S18 47 1099.53 436.5 S19 48 1045.53 436.5 S20 49 991.53 436.5 PCF85133_1 Product data sheet LCD supply voltage LCD backplane output LCD segment output © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 33 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates Table 22. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 23. Symbol Bump X (µm) Y (µm) Description S21 50 937.53 436.5 LCD segment output S22 51 883.53 436.5 S23 52 829.53 436.5 S24 53 714.06 436.5 S25 54 660.06 436.5 S26 55 606.06 436.5 S27 56 552.06 436.5 S28 57 498.06 436.5 S29 58 444.06 436.5 S30 59 390.06 436.5 S31 60 336.06 436.5 S32 61 282.06 436.5 S33 62 228.06 436.5 S34 63 112.59 436.5 S35 64 58.59 436.5 S36 65 4.59 436.5 S37 66 −49.41 436.5 S38 67 −103.41 436.5 S39 68 −157.41 436.5 S40 69 −211.41 436.5 S41 70 −265.41 436.5 S42 71 −319.41 436.5 S43 72 −373.41 436.5 S44 73 −427.41 436.5 S45 74 −481.41 436.5 S46 75 −596.88 436.5 S47 76 −650.88 436.5 S48 77 −704.88 436.5 S49 78 −758.88 436.5 S50 79 −812.88 436.5 S51 80 −866.88 436.5 S52 81 −920.88 436.5 S53 82 −974.88 436.5 S54 83 −1028.88 436.5 S55 84 −1082.88 436.5 S56 85 −1136.88 436.5 S57 86 −1252.35 436.5 S58 87 −1306.35 436.5 S59 88 −1360.35 436.5 PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 34 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates Table 22. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 23. Symbol Bump X (µm) Y (µm) S60 89 −1414.35 436.5 S61 90 −1468.35 436.5 S62 91 −1522.35 436.5 S63 92 −1576.35 436.5 S64 93 −1630.35 436.5 S65 94 −1684.35 436.5 S66 95 −1738.35 436.5 S67 96 −1792.35 436.5 S68 97 −1876.05 −436.5 S69 98 −1822.05 −436.5 S70 99 −1768.05 −436.5 S71 100 −1714.05 −436.5 S72 101 −1660.05 −436.5 S73 102 −1606.05 −436.5 S74 103 −1552.05 −436.5 S75 104 −1498.05 −436.5 S76 105 −1444.05 −436.5 S77 106 −1390.05 −436.5 S78 107 −1336.05 −436.5 S79 108 −1282.05 −436.5 BP3 109 −1228.05 −436.5 BP1 110 −1174.05 −436.5 D1 - 1932.03 −436.5 D2 - 1909.53 436.5 D3 - 1801.53 436.5 D4 - 1693.53 436.5 D5 - 1585.53 436.5 D6 - 1477.53 436.5 D7 - −1846.35 436.5 D8 - −1953 D9 - −1930.05 −436.5 Description LCD segment output LCD backplane output [2] 436.5 [1] For most applications SDA and SDAACK are shorted together; see Section 7.16. [2] The dummy pads are connected to VSS but are not tested. PCF85133_1 Product data sheet dummy pad © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 35 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 14. Bare die outline Bare die; 110 bumps; 4.16 x 1.07 x 0.38 mm PCF85133 D X 96 41 +y +x 0 97 E 0 PC85133-1 110 1 40 Y b A e1 e A1 L detail Y detail X 0 1 scale Dimensions Unit mm 2 mm A(1) A1(1) b(1) D E e(1) e1(1) L(1) max 0.018 nom 0.380 0.015 0.0338 4.156 1.069 0.054 0.2026 0.090 min 0.012 Note 1. Dimension not drawn to scale. pcf85133_do References Outline version IEC JEDEC JEITA PCF85133 --- --- --- European projection Issue date 09-01-26 09-02-03 Fig 23. Bare die outline of PCF85133 PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 36 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 16. Packing information A 1.1 2.1 1.2 2.2 3.1 C x.1 D 1.3 F B 1.y y E x 001aai624 Fig 24. Tray details for PCF85133 PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 37 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates marking code 001aaj643 Fig 25. Tray alignment for PCF85133 tray Table 23. Tray dimensions of PCF85133 tray See Figure 24. Symbol Description Value A pocket pitch in x direction 6.3 mm B pocket pitch in y direction 3 mm C pocket width in x direction 4.26 mm D pocket width in y direction 1.17 mm E tray width in x direction 50.8 mm F tray width in y direction 50.8 mm N number of pockets, x direction 7 M number of pockets, y direction 15 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray (see Figure 25). Refer to the bump location diagram (Figure 23) for the orientation and position of the type name on the die surface. PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 38 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 17. Abbreviations Table 24. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor COG Chip-On-Glass DC Direct Current HBM Human Body Model I2C Inter-Integrated Circuit IC Integrated Circuit ITO Indium Tin Oxide LCD Liquid Crystal Display MM Machine Model RAM Random Access Memory RC Resistance and Capacitance RMS Root Mean Square 18. Revision history Table 25. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF85133_1 20090217 Product data sheet - - PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 39 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 19.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF85133_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 1 — 17 February 2009 40 of 41 PCF85133 NXP Semiconductors Universal LCD driver for low multiplex rates 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 5 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 5 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . . 7 7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 7 7.4.2 1:2 multiplex drive mode . . . . . . . . . . . . . . . . . . 8 7.4.3 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . 10 7.4.4 1:4 multiplex drive mode . . . . . . . . . . . . . . . . . 11 7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5.1 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.7 Display register . . . . . . . . . . . . . . . . . . . . . . . . 12 7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 13 7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 13 7.10 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.11 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.12 Subaddress counter . . . . . . . . . . . . . . . . . . . . 16 7.13 Output bank selector. . . . . . . . . . . . . . . . . . . . 16 7.14 Input bank selector . . . . . . . . . . . . . . . . . . . . . 16 7.15 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.16 Characteristics of the I2C-bus . . . . . . . . . . . . . 17 7.16.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.16.1.1 START and STOP conditions . . . . . . . . . . . . . 18 7.16.2 System configuration . . . . . . . . . . . . . . . . . . . 18 7.16.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.16.4 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 19 7.16.5 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.6 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 20 7.17 Command decoder . . . . . . . . . . . . . . . . . . . . . 22 7.18 Display controller . . . . . . . . . . . . . . . . . . . . . . 23 8 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 24 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 25 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 26 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 27 12 Application information. . . . . . . . . . . . . . . . . . 29 12.1 Cascaded operation . . . . . . . . . . . . . . . . . . . . 29 13 13.1 13.2 13.3 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Bare die description . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Alignment marks . . . . . . . . . . . . . . . . . . . . . . Bump locations. . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 32 32 36 37 37 39 39 40 40 40 40 40 40 41 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 17 February 2009 Document identifier: PCF85133_1