PHILIPS PCF8820

INTEGRATED CIRCUITS
DATA SHEET
PCF8820
67 × 101 Grey-scale/ECB colour
dot matrix LCD driver
Product specification
File under Integrated Circuits, IC12
2000 Dec 07
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
I2C-bus interface
Bit transfer
START and STOP conditions
System configuration
Acknowledge
I2C-bus protocol
Command decoder
Display data byte
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
7.18
7.18.1
7.18.2
7.18.3
7.18.4
7.18.5
7.18.6
7.18.7
6
PINNING
8
INSTRUCTIONS
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
6.2.14
6.2.15
Pad configuration
Pad functions
Row driver outputs
Column driver outputs
Ground supply
Supply voltage
Voltage multiplier output
Voltage multiplier regulation input
Supply voltage of bias voltage generator
LCD intermediate bias voltages
Serial data input
Serial data output
Serial clock input
Slave address inputs
Oscillator signal input
External reset input
Test pads
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.2
Description of the bit functions
Power-down mode
Partial screen mode
Y-address of DDRAM
Bias system
High voltage generator configuration
Temperature read-out
VLCD control register
Grey-scale register and grey-scale level
Direct drive mode
Frame frequency calibration
Reset and initialization
9
LIMITING VALUES
10
HANDLING
11
DC CHARACTERISTICS
12
TIMING
7
FUNCTIONAL DESCRIPTION
13
APPLICATION INFORMATION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
Oscillator
I2C-bus interface controller
Input filters
Display Data RAM (DDRAM)
Timing generator
Address counter
Display address counter
Command decoder
Column driver outputs
Row driver outputs
Bias voltage generator
High voltage generator
Temperature compensation
Temperature sensor
LCD driver waveforms
DDRAM to display mapping
DDRAM addressing
13.1
13.2
13.3
13.4
13.5
13.6
Programming example for the PCF8820
Examples of effects on the display
High voltage generator
Application for COG
Typical system configuration
External supply of VLCDIN
14
BONDING PAD INFORMATION
15
DEVICE PROTECTION CIRCUITS
16
TRAY INFORMATION
17
DATA SHEET STATUS
18
DEFINITIONS
19
DISCLAIMERS
20
BARE DIE DISCLAIMER
21
PURCHASE OF PHILIPS I2C COMPONENTS
CONTENTS
2000 Dec 07
2
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
1
PCF8820
FEATURES
• Single-chip LCD controller and driver for grey-scale/
Electrically Controlled Birefringence (ECB) colour
• 4 grey levels/colours (2-bit) definable from 64 levels
• 67 row and 101 column outputs
• Display data RAM 67 × 101 × 2-bit with linear RAM
addressing
• Software selectable top and bottom row swap for
adapting driver to different glass-layouts
• Partial screen mode with reduced current consumption
(8 rows at top or bottom of display)
• CMOS compatible inputs
• Manufactured in silicon gate CMOS process.
• On-chip:
– Generation of LCD supply voltage (VLCDOUT);
external supply also possible
2
APPLICATIONS
– Configurable voltage multiplier factor of
8, 7, 6, 5, 4, 3 or 2; direct drive also possible
• Battery powered equipment
• Mobile telecommunication systems
• Point of sale terminals
– Selectable linear temperature compensation
of VLCDOUT
• Instrumentation
– Generation of intermediate LCD bias voltages
• Automotive information systems.
– Oscillator requires no external components; external
clock also possible.
3
• Temperature read-out
• Fast mode
I2C-bus
GENERAL DESCRIPTION
The PCF8820 is a low power CMOS LCD row/column
driver, designed to drive grey-scale/ ECB colour dot matrix
graphic displays at a multiplex rate of 1 : 67. In the partial
screen mode, only 8 rows are driven at a multiplex rate of
1 : 8.
interface (400 kbits/s)
• Frame frequency calibration via software
• Software selectable bias configuration
• Compatible with 4-bit, 8-bit or 16-bit microcontrollers
This chip provides all the necessary display functions,
including on-chip generation of the LCD supply voltage
and LCD bias voltages. Consequently, fewer external
components are required and the power consumption is
low.
• Multiplex rates of 1 : 67 or 1 : 8
• Logic supply voltage range from 2.5 to 5.5 V
(VDD1 to VSS1)
• High voltage generator supply voltage range from
2.7 to 5.5 V (VDD2 to VSS1 and VDD3 to VSS2)
The PCF8820 interfaces with most microcontrollers and
communicates via a two-line bidirectional bus (I2C-bus).
All inputs are CMOS compatible.
• Bias voltage generator supply voltage range
(VLCDIN to VSS1):
Remark: the waveform generation for ECB colour is
identical to that used for grey-scale.
– From 7 to 14.5 V at a multiplex rate of 1 : 67
– From 4.5 to 14.5 V in partial screen mode at a
multiplex rate of 1 : 8.
• Low power consumption, suitable for battery operated
systems
• Slim chip layout, suitable for chip-on-glass applications
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8820U
2000 Dec 07
−
DESCRIPTION
chip with bumps in tray
3
VERSION
−
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
5
PCF8820
BLOCK DIAGRAM
V5
handbook, full pagewidth
V4
V3
V2
C0 to C100
162 163 164 165
VLCDIN
VLCDSENSE
VLCDOUT
166 to 171
172
173 to 178
VDD1
179 to 184
VDD2
188 to 194
VDD3
185 to 187
VSS1
VSS2
T1
T2
T3
T4
T5
T6
SCL
SDA_IN
SDA_OUT
RES
R0 to R66
3 to 25, 232 to 222,
148 to 127, 151 to 161
26 to 126
BIAS
VOLTAGE
GENERATOR
COLUMN
DRIVERS
ROW
DRIVERS
PCF8820
HIGH
VOLTAGE
GENERATOR
OSCILLATOR
206 to 211
198 to 203
205
220
DISPLAY
DATA LATCHES
TIMING
GENERATOR
TEMPERATURE
SENSOR
221
212
DISPLAY DATA RAM
(DDRAM)
213
217
DISPLAY
ADDRESS
COUNTER
218
215, 216
195, 196
197
INPUT
FILTERS
I2C-BUS
INTERFACE
CONTROLLER
COMMAND
DECODER
ADDRESS
COUNTER
219
204
214
MGT114
SA1
SA0
Fig.1 Block diagram.
2000 Dec 07
4
OSC
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
6
PCF8820
PINNING
6.1
Pad configuration
SYMBOL
PAD
DESCRIPTION
R0 to R22
3 to 25
LCD row driver outputs (block 1)
R23 to R33
232 to 222
LCD row driver outputs (block 2)
R34 to R55
148 to 127
LCD row driver outputs (block 3)
R56 to R66
151 to 161
LCD row driver outputs (block 4)
C0 to C100
26 to 126
LCD column driver outputs
VSS1
206 to 211
ground supply 1
VSS2
198 to 203
ground supply 2
VDD1
179 to 184
supply voltage 1 of logic
VDD2
188 to 194
supply voltage 2 of high voltage generator; temperature read-out
VDD3
185 to 187
supply voltage 3 of high voltage generator; temperature read-out
VLCDOUT
173 to 178
voltage multiplier output
VLCDSENSE
172
voltage multiplier regulation input
VLCDIN
166 to 171
supply voltage for LCD (bias voltage generator)
V2
165
LCD intermediate bias voltage 2; for test purposes only
V3
164
LCD intermediate bias voltage 3; for test purposes only
V4
163
LCD intermediate bias voltage 4; for test purposes only
V5
162
LCD intermediate bias voltage 5; for test purposes only
SDA_IN
195 and 196
serial data input
SDA_OUT
197
serial data output (acknowledge)
SCL
215 and 216
serial clock input
SA0
204
I2C-bus slave address input 0 (bit 0)
SA1
214
I2C-bus slave address input 1 (bit 1)
OSC
220
oscillator signal input
RES
219
external reset input (active LOW)
T1
205
test 1 input
T2
221
test 2 output
T3
212
test 3 I/O
T4
213
test 4 I/O
T5
217
test 5 input
T6
218
test 6 output
The pad configuration is shown in Fig.32.
2000 Dec 07
5
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
6.2
6.2.1
When an external supply voltage is used, pads VLCDIN,
VLCDSENSE and VLCDOUT do not have to be connected
together. However, if pads VLCDSENSE and VLCDOUT are
both connected to pad VLCDIN, the current consumption
can be reduced under the following conditions:
Pad functions
ROW DRIVER OUTPUTS
Row driver outputs (R0 to R66) are the outputs for the LCD
row drive signals. They should be connected directly to the
67 rows of the LCD. If less than 67 rows are required, the
unused outputs must be left open-circuit.
6.2.2
• The output of VLCDOUT is set to high-impedance
(see Table 8)
• The HIGH voltage programming range is selected by
setting bit PRS = 1, the maximum voltage multiplier on
factor 8 and the VLCD control register on the maximum
value (see Table 2).
COLUMN DRIVER OUTPUTS
Column driver outputs (C0 to C100) are the outputs for the
LCD column drive signals. They should be connected
directly to the 101 columns of the LCD. If less than
101 columns are required, the unused column outputs
must be left open-circuit.
6.2.3
6.2.8
GROUND SUPPLY
6.2.9
6.2.10
Not connecting pad SDA_IN to pad SDA_OUT allows the
device to be used in applications in which the acknowledge
bit is not required. In Chip-On-Glass (COG) applications, it
is sometimes beneficial not to connect pad SDA_OUT to
pad SDA_IN. This is because in COG applications where
the track resistance from pad SDA_OUT to the system
SDA line is significant, a voltage divider is created by the
bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. This divider could prevent the PCF8820 from
asserting a valid logic 0 level during an acknowledge
cycle.
VOLTAGE MULTIPLIER OUTPUT
VOLTAGE MULTIPLIER REGULATION INPUT
VLCDSENSE is the regulation input of the high voltage
multiplier and must be connected to VLCDOUT.
6.2.7
SUPPLY VOLTAGE OF BIAS VOLTAGE GENERATOR
VLCD is the supply voltage on pad VLCDIN for the bias
voltage generator which supplies the LCD outputs. The
voltage on pad VLCDIN must not be lower than VDD1.
In COG applications, where the acknowledge cycle is
required, the track resistance from the pad SDA_OUT to
the system SDA line must be minimized to guarantee a
valid LOW-level.
If VLCD is generated internally, pad VLCDOUT must be
connected to pad VLCDIN.
6.2.11
If VLCD is supplied externally, the external supply voltage
must be connected to pad VLCDIN. An external supply
voltage must be applied after applying VDD1, and it must be
removed before or when removing VDD1 (see Fig.25). It is
recommended that an external supply voltage is applied
after leaving the reset state. The external supply voltage
can stay applied in the Power-down mode.
2000 Dec 07
SERIAL DATA OUTPUT
SDA_OUT is the serial data output (data, acknowledge)
for the I2C-bus. Connecting pad SDA_OUT to
pad SDA_IN makes the SDA line fully I2C-bus compatible.
VLCDOUT is the output of the voltage multiplier of the high
voltage generator.
6.2.6
SERIAL DATA INPUT
SDA_IN is the serial data input from the I2C-bus.
SUPPLY VOLTAGE
The supply voltage rails (VDD1, VDD2 and VDD3) must be
connected together when the same supply is used for both
the logic circuits and for the voltage multiplier. When the
circuits are fed separately, VDD2 and VDD3 must be
connected to the same supply.
6.2.5
LCD INTERMEDIATE BIAS VOLTAGES
The LCD intermediate bias voltages (V2, V3, V4 and V5)
which are applied to the LCD columns and rows are
present on these pads for test purposes. They must be left
open-circuit in the application.
The ground supply rails (VSS1 and VSS2) must be
connected together. VSS1 is related to VDD1 and VDD3;
VSS2 is related to VDD2.
6.2.4
PCF8820
SERIAL CLOCK INPUT
SCL is the serial clock input from the I2C-bus.
6
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
6.2.12
7.4
SLAVE ADDRESS INPUTS
OSCILLATOR SIGNAL INPUT
7.5
Pad OSC must be connected directly to VDD1 when the
on-chip oscillator is used. No external components are
required. It should be noted that any voltage drop of VDD1
may affect the performance of the on-chip oscillator.
7.6
EXTERNAL RESET INPUT
TEST PADS
7.7
The test pads (T1, T2, T3, T4, T5 and T6) must not be
accessible to the user.
7.1
7.8
Oscillator
7.9
I2C-bus interface controller
The programmed grey-scale levels are built-up in the LCD
over four frames (N11, N12, N13 and N14) as shown in
Figs 3, 4 and 5.
7.10
Input filters
Row driver outputs
The LCD driver section has 67 outputs (R0 to R66) which
should be connected directly to the row drive inputs of the
LCD. The row driver signals are generated in accordance
with the selected LCD drive mode.
RC low-pass filters are provided on inputs SDA_IN, SCL
and RES to enhance noise immunity in electrically
adverse environments.
2000 Dec 07
Column driver outputs
The LCD driver section has 101 outputs (C0 to C100)
which should be connected directly to the column drive
inputs of the LCD. The column driver signals are
generated in accordance with the multiplexed row signals
and with the data in the display data latch.
The I2C-bus interface controller receives and executes the
commands sent via the I2C-bus. The PCF8820 acts as an
I2C-bus slave receiver/transmitter and therefore it cannot
control the bus communication.
7.3
Command decoder
The command decoder receives command words which
are followed by data byte(s) from the I2C-bus. The
command decoder identifies the command words and
determines the destination for the data byte(s).
FUNCTIONAL DESCRIPTION
The on-chip oscillator provides the clock signal for the LCD
system. The clock mode is controlled via the I2C-bus
interface. A clock signal must always be present, except in
the Power-down mode, to prevent the LCD entering a
DC state.
7.2
Display address counter
The display address counter generates read addresses to
the DDRAM. During a read operation, display data is read
out to the LCD.
Pads T1, T3 and T4 must be connected to VSS1, pad T5
must be connected to VDD1, and pads T2 and T6 must be
left open-circuit.
7
Address counter
The address counter generates write addresses to the
DDRAM. During a write operation, display data is stored at
the addressed locations.
A LOW-level on input RES initializes the chip.
6.2.15
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the I2C-bus.
An external clock must be connected to input OSC.
6.2.14
Display Data RAM (DDRAM)
The PCF8820 contains a 67 × 101 × 2-bit static RAM,
which stores the display data. The RAM comprises
17 banks of 101 bytes (17 × 101 × 8 bits). Not all of the
last bank is implemented. During RAM access, data is
transferred to the RAM via the I2C-bus interface controller.
These inputs (SA0 and SA1) allow up to four PCF8820
drivers to be controlled on the same I2C-bus. Inputs SA0
and SA1 represent respectively bit 0 and bit 1 of the slave
address.
6.2.13
PCF8820
7
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
7.11
7.14
Bias voltage generator
• Normal mode (from 7.0 to 14.5 V)
• Partial screen mode (from 4.5 to 14.5 V).
The temperature sensor allows any temperature
compensation to be implemented; any programmable
parameter can be optimized as a function of the sensor
read-out temperature.
High voltage generator
The high voltage generator contains a voltage multiplier
which uses a charge pump circuit supplied by VDD2 and
VDD3.
7.15
At frame inversion, the PCF8820 generates a dummy row
cycle, where no row is selected. This ensures equal
conditions for the first row after frame inversion as for the
other rows. Therefore the effective multiplex rate in all
modes is 1 : (multiplex rate + 1).
Temperature compensation
The viscosity of the liquid crystal depends on the
temperature; so to maintain optimum contrast at lower
temperatures VLCD needs usually to be increased. Fig.2
shows VLCD as a function of the temperature for a typical
high multiplex rate liquid crystal.
7.16
MGT123
VLCD
(V)
(1)
(2)
0
Tamb (°C)
(1) LCD characteristic.
(2) Linear temperature compensation.
Fig.2
LCD supply voltage as a function of the
temperature.
2000 Dec 07
DDRAM to display mapping
DDRAM to display mapping is shown in Fig.6.
Linear temperature compensation is supported in the
PCF8820. The temperature coefficient for VLCDOUT can be
set to one of 8 values by setting bits TC2 to TC0.
handbook, halfpage
LCD driver waveforms
The LCD waveforms are shown in Figs 3, 4 and 5.
The multiplier is software programmable with a factor from
2 to 8. In the direct drive mode the output voltage
VLCDOUT = VDD2.
7.13
Temperature sensor
The PCF8820 has a built-in temperature sensor. The
sensor monitors the temperature and writes an 8-bit
number into the status register. The temperature sensor
and status register can both be accessed via the I2C-bus
interface controller.
The bias voltage generator generates 4 buffered
intermediate LCD bias voltages. It contains 4 operational
amplifiers and an input reference voltage generator. It can
operate in two voltage ranges:
7.12
PCF8820
8
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N13
N14
N21
state1
ROW 0
V4
R0(t)
V5
VSS
state2
VLCD
V2
V3
ROW 1
V4
R1(t)
V5
VSS
VLCD
V2
V3
4
4
COL 0
V4
C0(t)
4
V5
VSS
VLCD
V2
V3
x x 7 9
5
16
x x 7 9 16
x x 8 8 16
COL 1
V4
C1(t)
x x 8 8 16
x x 7 9 16
V5
VSS
9
Vstate1(t)
4
VLCD
V3
V4 − V5
0V
− V5
VLCD − V2
0V
V3 − V2
Philips Semiconductors
N12
VLCD
V2
V3
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
N11
ook, full pagewidth
2000 Dec 07
Frame
V4 − VLCD
−VLCD
Vstate2(t)
VLCD
V3
VLCD − V2
0V
V3 − V2
V4 − V5
0V
− V5
V4 − VLCD
−VLCD
0
2
66
0
0
1
2
66
0
0
1
2
66
0
0
1
2
66
0
Example for setting grey-scale register.
ROW0, COL0: GS = 17
ROW1, COL0: GS = 0
ROW0, COL1: GS = 30
ROW1, COL0: GS = 63 (63 will be set to 64; see Section 8.1.8).
Fig.3 Typical LCD driver waveforms at a multiplex rate of 1 : 67.
0
1
2
66
MGT115
Product specification
Vstate2(t) = C1(t) − R1(t)
1
PCF8820
Vstate1(t) = C1(t) − R0(t)
0
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VLCD
V2
V3
N13
N14
N21
state1
ROW 0
V4
R0(t)
V5
VSS
state2
VLCD
V2
V3
ROW 1
V4
R1(t)
V5
VSS
VLCD
V2
V3
4
4
COL 0
V4
C0(t)
4
V5
VSS
VLCD
V2
V3
5
x x 7 9 16
x x 7 9 16
x x 8 8 16
COL 1
V4
C1(t)
x x 8 8 16
x x 7 9 16
V5
VSS
10
Vstate1(t)
4
VLCD
V3
V4 − V5
0V
− V5
VLCD − V2
0V
V3 − V2
Philips Semiconductors
N12
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
N11
ook, full pagewidth
2000 Dec 07
Frame
V4 − VLCD
−VLCD
Vstate2(t)
VLCD
V3
VLCD − V2
0V
V3 − V2
V4 − V5
0V
− V5
V4 − VLCD
−VLCD
0
2
7
0
0
1
2
7
0
0
1
2
7
0
0
1
2
7
0
0
1
2
Example for setting grey-scale register.
ROW0, COL0: GS = 17
ROW1, COL0: GS = 0
ROW0, COL1: GS = 30
ROW1, COL0: GS = 63 (63 will be set to 64; see Section 8.1.8).
Fig.4 Typical LCD driver waveforms at a multiplex rate of 1 : 8 for partial screen mode.
7
MGT116
Product specification
Vstate2(t) = C1(t) − R1(t)
1
PCF8820
Vstate1(t) = C1(t) − R0(t)
0
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N13
N14
N21
state1
ROW 0 0.5V
LCD
R0(t)
state2
VSS
VLCD
ROW 1 0.5V
LCD
R1(t)
VSS
VLCD
COL 0
C0(t)
VSS
VLCD
COL 1
C1(t)
VSS
11
VLCD
0.5VLCD
Vstate1(t) 0 V
Philips Semiconductors
N12
VLCD
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
N11
ook, full pagewidth
2000 Dec 07
Frame
−0.5VLCD
−VLCD
VLCD
0.5VLCD
Vstate2(t) 0 V
−0.5VLCD
−VLCD
0
1
2
7
0
0
1
2
7
0
0
1
2
7
0
0
1
2
7
0
0
1
2
7
MGT117
Fig.5 Typical LCD driver waveforms at a multiplex rate of 1 : 8, for partial screen mode and bias system 1/2.
Product specification
Example for setting grey-scale register.
ROW0, COL0: GS = 0
ROW1, COL0: GS = 63 (63 will be set to 64; see Section 8.1.8).
ROW0, COL1: GS = 63 (63 will be set to 64; see Section 8.1.8).
ROW1, COL0: GS = 63 (63 will be set to 64; see Section 8.1.8).
PCF8820
Vstate1(t) = C1(t) − R0(t).
Vstate2(t) = C1(t) − R1(t).
0
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
P0
handbook, full pagewidth
LSB DB0 MSB
DB1
P0
LSB
DB2
P1
MSB
pixel 0
LSB
DB3 P1
LSB
P0
DB4 P2
MSB
P1
P2
DB5 P2
LSB
P3
MSB
P0
bank 0
P1
P2
top of LCD
R0
P3
DB6 P3
MSB
bank 1
MSB DB7 P3
LSB
R4
bank 2
R8
bank 3
R12
.
.
.
.
.
.
bank 13
.
.
R16
LCD
R52
bank 14
R56
bank 15
R60
bank 16
X
R64
X
R66
R = row
P = pixel
MGT118
Fig.6 DDRAM to display mapping.
2000 Dec 07
12
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
7.17
DDRAM addressing
PCF8820
Bit MX (see Table 3) enables or disables horizontal
address space mirroring:
Data is written in 8-bit bytes into the display data RAM
matrix of the PCF8820 (see Figs 6 to 8). The display data
RAM comprises a matrix of 67 × 101 × 2 bits. The columns
are addressed by the address pointer. The address ranges
are: X = 0 to 100 (64H) and Y = 0 to 16 (10H). It should be
noted that only 3 rows are addressed in bank 16.
Addresses outside these ranges are not allowed.
• When bit MX = 0, mirroring is disabled. The address
corresponds to Col0 (see Fig.7).
• When bit MX = 1, mirroring is enabled and address
X = 0 corresponds to Col0 (see Fig.8). Bit MX
determines how data is written to the RAM. If bit MX is
changed after writing data to the RAM, no change on the
display will be visible.
LSB
handbook, full pagewidth
Col0
0
MSB
Y address
16
0
X address
100
MGT119
Fig.7 RAM X-address format for mirroring disabled.
LSB
handbook, full pagewidth
Col0
0
MSB
Y address
16
X address
100
0
MGT120
Fig.8 RAM X-address format for mirroring enabled.
2000 Dec 07
13
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
Bit V (see Table 3) selects either horizontal or vertical
address mode:
PCF8820
After the very last address (X = 100 and Y = 16), the
address pointers return to the first address (X = 0 and
Y = 0). It should be noted that in bank 16 only
bits DB0 to DB5 of the data will be written into the RAM.
• In vertical address mode (bit V = 1), the Y-address is
incremented after each byte (see Fig.9). After Y = 16,
the Y-address sequence returns to Y = 0 and the
X-address is incremented to address the next column.
• In horizontal address mode (bit V = 0) the X-address is
incremented after each byte (see Fig.10). After X = 100,
the X-address sequence returns to X = 0 and the
Y-address is incremented to address the next row.
handbook, full pagewidth
0
17
1
18
2
19
3
20
0
Y address
13
14
15
16
1716
0
X address
100
16
MGT121
Fig.9 Writing data to RAM sequence in vertical address mode.
handbook, full pagewidth
0
1
101
102
202
203
303
304
2
3
4
5
100
0
201
Y address
404
1414
1515
1616
0
1716
X address
100
Fig.10 Writing data to RAM sequence in horizontal address mode.
2000 Dec 07
14
16
MGT122
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
7.18
7.18.2
I2C-bus interface
START AND STOP CONDITIONS
Both data and clock lines are HIGH when the bus is not
busy (see Fig.12).
The I2C-bus allows bidirectional data communication
between different ICs or modules. The serial data input line
and serial data output line are connected together, so
representing the Serial Data (SDA) line. See Section 13.4
for layout considerations. The SDA line and the Serial
Clock Line (SCL) line must be connected to a positive
supply voltage via a pull-up resistor. Data transfer may be
initiated only when the bus is not busy.
7.18.1
PCF8820
A START condition (S) occurs when the data line goes
from HIGH-to-LOW while the clock is HIGH.
A STOP condition (P) occurs when the data line goes from
LOW-to-HIGH while the clock is HIGH.
BIT TRANSFER
One data bit is transferred during a clock pulse period. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse, otherwise any change in the data
within this period will be interpreted as a control signal
(see Fig.11).
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.11 Bit transfer.
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Fig.12 Definition of START and STOP conditions.
2000 Dec 07
15
MBC622
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
7.18.3
During the acknowledge clock pulse a HIGH-level signal is
put on the bus by the transmitter.
SYSTEM CONFIGURATION
Thd system components are defined below (see Fig.13):
A slave receiver which is addressed must generate an
acknowledge bit after the reception of each data byte.
A master receiver must generate an acknowledge bit after
receiving a data byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line to a LOW-level during the
acknowledge clock pulse. Set-up and hold times must be
taken into consideration to ensure that the SDA line is
stable during the HIGH period of the acknowledge related
clock pulse.
• Transmitter: the device which sends data to the bus
• Receiver: the device which receives data from the bus
• Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
• Slave: the device addressed by a master
• Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
A master receiver must signal an end-of-data to the slave
transmitter by not generating an acknowledge bit on the
last byte that has been clocked out of the slave transmitter.
In this event the slave transmitter must leave the data line
HIGH to allow the master to generate a STOP condition.
• Synchronization: procedure to synchronize the clock
signals of two or more devices.
7.18.4
For the PCF8820 the acknowledge bit is output at
pad SDA_OUT.
ACKNOWLEDGE
Each 8-bit data byte transferred over the bus must be
followed by an acknowledge bit (see Fig.14).
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
PCF8820
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.13 System configuration.
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.14 Acknowledgement on the I2C-bus.
2000 Dec 07
16
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
7.18.5
PCF8820
Only the addressed PCF8820 acknowledges after each
byte is received. The I2C-bus master issues a stop
condition (P) at the end of the transmission.
I2C-BUS PROTOCOL
The PCF8820 is a slave transmitter/receiver. If data is to
be read from the device, the SDA_OUT output must be
used.
Before any data is transferred over the I2C-bus, the
destination device is addressed first (see Fig.15).
The PCF8820 has four 7-bit slave addresses reserved:
0111 100, 0111 101, 0111 110 and 0111 111. The two
least significant bits of the slave address are set by
connecting slave address inputs SA1 and SA0 to either
VSS1 (logic 0) or VDD1 (logic 1).
S
0
slave address
R/W Co
control byte
A
SA1 SA0 R/W
1
Co
RS
control byte
X
X
X
X
X
X
MGT124
continuation
bit
Fig.16 Control byte.
acknowledgement
from PCF8820
data byte
2n ≥ 0 bytes
A 0 RS
Co
acknowledgement
from PCF8820
control byte
A
1 byte
acknowledgement
from PCF8820
data byte
Fig.17 Write sequence: master transmits bytes to slave receiver.
17
A P
m ≥ 0 bytes
MGT125
2000 Dec 07
A
slave
read/write
address
bit
bit 1
slave
address
bit 0
register
selection
bit
If bit RS = 1, the data bytes are stored as display data in
the DDRAM at the address specified by the data pointer.
The data pointer is automatically incremented.
If bit RS = 0, the data byte is interpreted as a command
byte to be decoded and the device will be set according to
the received commands.
S S
S 0 1 1 1 1 A A 0 A 1 RS
1 0
1
Fig.15 Slave address.
Depending on the setting of bit RS in the last control byte,
either a series of display data bytes or command data
bytes may follow.
acknowledgement
from PCF8820
1
MGU185
A command word consists of a control byte (see Fig.16)
defining ‘continuation’ bit Co and ‘register selection’
bit RS, plus a data byte. The last control byte is indicated
by resetting bit Co = 0. The control and data bytes are also
acknowledged by all addressed slaves on the bus.
acknowledgement
from PCF8820
1
START
condition
A write sequence (see Fig.17) is initiated with a START
condition (S) from the I2C-bus master which is followed by
the slave address. Only the addressed slave
acknowledges. After acknowledgement, one or more
command words follow which define the status of the
addressed slave.
handbook, full pagewidth
acknowledge
bit
slave address
update
data pointer
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
For a read sequence (see Fig.18), the addressed
PCF8820 will immediately start to output the requested
data until a NOT acknowledge is transmitted by the
master. Before the read access, the user has to set bit RS
to the appropriate value by a preceding write access. The
sequence should be terminated by a STOP condition
when no further access is required, or by a RE-START
condition if further access is required.
PCF8820
acknowledgement
from PCF8820
S S
S 0 1 1 1 1 A A 1 A
1 0
not acknowledgement
from master
temperature
readout value
A P
slave address
7.18.6
STOP condition
R/W
COMMAND DECODER
MGT126
The command decoder identifies command words
received via the I2C-bus.
Fig.18 Read sequence: master receives bytes
from slave transmitter status register.
Bit 7 of the control byte is named bit Co (see Fig.16):
• Bit Co = 1 indicates that only one command byte or
DDRAM data byte will follow next
• Bit Co = 0 indicates that a stream of command bytes or
DDRAM data bytes will follow next depending on last
status of bit RS.
MSB
Bit 6 of a control byte is named bit RS:
LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
• Bit RS = 1 indicates that another DDRAM data byte will
follow next
P3
P3
P2
P2
P1
P1
P0
P0
LSB MSB LSB MSB LSB MSB LSB MSB
• Bit RS = 0 indicates that another command byte will
follow next.
pixel 3
pixel 2
pixel 1
pixel 0
MGT127
The definition of bits Co and RS is shown in Table 1.
7.18.7
DISPLAY DATA BYTE
Fig.19 Grey-scale display data byte.
A display data byte for grey-scale is shown in Fig.19.
Table 1
Definition of bits Co and RS
BIT
VALUE
ACTION
Co
0
last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may
only be terminated by a STOP or RE-START condition
1
another control byte will follow the data byte unless a STOP or RE-START condition is
received
0
data byte will be decoded and used to set up the device
RS
data byte will return the sensor temperature read-out
1
data byte will be stored in the DDRAM
RAM read-back (not supported)
2000 Dec 07
18
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
8
PCF8820
In normal use, the most frequently used instructions are
those which perform data transfers to the DDRAM.
Address pointer update follows after the data byte has
been written to the DRAM. This reduces the program load
of the microcontroller.
INSTRUCTIONS
I2C-bus.
The clock of the
The PCF8820 interfaces via the
LCD is not required to process instructions.
The data received by the PCF8820 is either instruction
data which defines its operating mode or display data to be
stored in its DDRAM. The type of data is identified by
bit RS. When bit RS = 0, the PCF8820 will respond to the
instructions. When bit RS = 1, the PCF8820 will load the
data into its DDRAM.
Undefined register locations are not allowed.
The instruction set comprises several command pages.
A command page is selected by setting bits H0 to H2.
The instruction set is given in Table 2.
There are four types of instruction data whose functions
are listed below:
The bit functions are described in detail in Section 8.1.
• Define PCF8820 functions, such as display
configuration, etc.
• Set DDRAM addresses
• Perform data transfers to DDRAM
• Other functions.
Table 2
Instruction set
INSTRUCTION
CONTROL
BITS(1)
RS
R/W
COMMAND BYTE
DESCRIPTION
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Independent command page (H2 = X, H1 = X, H0 = X); note 2
Write data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
writes data to DDRAM
Read
temperature
0
1
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TR0
NOP
0
0
0
0
0
0
0
0
0
0
no operation
Default H2 to H0
0
0
0
0
0
0
0
0
0
1
jumps to function and RAM
command page
reads sensor temperature
read-out
Function and RAM command page (H2 = 0, H1 = 0, H0 = 0)
Instruction set
0
0
0
0
0
0
1
H2
H1
H0
selects a command page
Select function
0
0
0
0
0
1
DO
PD
V
0
data order; power-down
control; address mode
Set Y address of
DDRAM
0
0
0
1
0
Y4
Y3
Y2
Y1
Y0
selects Y-address of
DDRAM: 0 ≤ Y ≤ 16
Set X address of
DDRAM
0
0
1
X6
X5
X4
X3
X2
X1
X0
selects X-address of
DDRAM: 0 ≤ X ≤ 100
selects display mode
Display setting command page (H2 = 0, H1 = 0, H0 = 1)
Display control
0
0
0
0
0
0
0
1
D
E
External display
control
0
0
0
0
0
0
1
MX
MY
PS
mirror X; mirror Y; partial
screen mode
Bias system
0
0
0
0
0
1
0
BS2
BS1
BS0
selects bias system
0
BS1/2
Bias system
2000 Dec 07
1/
2
0
0
0
0
1
1
1
19
0
set bias system 1/2 for partial
screen mode
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
INSTRUCTION
Display part
CONTROL
BITS(1)
PCF8820
COMMAND BYTE
DESCRIPTION
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
0
0
DP2
DP1
DP0
set display for partial screen
mode
HVGen command page (H2 = 0, H1 = 1, H0 = 0)
High voltage
generator
control
0
0
0
0
0
0
0
1
PRS
HVE
set VLCDOUT programming
range and high voltage
generator on
High voltage
generator
configuration
0
0
0
0
0
0
1
S2
S1
S0
set voltage multiplier factor
Temperature
control
0
0
0
0
0
1
0
TC2
TC1
TC0
set temperature coefficient
Temperature
measurement
control
0
0
0
0
1
0
0
0
0
SM
start temperature
measurement
VLCD control
0
0
1
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1
VOP0
set VLCD register value:
0 ≤ VOP ≤ 127
Grey-scale/colour command page (H2 = 0, H1 = 1, H0 = 1)
Grey-scale
register control
0
0
0
1
0
0
0
0
GR1
GR0
select grey-scale register:
0 ≤ GR ≤ 3
Grey-scale level
control
0
0
1
0
GS5
GS4
GS3
GS2
GS1
GS0
set grey-scale register value:
0 ≤ GS ≤ 63
Special feature command page (H2 = 1, H1 = 0, H0 = 0)
Display off,
direct drive
mode
0
0
0
0
0
0
0
1
DOF
DM
display off; voltage multiplier
in direct drive mode
Oscillator setting
0
0
0
0
0
0
1
0
EC
OC
select external clock; start
oscillator calibration
Row block
swapping
0
0
0
1
0
0
0
0
top row swap; bottom row
swap
TRS BRS
Notes
1. Bit R/W is set in the slave address byte; bit RS is set in the control byte.
2. X = don’t care.
2000 Dec 07
20
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
8.1
PCF8820
Description of the bit functions
Table 3
Instruction set bit functions
RESET
STATE
VALUE
D7 to D0
−
−
data to be written to DDRAM
TR7 to TR0
−
−
read-out value of sensor temperature
BIT
H2 to H0
FUNCTION
command page numbers
000
000
function and RAM
001
display setting
010
high voltage generator setting
011
grey-scale/colour
100
special features
DO
data order when written to DDRAM
0
0
1
PD
normal (see Fig.6)
swapped: DB7 <-> DB0, DB6 <-> DB1, etc.
operation mode
0
1
1
V
operating mode
Power-down mode; see Section 8.1.1
address mode
0
0
1
horizontal address mode: data is written to DDRAM (see Fig.10)
vertical address mode: data is written to DDRAM (see Fig.9)
Y4 to Y0
0
−
Y-address of the DDRAM points to the rows; the address range is from
0 to 16 (10H); see Section 8.1.3
X6 to X0
0
−
X-address of the DDRAM points to the columns; the address range is from
0 to 100 (64H)
00
00
display blank: using the value in grey-scale register 0
01
all display segments on: using the value in grey-scale register 3
10
normal mode: using the values of the four grey-scale registers appropriate to the
RAM data
11
inverse video: using the values in all four grey-scale registers as in normal mode
but with their values swapped (GS0 and GS3 values transposed, GS1 and GS2
values transposed)
D, E
display mode
MX
horizontal address space mirroring; see Figs 7 and 8; see Table 10
0
0
disabled: data to DDRAM is written from left (X = 0) to right (X = 100)
1
enabled: data to DDRAM is written from right (X = 0) to left (X = 100)
MY
vertical address space mirroring; see Table 10
0
2000 Dec 07
0
disabled: normal display
1
enabled: data is immediately mirrored vertically on the LCD. The status of bit MY
takes effect when data is read from the DDRAM and when generating column
signals.
21
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
BIT
RESET
STATE
VALUE
PS
0
full display mode: multiplex rate is 1 : 67
1
partial screen mode: multiplex rate is 1 : 8; see Section 8.1.2.
000
−
0
0
setting of bits BS2 to BS0
1
bias system 1/2; see Section 8.1.4
BS1/2
DP2, DP1,
DP0
display part
000
000
DDRAM bank 0 to 1: first 8 rows
111
DDRAM bank 14 to 15: last 8 rows
VLCDOUT programming range; see Fig.20
0
0
LOW range
1
HIGH range
HVE
high voltage generator
0
0
disabled
1
enabled
S2, S1, S0
voltage multiplier factor; see Section 8.1.5
000
000
2 × VDD2
001
3 × VDD2
010
4 × VDD2
011
5 × VDD2
100
6 × VDD2
101
7 × VDD2
110
000
000
coefficient 0
001
coefficient 1
010
coefficient 2
011
coefficient 3
100
coefficient 4
101
coefficient 5
110
coefficient 6
111
coefficient 7
temperature measurement
0
2000 Dec 07
8 × VDD2
temperature coefficient; see Chapter 11
SM
VOP6 to VOP0
bias system selection bits; see Section 8.1.4
bias system selection
PRS
TC2, TC1,
TC0
FUNCTION
screen mode
0
BS2, BS1,
BS0
PCF8820
0
0
no measurement
1
start measurement
−
VLCD control register bits; see Section 8.1.7
22
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
BIT
RESET
STATE
VALUE
GR1, GR0
00
register 0: applied if DDRAM content is 00
01
register 1: applied if DDRAM content is 01
10
register 2: applied if DDRAM content is 10
11
0
−
DOF
register 3: applied if DDRAM content is 11
grey-scale level bits; in the reset state all 4 grey-scale registers are reset to 0;
see Section 8.1.8
display on/off
1
0
display on
1
display off: the state of the PCF8820 is equivalent to Power-down mode
(bit PD = 1). However, temperature measurement is still possible
DM
drive of voltage multiplier
0
0
no direct drive
1
direct drive: VLCDOUT = VDD2; see Section 8.1.9
EC
clock selection
0
1
OC
internal clock
external clock
oscillator setting; see Section 8.1.10
0
0
1
TRS
stop calibration of frame frequency
start calibration of frame frequency
top rows
0
0
not swapped
1
swapped: the signals for row driver outputs R23 to R33 appear at outputs
R56 to R66, and the signals for row driver outputs R56 to R66 appear at
outputs R23 to R33
BRS
bottom rows
0
2000 Dec 07
FUNCTION
grey-scale register selection:
00
GS5 to GS0
PCF8820
0
not swapped
1
swapped: the signals for row driver outputs R0 to R22 appear at outputs
R34 to R55, and the signals for row driver outputs R34 to R55 appear at outputs
R0 to R22
23
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
8.1.1
8.1.3
POWER-DOWN MODE
During power-down (bit PD = 1) all static currents are
switched off (no internal oscillator, no timing, no LCD
segment drive system) and all LCD outputs are internally
connected to VSS.
PCF8820
Y-ADDRESS OF DDRAM
Bits Y4 to Y0 define the Y-address of the DDRAM.
Table 4
Y-address
Y4
Y3
Y2
Y1
Y0
To decrease the voltage at VLCDOUT very fast the following
features can be used:
0
0
0
0
0
bank 0
• Select the direct drive mode by setting bit DM = 1
resulting in VLCDOUT = VDD2
0
0
0
0
1
bank 1
0
0
0
1
0
bank 2
• Select the non direct drive mode by setting bit DM = 0,
resulting in VLCDOUT = 0 V (output high-impedance).
0
0
0
1
1
bank 3
0
0
1
0
0
bank 4
During power-down:
0
0
1
0
1
bank 5
• All LCD outputs at VSS (display off)
0
0
1
1
0
bank 6
0
0
1
1
1
bank 7
0
1
0
0
0
bank 8
• High voltage generator is disabled; however, the status
of bit HVE is unchanged (see Table 8)
0
1
0
0
1
bank 9
0
1
0
1
0
bank 10
• An external VLCD can be disconnected from VLCDIN
0
1
0
1
1
bank 11
• The I2C-bus is operational; commands can be executed
0
1
1
0
0
bank 12
• DDRAM contents is not cleared; DDRAM data can be
written
0
1
1
0
1
bank 13
0
1
1
1
0
bank 14
• Register settings remain unchanged
0
1
1
1
1
bank 15
• Temperature measurement is not possible.
1
0
0
0
0
bank 16
• Oscillator is off
• Intermediate bias voltage generator is off
8.1.2
8.1.4
PARTIAL SCREEN MODE
RAM BANK
BIAS SYSTEM
If bit MY = 0, data is displayed either on rows 0 to 7 (first
8 rows) or on rows 56 to 63 (last 8 rows).
Different LCD bias voltage settings are required at
different multiplex rates. The status of bits BS2 to BS0 and
bit BS1/2 select different ‘bias systems’ which determine
the intermediate bias voltage levels between
VLCDIN and VSS1. It should be noted that the bias system
selected by bit BS1/2 is independent of the bias systems
selected by bits BS2 to BS0.
If bit MY = 1, data is displayed either on rows 66 to 59 (first
8 rows) or on rows 10 to 3 (last 8 rows).
A value ‘n’ attributed to each bias system is used to
calculate these levels (see Table 5).
Partial screen mode allows data to be displayed of
DDRAM bank 0 to 1 on the first 8 rows or bank 14 to 15 on
the last 8 rows, depending on the status of
bits DP2 to DP0.
The partial screen mode also allows VLCDIN to be reduced
to save power.
The optimum value for ‘n’ is given by: n =
M is the multiplex rate.
Frame frequency calibration is not allowed in the partial
screen mode.
2000 Dec 07
M – 3 where
Table 6 shows how bias voltage levels are calculated for
three of the available bias systems using supported ‘n’
values.
24
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
Table 5
PCF8820
Programming the required bias system
BS2
BS1
BS0
BS1/2
n
BIAS SYSTEM
0
0
0
0
7
0
0
1
0
6
0
1
0
0
5
0
1
1
0
4
1
0
0
0
3
1
0
1
0
2
1
1
0
0
1
1
1
1
0
0
X
X
X
1
−2
1/
11
1/
10
1/
9
1/
8
1/
7
1/
6
1/
5
1/
4
1/
2
Table 6
COMMENT
recommended at multiplex rate 1 : 67
recommended at multiplex rate 1 : 8
allows a lower VLCDIN at multiplex rate 1 : 8
Examples of LCD bias voltages
BIAS SYSTEM
BIAS VOLTAGE
LEVEL ON PAD
CALCULATING BIAS
VOLTAGE
VLCDOUT
VLCDIN
V2
n+3
------------- × V LCDIN
n+4
8/
9
× VLCDIN
3/
4
× VLCDIN
V3
n+2
------------- × V LCDIN
n+4
7/
9
× VLCDIN
1/
2
× VLCDIN
VSS1
V4
2
------------- × V LCDIN
n+4
2/
9
× VLCDIN
1/
2
× VLCDIN
VLCDIN
V5
1
------------- × V LCDIN
n+4
1/
9
× VLCDIN
1/
4
× VLCDIN
VSS1
VSS1
8.1.5
1/
9
VLCDIN
VSS1
(n = 0)
VLCDIN
VSS1
1/
2
(n = −2)
VLCDIN
1/
2
1/
2
× VLCDIN
× VLCDIN
VSS1
5. Increment the multiplication factor to the desired value
for VLCDOUT using bits S2 to S0.
HIGH VOLTAGE GENERATOR CONFIGURATION
The PCF8820 incorporates a software configurable
voltage multiplier which uses a charge pump circuit
supplied by VDD2 and VDD3. After a reset the voltage
multiplier factor is set to 2 (VLCDOUT = 2 × VDD2). Other
voltage multiplier factors are set by bits S2 to S0.
8.1.6
TEMPERATURE READ-OUT
The PCF8820 has a built-in temperature sensor. At the
end of a temperature measurement, the sensor writes a
temperature value to the status register. The temperature
value is an 8-bit number represented by bits TR7 to TR0 in
the status register which can be read via the I2C-bus.
To reduce high current peaks at voltage multiplier start-up,
it is recommended that the voltage multiplier is switched on
using the following procedure:
To save power, the sensor need only be enabled when a
measurement is required. A measurement is initialized by
setting bit SM = 1 which will be automatically cleared after
5 clock cycles (from internal oscillator or external clock).
The internal oscillator will be initialized and allowed to
warm-up for approximately 2 frame periods, after which a
measurement will be initiated at the start of the next frame
and completing after 2 frames.
1. Set bit DM = 1 and bit PD = 1
2. Set multiplication factor to 2 by setting bits S2 to S0 to
logic 0
3. Set register value VOP to the desired value,
bit PRS = 1 and bit HVE = 1
4. Set bit PD = 0, which switches on the charge pump
(at multiplication factor 2)
2000 Dec 07
1/
4
(n = 5)
25
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
It is not possible to measure temperature in Power-down
mode.
8.1.7
PCF8820
VLCD CONTROL REGISTER
The VLCDOUT value can be set by software using the
bits VOP6 to VOP0 of the VLCD control register.
During a temperature measurement, the status register
value remains zero until the measurement has completed
and then the register is updated with the current
temperature value (non-zero value). Because the I2C-bus
interface is asynchronous to the temperature
measurement, the value read from the status register
should be validated by reading the status register a few
times.
The programmed value for VLCD has to be calculated for a
reference temperature, called the cut-point temperature
Tcp, using the equation:
VLCD (at Tcp) = a + b × VOP
The values for parameters Tcp, a and b are given in
Table 7, and their relationship with the VLCD control
register values are shown in Fig.20.
During a temperature measurement, the temperature
coefficient (TC) has to be selected.
The VLCDOUT generated is dependent on the operating
temperature Toper, the selected temperature coefficient TC
and the programmed value for VLCD at the reference
temperature Tcp and is calculated by the equation:
The ideal temperature read-out can be calculated by the
1
equation: TR ideal = 128 + ( T – 27 °C ) × --a
VLCD (at Toper) = VLCD (at Tcp) × {1 + TC × (Toper − Tcp)}
where T is the on-chip temperature in °C and ‘a’ is the
conversion constant (see Chapter 11).
Two overlapping VLCD ranges are selectable by bit PRS
(see Table 7 and Fig.20). The maximum voltage that can
be generated depends on the values of VDD2 and VDD3,
and the display load current. At a multiplex rate of 1 : 67,
the optimum operating voltage for the LCD can be
calculated by the equation:
To improve the accuracy of the temperature
measurement, it is recommended that the temperature
read-out is calibrated during the product’s final assembly.
Calibration of the temperature read-out requires a
measurement to be made at a defined ideal temperature.
The offset between the ideal temperature value and the
measured temperature value is calculated by:
1 + 67 + 1
V LCD = ------------------------------------------------- × V th ≅ 6.975 × V th
1
2 ×  1 – --------------------

67 + 1
TRoffset = TRideal − TRmeas
where TRmeas is the actual temperature read-out of the
PCF8820. The offset value must be stored in a non-volatile
register, such as an EEPROM.
where Vth is the threshold voltage of the liquid crystal
material used.
A calibrated temperature read-out can be calculated for
each measurement by the equation:
The practical value for VLCD is determined by equating
Voff(rms) with the defined LCD threshold voltage (Vth), which
is the typically value when the LCD exhibits approximately
10% contrast.
TRcal = TRmeas + TRoffset
The accuracy after the calibration is ±10% ±1 bit of the
difference between the measured temperature and the
calibration temperature. For this reason, it is
recommended that a calibration is performed at or near the
most sensitive LCD temperature.
Table 7
VALUE
SYMBOL
For example: calibration temperature is 25 °C and the
measured temperature is −20 °C. The relative error
A = ±0.10 × {25 − (−20)} ±1 bit × a
A = ±4.5 ±1.13
This calibration accuracy is valid for temperature
measurements made when the supply voltage value is the
same as when it was calibrated.
26
UNIT
BIT PRS = 0
BIT PRS = 1
Tcp
23.0
23.0
°C
a
4.500
10.215
V
b
0.045
0.045
V
programming
range
A = ±5.63 °C.
2000 Dec 07
Parameter values for programming VLCD control
register
4.5 to 10.215
10.215 to 15.93 V
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
handbook, full pagewidth
VLCD
(V)
b
a
00
01
02
03
04
05
06
. . . 7D
7E
7F
00
LOW(1)
01
02
03
04
05
06
. . . 7D
7E
7F
register
value
HIGH(2)
MGT128
(1) Bit PRS = 0: VLCD programming range is LOW.
(2) Bit PRS = 1: VLCD programming range is HIGH.
Fig.20 Generated VLCDOUT set by programming VLCD control register value (bits VOP6 to VOP0).
The programming range for the generated VLCDOUT allows
values above the maximum value of VLCD. Therefore, the
user must ensure that the VLCD control register value and
the temperature coefficient selected, will never allow the
maximum VLCD limit to be exceeded for all conditions and
including all tolerances. The customer must also ensure
that the VLCD control register value will never be lower than
VDD1 or VDD2, except in the Power-down mode, for all
conditions and including all tolerances.
The grey-scale level for each pixel is effected by writing the
resultant grey-scale register value into the DDRAM (see
Fig.6).
8.1.8
A blinking cursor can be effected by continuously
switching the content of one grey-scale register between
the two grey-scales from e.g. white to black and back
again with a frequency of 2 Hz giving the impression of a
blinking cursor. This procedure causes less load for the
microcontroller than changing all pixels which form the
desired cursor. This implies the display has 3 grey-scale
levels left e.g. off, grey and on.
One of the grey-scale registers can be used to create a
blinking cursor. The intensity of the pixels comprising the
cursor are to be defined by the value in the grey-scale
register. The brightness/colour of the cursor pixels can be
changed by selecting a different grey-scale register
containing a different grey-scale value.
GREY-SCALE REGISTER AND GREY-SCALE LEVEL
The PCF8820 has 4 grey-scale registers selected by bits
GR0 and GR1, which define the four grey intensity levels.
Each of the 4 registers contain 6 bits allowing to select one
out of the 64 grey levels. A grey-scale register must be
addressed before it can be written to by using the
instruction ‘Grey-scale register’ (see Table 2). The content
of the grey-scale register (bits GS5 to GS0) is set by the
instruction ‘Grey-scale level control’ (see Table 2). It
should be noted that a grey-scale register setting of 63 is
internally converted to 64. Even numbers are preferred;
odd numbers produce a small DC component in the
waveform of the respective column (see Fig.3).
2000 Dec 07
27
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
8.1.9
The resulting frame frequency is calculated by the
f clk
equation: f frame = ------------- × pre-divider ratio [ Hz ]
1088
DIRECT DRIVE MODE
The voltage multiplier is in the direct drive mode
(VLCDOUT = VDD2) in the following settings (see Table 8):
• If bit DM = 1 and Power-down mode (bit PD = 1)
where fclk can be either the internal oscillator clock signal
or an external clock signal source.
• If bit DM = 1 and display off mode (bit DOF = 1)
• If bit DM = 1 and high voltage generator is disabled
(bit HVE = 0).
Figure 21 shows the resulting frame frequency at different
clock frequencies and at different pre-divider ratios, for a
calibration period of 190 µs.
It is recommended to always select the direct drive mode
before switching on the voltage multiplier. This is a feature
which can be used to reduce VLCDOUT very quickly, or to
avoid high current when the voltage multiplier starts up.
The frame frequency calibration can also be used to set
the frame frequency to a lower than typical value with a
corresponding reduction in current consumption. The
necessary calibration period (time between calibration
start and stop) can be estimated by the equation:
77 (Hz) × 190 ( µs )
t cal = ------------------------------------------------f frame
Output VLCDOUT is high-impedance when bit DM = 0 and
bit PD = 1, bit DM = 0 and bit DOF = 0 or when bit DM = 0,
bit PD = 0 and bit HVE = 0.
Table 8
Output VLCDOUT as a function of bits DM, HVE,
PD and DOF; note 1
DM
HVE
PD
DOF
0
X
1
X
high Z
0
X
X
1
high Z
0
0
0
0
high Z
1
0
0
0
VDD2
1
X
1
X
VDD2
1
X
X
1
VDD2
X
1
0
0
internally generated VLCD
where tcal is the calibration time in µs and fframe is the
desired frame frequency in Hz.
VLCDOUT
Figure 22 shows the resulting frame frequency as a
function of the calibration period at different pre-divider
ratios at a clock frequency of 336 kHz.
8.2
1. X = don’t care.
After VDD1 has reached its minimum value, the RES input
level must be ≤0.3VDD1 after a maximum time tsu
(see Fig.24).
FRAME FREQUENCY CALIBRATION
The PCF8820 uses on-chip software to calibrate the frame
frequency. After reset, the frame frequency calibration is
disabled (bit OC = 0). Frame frequency calibration can
only be performed if the PCF8820 is not in Power-down
mode or in the partial screen mode.
After reset the state of the PCF8820 is as follows:
• Default values of bits and registers as seen in Table 3
• All row and column outputs are at VSS (display off)
• VLCDOUT is high-impedance
The calibration is initiated by setting bit OC = 1 and is
stopped by setting bit OC = 0. The time between
calibration start and stop must be 190 µs to give a frame
frequency of 77 Hz (typical value).
• RAM data is undefined.
All other commands are allowed during a calibration.
The frame frequency calibration uses a pre-divider which
has a range from 1 : 1 to 1 : 15. The default ratio after reset
is 1 : 4. The calibration period determines the pre-divider
ratio for the oscillator frequency or external clock signal.
2000 Dec 07
Reset and initialization
After power-on the content of all internal registers
including the DDRAM are in an undefined state. A reset
pulse must be applied within a specified time to reset all
internal registers. A reset can be achieved by applying an
external reset pulse (active LOW) to pad RES. When reset
occurs within the specified time all internal registers are
reset, however the DDRAM is still undefined.
Note
8.1.10
PCF8820
28
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
MGT129
100
handbook, full pagewidth
1:2
95
f frame
(Hz)
90
1:3
1:4
1:5
85
1:6
1:7
1:8
80
75
70
65
60
150
250
200
300
350
400
450
500
550
600
650
700
750
fclk (kHz)
tcal = 190 µs.
Fig.21 Calibrated frame frequency as a function of clock frequency and pre-divider ratio.
MGT130
110
handbook, full pagewidth
1:3
100
f frame
(Hz) 90
80
1:4
70
1:5
60
1:6
50
1:7
1:8
40
1:9
1:10
30
1:11
1:12
1:13
1:14
1:15
20
10
100
150
200
250
300
350
400
450
500
550
600
650
700
750
t cal (µs)
fclk = 336 kHz.
Fig.22 Frame frequency as a function of the calibration time and pre-divider ratio.
2000 Dec 07
29
800
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+6.5
V
VLCDIN
supply voltage for the LCD
−0.5
+15
V
Vn
voltage on
any VLCD related pin
−0.5
VLCDIN + 0.5
V
any other pin
−0.5
VDD1 + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
ISS
ground supply current
−50
+50
mA
Ptot
total power dissipation
−
100
mW
P/out
power dissipation per output
−
10
mW
Tamb
ambient temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
Tj
junction temperature
−
150
°C
V
Note
1. All voltages are referred to VSS = 0 V. Stress above one or more of the limiting values may cause permanent damage
to the device. These are stress ratings only and operation of the device at these or at any other conditions above
those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability. Parameters are valid over operating temperature range unless otherwise
specified.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ).
11 CHARACTERISTICS
VDD1 = 2.5 to 5.5 V; VDD2 = VDD3 = 2.7 to 5.5 V; VSS1 = VSS2 = 0 V; VLCDIN = 4.5 to 14.5 V; Tamb = −40 to +85 °C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD1
supply voltage 1 of logic
circuits
2.5
−
5.5
V
VDD2
supply voltage 2 of voltage
multiplier
2.7
−
5.5
V
VDD3
supply voltage 3 of voltage
multiplier
2.7
−
5.5
V
VLCDIN
supply voltage of LCD
graphic mode
7.0
−
14.5
V
partial screen mode;
note 1
VDD
−
14.5
V
2000 Dec 07
30
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
SYMBOL
IDD(tot)
ILCDIN
PARAMETER
total supply current into
pins VDD1, VDD2 and VDD3
supply current of VLCDIN
2000 Dec 07
PCF8820
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Power-down mode;
VLCDIN = 8.6 V (external);
notes 2 and 3
−
0.5
10
µA
partial screen mode;
VLCDIN = 4.5 V (external);
note 3
−
15
35
µA
partial screen mode;
VLCDIN = 4.5 V (internal);
LCD load is 10 µA;
voltage multiplier factor 3;
bias system = 1/6;
notes 3 and 4
−
210
300
µA
normal mode;
VLCDIN = 8.6 V (external);
note 3
−
20
35
µA
normal mode;
VLCDIN = 8.6 V (internal);
LCD load is 10 µA;
voltage multiplier factor 5;
bias system = 1/9;
notes 3 and 4
−
430
680
µA
Power-down mode;
VLCDIN = 8.6 V (external);
bias system = 1/9;
VLCD control value = 28H;
bit PRS = 1;
notes 3 and 5
−
6
15
µA
partial screen mode;
VLCDIN = 4.5 V (external);
LCD load is 10 µA;
bias system = 1/6;
VLCD control value = 00H;
bit PRS = 0;
notes 3, 4 and 5
−
45
70
µA
normal mode;
VLCDIN = 8.6 V (external);
LCD load is 10 µA;
bias system = 1/9;
VLCD control value = 5CH;
bit PRS = 0;
notes 3, 4 and 5
−
60
95
µA
31
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
SYMBOL
PARAMETER
PCF8820
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Logic inputs
PADS SA0, SA1, RES, T1, T3, T4 and T5
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IL
leakage current
VI = VDD1 or VSS1
VSS1
−
0.3VDD1
V
0.7VDD1
−
VDD1
V
−1
−
+1
µA
PAD OSC
VI
LOW-level input voltage
VSS1
−
VSS1 + 0.1 V
VI
HIGH-level input voltage
VDD1 − 0.1
−
VDD1
V
IL
leakage current
−1
−
+1
µA
VSS1
−
0.3VDD1
V
VI = VDD1 or VSS1
I2C-bus
PADS SDA_IN and SCL
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IL
leakage current
0.7VDD1
−
5.5
V
VI = VDD1 or VSS1
−1
−
+1
µA
PAD SDA_OUT
IOL
LOW-level output current
VOL = 0.4 V; VDD1 = 5 V
3.0
−
−
mA
IL
leakage current
VI = VDD1 or VSS1
−1
−
+1
µA
Column and row outputs
Rcol
column output resistance
C0 to C100
VDD1 = 5 V; VLCDIN = 12 V; −
IL = 100 µA; outputs tested
one at a time
−
10
kΩ
Rrow
row output resistance
R0 to R66
VDD1 = 5 V; VLCDIN = 12 V; −
IL = 100 µA; outputs tested
one at a time
−
3.0
kΩ
Vbias(col)
bias voltage tolerance
C0 to C100
−100
0
+100
mV
Vbias(row)
bias voltage tolerance
R0 to R66
−100
0
+100
mV
−
−
4.6
%
LCD supply voltage generator
STABILITY
∆VLCDOUT tolerance of internally
generated VLCDOUT
Tamb = −20 to +85 °C;
VLCDOUT ≤ 12 V
TEMPERATURE COEFFICIENT OF VLCDOUT; Tamb = −20 TO +85 °C
TC0
temperature coefficient 0
−
−0.04 × 10−3 −
K−1
TC1
temperature coefficient 1
−
−1.89 × 10−3 −
K−1
TC2
temperature coefficient 2
−
−2.05 × 10−3 −
K−1
TC3
temperature coefficient 3
−
−2.22 ×
−
K−1
TC4
temperature coefficient 4
−
−2.38 × 10−3 −
K−1
2000 Dec 07
32
10−3
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
SYMBOL
PARAMETER
PCF8820
CONDITIONS
MIN.
TYP.
10−3
MAX.
UNIT
TC5
temperature coefficient 5
−
−2.55 ×
−
K−1
TC6
temperature coefficient 6
−
−2.72 × 10−3 −
K−1
TC7
temperature coefficient 7
−
−2.98 × 10−3 −
K−1
−
23
−
°C
REFERENCE TEMPERATURE
Tcp
cut-point temperature
Temperature read-out
a
conversion constant
atol
tolerance of a
−
1.13
−
°C/bit
same supply voltage VDD
−
−
10
%
repeatability
−
−
1
bit
affect of changing VDD
−
−
0.5
bit/V
Notes
1. The minimum value for VLCDIN is limited by the supply voltages VDD1 and VDD2:
a) For VDD1 ≤ 4.5 V and VDD2 ≤ 4.5 V: VLCDIN > 4.5 V.
b) For VDD1 > 4.5 V or VDD2 > 4.5 V: VLCDIN > highest value of VDD1 or VDD2.
2. All static currents are switched off in Power-down mode; no external clock.
3. VDD1 = VDD2 = VDD3 = 2.75 V; LCD outputs are open-circuit; inputs connected to VDD1 or VSS1; I2C-bus inactive;
external clock with fext = 336 kHz; Tamb = 27 °C.
4. The typical currents are measured on a sample base with the DDRAM and grey-scale registers loaded with data
which would produce the display shown in Fig.23 if an LCD was connected. Extensive use of grey-scales will
increase current consumption compared to black and white mode. If specified, the maximum current is tested with a
regular pattern which is equivalent in current to the display shown in Fig.23.
5. Voltage multiplier disabled; pins VLCDIN, VLCDOUT and VLCDSENSE connected together.
handbook, full pagewidth
MGT131
Fig.23 Display used to define DDRAM and grey-scales for current measurements.
2000 Dec 07
33
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
12 TIMING
VDD1 = 2.5 to 5.5 V; VDD2 = VDD3 = 2.7 to 5.5 V; VSS1 = VSS2 = 0 V; VLCDIN = 4.5 to 14.5 V; Tamb = −40 °C to +85 °C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock signal
fframe
LCD frame frequency
not calibrated; note 1
44
77
158
Hz
fframe(cal1)
LCD frame frequency
calibrated; accurate calibration
timing of 190 µs; note 2
68
77
91
Hz
fframe(cal2)
LCD frame frequency
calibrated; accurate calibration
timing of 190 µs
63
77
96
Hz
fosc
oscillator frequency
not calibrated; note 3
190
336
670
kHz
external clock frequency
not calibrated
190
336
670
kHz
PAD OSC
fext
Reset timing; see Fig.24
PAD RES
tWL
reset pulse width LOW
1.0
−
−
µs
tWH
reset pulse width HIGH
1.5
−
−
µs
tW(spike)
tolerable spike width on RES
input
−
−
10
ns
tsu
reset-LOW pulse set-up time
after power-on
−
−
30
µs
toper
end of reset to interface being
operational
−
−
3
µs
VDD = 2.75 V; note 4
LCD on and off timing; see Fig.25
PAD VLCDIN
tLCD(on)
external LCD turn-on time
after VDD1 turns on
1
−
−
ms
tLCD(off)
external LCD turn-off time
before VDD1 turns off
1
−
−
ms
I2C-bus timing; see Fig.26; note 5
PADS SCL and SDA
fSCL
SCL clock frequency
0
−
400
kHz
tLOW
SCL LOW time
1.3
−
−
µs
tHIGH
SCL HIGH time
0.6
−
−
µs
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
0.9
µs
tr
rise time SDA and SCL
note 6
20 + 0.1 Cb
−
300
ns
tf
fall time SDA and SCL
note 6
20 + 0.1 Cb
−
300
ns
Cb
capacitive load represented by
each bus line
−
−
400
pF
tSU;STA
set-up time repeated START
0.6
−
−
µs
tHD;STA
hold time START condition
0.6
−
−
µs
2000 Dec 07
34
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
SYMBOL
PARAMETER
PCF8820
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tSU;STO
set-up time for STOP condition
0.6
−
−
µs
tW(spike)
tolerable spike width on bus
−
−
50
ns
tBUF
BUS free time
1.3
−
−
µs
Notes
f ext
f osc
1. Frame frequency: f frame = ------------ or f frame = ------------4352
4352
2. VDD unchanged after frequency calibration.
3. Not available at any pad.
4. Decoupling capacitor between VLCDIN and VSS1 is 100 nF. A higher capacitance increases tsu and a higher VDD1,
VDD2 or VDD3 reduces tsu.
5. All timing values are valid within VDD1, VDD2, VDD3 and Tamb ranges and are referenced to VIL and VIH with an input
voltage swing from VSS1 to VDD1.
6. Cb is the total capacitance (in pF) of one bus line.
handbook, full pagewidth
VDD1
t WH
RES
t WL
t WL
VDD1
t su
t WH
RES
t WL
t WL
RES
t oper
SDA,
SCL
MGT135
Fig.24 Reset timing.
2000 Dec 07
35
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
handbook, full pagewidth
VDD1
VLCDIN
t LCD(off)
t LCD(on)
MGT136
Fig.25 Timing diagram of applying and removing the external LCD supply voltage to and from pad VLCDIN.
ook, full pagewidth
SDA
t BUF
tf
t LOW
SCL
t HD;STA
t HD;DAT
tr
t HIGH
t SU;DAT
SDA
MGA728
t SU;STA
Fig.26 I2C-bus timing.
2000 Dec 07
36
t SU;STO
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
13 APPLICATION INFORMATION
13.1
Programming example for the PCF8820
It should be noted that only a part of the LCD is shown in the LCD column of Table 9.
Table 9
Programming example
SERIAL BUS BYTE
STEP
LCD
OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
1
1
1
0
start slave address, R/W = 0
2
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
3
0
0
0
0
0
0
0
1
H2 to H0 independent command:
select function and RAM command
page (H2 to H0 = 000)
4
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
5
0
0
0
0
1
0
0
1
function and RAM command page:
select display setting command
page (H2 to H0 = 001)
6
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
7
0
0
0
0
0
1
1
0
display setting command page: set
normal display mode (D = 1, E = 0)
8
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
9
0
0
0
1
0
0
1
0
display setting command page: set
bias system = 1/9
(BS2 to BS0 = 010)
10
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
11
0
1
0
0
0
0
0
0
display setting command page:
select first 8 rows for partial screen
mode (DP2 to DP0 = 000)
12
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
13
0
0
0
0
0
0
0
1
H2 to H0 independent command:
select function and RAM command
page (H2 to H0 = 000)
14
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
15
0
0
0
1
0
1
1
0
function and RAM command page:
select Power-down mode (PD = 1)
and vertical address mode (V = 1)
16
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
17
0
0
0
0
1
1
0
0
function and RAM command page:
select special feature command
page (H2 to H0 = 100)
18
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
19
0
0
0
0
0
1
0
1
special feature command page:
enable display (DOF = 0) and
enable direct drive (DM = 1) to
pre-charge the charge pump
20
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
2000 Dec 07
SA1 SA0
37
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
SERIAL BUS BYTE
STEP
LCD
OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
21
0
0
0
0
0
0
0
1
H2 to H0 independent command:
select function and RAM command
page (H2 to H0 = 000)
22
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
23
0
0
0
0
1
0
1
0
function and RAM command page:
select HVGen command page
(H2 to H0 = 010)
24
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
25
0
0
0
0
1
0
0
0
HVGen command page: select
voltage multiplier factor 2×
(S2 to S0 = 000)
26
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
27
0
0
0
1
0
0
1
0
HVGen command page: select
temperature coefficient 2
(TC2 to TC0 = 010)
28
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
29
0
0
0
0
0
1
0
0
HVGen command page: select
LOW VLCD programming range
(PRS = 0), HVGen off (HVE = 0)
30
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
31
1
1
0
1
1
0
1
1
HVGen command page: set
VLCD to 8.595 V
(VOP6 to VOP0 = 1011011)
32
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
33
0
0
0
0
0
0
0
1
H2 to H0 independent command:
select function and RAM command
page (H2 to H0 = 000)
34
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
35
0
0
0
0
1
0
1
1
function and RAM command page:
select grey-scale/colour command
page (H2 to H0 = 011)
36
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
37
0
1
0
0
0
0
0
0
grey-scale/colour command page:
select grey-scale register 0
(GR1 to GR0 = 00)
38
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
39
1
0
0
0
0
0
0
0
grey-scale/colour command page:
set grey-scale to 0
(GS5 to GS0 = 000000)
40
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
41
0
1
0
0
0
0
0
1
grey-scale/colour command page:
select grey-scale register 1
(GR1 to GR0 = 01)
42
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
2000 Dec 07
38
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
SERIAL BUS BYTE
STEP
LCD
OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
43
1
0
0
1
0
1
0
0
grey-scale/colour command page:
set grey-scale to 20
(GS5 to GS0 = 010100)
44
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
45
0
1
0
0
0
0
1
0
grey-scale/colour command page:
select grey-scale register 2
(GR1 to GR0 = 10)
46
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
47
1
0
1
0
1
0
0
0
grey-scale/colour command page:
set grey-scale register 2 to 40
(GS5 to GS0 = 101000)
48
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
49
0
1
0
0
0
0
1
1
grey-scale/colour command page:
select grey-scale register 3
(GR1 to GR0 = 11)
50
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
51
1
0
1
1
1
1
1
1
grey-scale/colour command page:
set grey-scale register 3 to 63
(GS5 to GS0 = 111111)
52
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
53
0
0
0
0
0
0
0
1
H2 to H0 independent command:
select function and RAM command
page (H2 to H0 = 000)
54
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
55
0
0
0
0
1
0
1
0
function and RAM command page:
select HVGen command page
(H2 to H0 = 010)
56
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
57
0
0
0
0
0
1
0
1
HVGen command page: enable
HVGen (HVE = 1) and select LOW
VLCD programming range
(PRS = 0)
58
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
59
0
0
0
0
0
0
0
1
H2 to H0 independent command:
select function and RAM command
page (H2 to H0 = 000)
60
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
61
0
0
0
1
0
0
1
0
function and RAM command page:
select normal operation (PD = 0)
and vertical address mode (V = 1)
62
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
63
0
0
0
0
1
0
1
0
function and RAM command page:
select HVGen command page
(H2 to H0 = 010)
2000 Dec 07
39
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
SERIAL BUS BYTE
STEP
LCD
OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
64
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
65
0
0
0
0
1
0
0
1
HVGen command page: select
voltage multiplier factor 3×
(S2 to S0 = 001, incremented to 3x)
66
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
67
0
0
0
0
1
0
1
0
HVGen command page: select
voltage multiplier factor 4
(S2 to S0 = 010)
68
1
0
0
0
0
0
0
0
control byte: Co = 1, RS = 0
69
0
0
0
0
1
0
1
1
HVGen command page: select
voltage multiplier factor 5
(S2 to S0 = 011, incremented to 5x)
70
0
1
0
0
0
0
0
0
control byte: Co = 0, RS = 1
71
1
1
1
1
1
1
1
1
data write column 0 (vertical
addressing): address X and Y are
initialized to 0 by default, so they
are not set here
MGT143
72
0
0
0
0
0
0
1
1
data write: next write to subsequent
rows filling up column 0 with ‘00H’
MGT144
73 to 89
0
0
0
0
0
0
0
0
90
0
0
1
1
0
0
1
1
91
0
0
0
0
0
0
0
0
no display change
data writes (17 bytes)
data write column 1 (vertical
addressing)
MGT145
data write
MGT145
92 to
108
0
0
0
0
0
0
0
0
109
0
0
1
1
1
1
1
1
no display change
data writes (17 bytes)
data write column 2 (vertical
addressing)
MGT146
110
0
0
0
0
0
0
0
0
data write
MGT146
111 to
127
0
2000 Dec 07
0
0
0
0
0
0
0
no display change
40
data writes (17 bytes)
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
SERIAL BUS BYTE
STEP
LCD
OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
128
0
0
0
0
0
0
0
0
data write column 3 (vertical
addressing)
MGT146
129
0
0
0
0
0
0
0
0
data write
MGT146
130 to
146
0
0
0
0
0
0
0
0
147
1
1
1
1
1
1
1
1
no display change
data writes (17 bytes)
data write column 4 (vertical
addressing)
MGT147
148
0
0
0
0
0
0
1
1
149 to
165
0
0
0
0
0
0
0
0
166
0
0
1
1
0
0
0
0
data write
MGT148
no display change
data writes (17 bytes)
data write column 5 (vertical
addressing)
MGT149
167
0
0
0
0
0
0
0
0
data write
MGT149
168 to
184
0
0
0
0
0
0
0
0
185
1
1
1
1
1
1
1
1
186
0
0
0
0
0
0
1
1
no display change
data writes (17 bytes)
data write column 6 (vertical
addressing)
MGT150
data write: last data; stop
transmission
MGT151
187
0
1
1
1
1
0
no display change
restart, slave address, R/W = 0
188
1
0
0
0
0
0
0
0
no display change
control byte: Co = 1, RS = 0
189
0
0
0
0
0
0
0
1
no display change
H2 to H0 independent command:
select function and RAM command
page (H2 to H0 = 000)
2000 Dec 07
SA1 SA0
41
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
SERIAL BUS BYTE
STEP
LCD
OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
190
1
0
0
0
0
0
0
0
no display change
control byte: Co = 1, RS = 0
191
0
0
0
0
1
0
0
1
no display change
function and RAM command page:
select display setting command
page (H2 to H0 = 001)
192
1
0
0
0
0
0
0
0
no display change
control byte: Co = 1, RS = 0
193
0
0
0
0
0
1
1
1
display mode: set inverse video
mode (D = 1, E = 1)
MGT152
194
1
0
0
0
0
0
0
0
no display change
control byte: Co = 1, RS = 0
195
0
0
0
0
0
0
0
1
no display change
H2 to H0 independent command:
select function and RAM command
page (H2 to H0 = 000)
196
1
0
0
0
0
0
0
0
no display change
control byte: Co = 1, RS = 0
197
1
0
0
0
0
0
0
0
no display change
set X address of RAM to ‘0000000’
198
1
0
0
0
0
0
0
0
no display change
control byte: Co = 1, RS = 0
199
0
1
0
0
0
0
0
0
no display change
set Y address of RAM to ‘00000’
200
0
1
0
0
0
0
0
0
no display change
control byte: Co = 0, RS = 1
201
0
1
0
1
0
1
0
1
202
0
0
0
0
0
0
0
1
data write column 1 (vertical
addressing mode)
MGT153
data write: last data; stop
transmission
MGT154
2000 Dec 07
42
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
13.2
PCF8820
Examples of effects on the display
Table 10 Examples showing the effects on the LCD of setting bits PS, DP2 to DP0, MX and MY
EXAMPLE
1
PS
0
DP2 DP1 DP0
MX
MY
X
0
0
X
X
DISPLAY
DESCRIPTION
normal display
MGT155
2
0
X
X
X
1
0
X mirrored only
MGT156
3
0
X
X
X
0
1
Y mirrored only
MGT157
4
0
X
X
X
1
1
X and Y mirrored
MGT158
5
1
0
0
0
0
0
partial screen mode only; first 8 rows
selected
MGT159
6
1
0
0
0
1
0
partial screen mode; X mirrored; first 8
rows selected
MGT160
7
1
0
0
0
0
1
partial screen mode; Y mirrored; first 8
rows selected
MGT161
8
1
0
0
0
1
1
partial screen mode; X and Y mirrored;
first 8 rows selected
MGT162
9
1
1
1
1
0
0
partial screen mode; last 8 rows
selected
MGT163
2000 Dec 07
43
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
EXAMPLE
10
PS
1
DP2 DP1 DP0
MX
MY
1
1
0
1
1
PCF8820
DISPLAY
DESCRIPTION
partial screen mode; X mirrored; last 8
rows selected
MGT164
11
1
1
1
1
0
1
partial screen mode; Y mirrored; last 8
rows selected
MGT165
12
1
1
1
1
1
1
partial screen mode; X and Y mirrored;
last 8 rows selected
MGT166
2000 Dec 07
44
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
13.3
PCF8820
The characteristics shown for each voltage multiplier
factor are terminated before VLCDOUT has been reached
the maximum value to indicate that the voltage cannot be
increased any further. If a higher voltage is required, a
higher voltage multiplier factor must be selected.
High voltage generator
The high voltage generator contains a voltage multiplier
which uses a charge pump circuit supplied by VDD2 and
VDD3. The multiplier is software programmable with a
factor from 2 to 8. In the direct drive mode the output
voltage VLCDOUT = VDD2.
Connecting a LCD may increase the current into
pad VLCDIN which may affect the current taken by the
charge pump and also its efficiency. The amount of current
load may depend on the type of LCD used.
When the charge pump is used the total supply current of
the PCF8820 at a supply voltage of 3, 4 and 5 V is shown
in Figs 27, 28 and 29.
It is advisable to evaluate the PCF8820 connected to the
desired LCD and set to the required mode(s) to produce
characteristics similar to Figs 27, 28 and 29. The
customer can then use these graphs to select the most
efficient and safe voltage multiplier factor for each mode
required.
The separate graphs are shown for each voltage multiplier
factor with the following conditions:
• At Tamb
• VDD1, VDD2 and VDD3 connected to the same power
supply
• Supply line resistors of 50 Ω (typical value)
• Internal clock not calibrated
• No LCD connected to the PCF8820
• All pixels defined at grey-scale level 32; this is the worst
case
• Bias system 1⁄9
• Full screen mode (bit PS = 0) at a multiplex rate of 1 : 67
• Normal display mode.
MGT132
1.2
handbook, full pagewidth
IDD(tot)
(mA)
1.0
x8
x7
0.8
x6
0.6
x5
0.4
x4
x3
0.2
x2
0
4
5
6
7
8
9
10
11
12
13
Fig.27 Charge pump characteristics for VDD = 3 V.
2000 Dec 07
45
14
15
16
programmed VLCDOUT (V)
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
MGT133
1.0
handbook, full pagewidth
IDD(tot)
(mA)
x8
0.8
x7
x6
x5
0.6
x4
0.4
x3
0.2
x2
0
4
5
6
7
8
9
10
11
12
13
14
15
16
programmed VLCDOUT (V)
Fig.28 Charge pump characteristics for VDD = 4 V.
MGT134
1.0
handbook, full pagewidth
IDD(tot)
(mA)
x8
0.8
x7
x6
0.6
x5
x4
0.4
x3
0.2
x2
0
4
5
6
7
8
9
10
11
12
13
14
15
16
programmed VLCDOUT (V)
Fig.29 Charge pump characteristics for VDD = 5 V.
2000 Dec 07
46
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
13.4
PCF8820
The common supply resistor values especially, have to be
minimized (<5 Ω for high supply voltage VP1, VLCD and
GND).
Application for COG
The PCF8820 physical pad positions are optimized for
single plane wiring e.g. for Chip-On-Glass (COG) display
modules (see Fig.30). The pad lines are as follows:
The minimum value required for the external capacitors is:
• 3 input/output lines: SDA, SCL and RES
• Cext1 > 470 nF (Cext1 > Cext2 recommended)
• 101 column driver lines
• Cext2 > 100 nF (470 nF to 1 µF recommended).
• 33 and 34 row driver lines
A higher value of the capacitors is recommended to reduce
the ripple voltage.
• pads SA0, SA1 and OSC can be tied in the application
to appropriate levels.
For COG applications, it is recommended that the Indium
Tin Oxide (ITO) track resistance is minimized for the I/O
and power supply connections. These connections should
have an optimum track resistance of <50 Ω for the power
supply connections and <100 Ω for the I/O connections.
Increasing the track resistance reduces the performance
and increases the current consumption.
handbook, full pagewidth
LCD
(67 × 101 pixels)
101 colum drivers
VSS1
VSS2
VDD1
VDD2
VDD3
RES
SCL
SDA_IN
PCF8820
33 row drivers
VLCDIN
VLCDSENSE
VLCDOUT
34 row drivers
R I/O
Rsupply
Rcommon
Cext1
Cext2
3
I/O
VP1
GND
VLCD
MGT137
Fig.30 Application diagram for COG display module.
2000 Dec 07
47
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
13.5
Typical system configuration
13.6
The PCF8820 is a low power LCD driver designed to
interface with microcontrollers and a wide variety of LCDs.
PCF8820
External supply of VLCDIN
If an external LCD supply voltage is used, it must be
connected to pad VLCDIN. If pads VLCDOUT, VLCDSENSE and
VLCDIN are connected together, the impedance of
pad VLCDOUT should be set high-impedance by setting the
status of bits shown in Table 8. To obtain the highest
resistance and the lowest current into pad VLCDSENSE, it is
recommended to set the VLCD programming range to
HIGH (bit PRS = 1) and the VLCD control register value to
127 (maximum value) with bits VOP6 to VOP0.
The host microcontroller and the PCF8820 are both
connected to the I2C-bus. The SDA and SCL lines must be
connected to the positive power supply via pull-up
resistors.
The internal oscillator requires no external components.
The appropriate intermediate biasing voltage for the
multiplexed LCD waveforms are generated on-chip.
It should be noted that VLCDIN is not allowed to be lower
than VDD1.
The only other connections required to complete the
system are the power supplies (VDD1, VDD2 and VDD3) and
ground supplies (VSS1 and VSS2), LCD supply (VLCDIN) and
system reset (RES), including suitable capacitors for
decoupling.
An external VLCD must be applied after applying VDD1, and
it must be turned off before (or when) VDD1 is turned off
(see Fig.25). It is recommended that the external VLCD is
applied after leaving the reset state. The external VLCD can
stay turned on in Power-down mode.
VLCD
handbook, full pagewidth
VP1
VLCDIN
VLCDSENSE
101 column drivers
67 row drivers
LCD PANEL
RES
SA1
SA0
SDA_OUT
SCL
SDA_IN
VSS2
Rpu
PCF8820
VSS1
Rpu
HOST
MICROCONTROLLER
VDD3
VLCDOUT
OSC
VDD1
VDD2
VP2 ≤ 5.5 V
RES
SCL
I2C-bus
SDA
MGT138
Fig.31 Typical system configuration.
2000 Dec 07
48
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
14 BONDING PAD INFORMATION
COORDINATES(1)
SYMBOL
COORDINATES(1)
SYMBOL
x
PAD
x
dummy
PAD
1
−5443.7
y
col 13
39
−2573.7
−1162.5
−1162.5
col 14
40
−2503.7
−1162.5
−2433.7
−1162.5
y
dummy
2
−5373.7
−1162.5
col 15
41
row 0
3
−5233.7
−1162.5
col 16
42
−2363.7
−1162.5
row 1
4
−5163.7
−1162.5
col 17
43
−2293.7
−1162.5
row 2
5
−5093.7
−1162.5
col 18
44
−2223.7
−1162.5
row 3
6
−5023.7
−1162.5
col 19
45
−2153.7
−1162.5
row 4
7
−4953.7
−1162.5
col 20
46
−2083.7
−1162.5
row 5
8
−4883.7
−1162.5
col 21
47
−2013.7
−1162.5
row 6
9
−4813.7
−1162.5
col 22
48
−1943.7
−1162.5
row 7
10
−4743.7
−1162.5
col 23
49
−1873.7
−1162.5
row 8
11
−4673.7
−1162.5
col 24
50
−1803.7
−1162.5
row 9
12
−4603.7
−1162.5
col 25
51
−1663.7
−1162.5
row 10
13
−4533.7
−1162.5
col 26
52
−1593.7
−1162.5
row 11
14
−4463.7
−1162.5
col 27
53
−1523.7
−1162.5
col 28
54
−1453.7
−1162.5
row 12
15
−4393.7
−1162.5
row 13
16
−4323.7
−1162.5
col 29
55
−1383.7
−1162.5
row 14
17
−4253.7
−1162.5
col 30
56
−1313.7
−1162.5
col 31
57
−1243.7
−1162.5
row 15
18
−4183.7
−1162.5
row 16
19
−4113.7
−1162.5
col 32
58
−1173.7
−1162.5
row 17
20
−4043.7
−1162.5
col 33
59
−1103.7
−1162.5
row 18
21
−3973.7
−1162.5
col 34
60
−1033.7
−1162.5
row 19
22
−3903.7
−1162.5
col 35
61
−963.7
−1162.5
row 20
23
−3833.7
−1162.5
col 36
62
−893.7
−1162.5
row 21
24
−3763.7
−1162.5
col 37
63
−823.7
−1162.5
row 22
25
−3693.7
−1162.5
col 38
64
−753.7
−1162.5
col 0
26
−3483.7
−1162.5
col 39
65
−683.7
−1162.5
col 1
27
−3413.7
−1162.5
col 40
66
−613.7
−1162.5
col 2
28
−3343.7
−1162.5
col 41
67
−543.7
−1162.5
col 3
29
−3273.7
−1162.5
col 42
68
−473.7
−1162.5
col 4
30
−3203.7
−1162.5
col 43
69
−403.7
−1162.5
−333.7
−1162.5
col 5
31
−3133.7
−1162.5
col 44
70
col 6
32
−3063.7
−1162.5
col 45
71
−263.7
−1162.5
col 7
33
−2993.7
−1162.5
col 46
72
−193.7
−1162.5
−1162.5
col 8
34
−2923.7
−1162.5
col 47
73
−123.7
col 9
35
−2853.7
−1162.5
col 48
74
−53.7
−1162.5
col 10
36
−2783.7
−1162.5
col 49
75
+16.3
−1162.5
col 11
37
−2713.7
−1162.5
col 50
76
+156.3
−1162.5
col 12
38
−2643.7
−1162.5
col 51
77
+226.3
−1162.5
2000 Dec 07
49
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
COORDINATES(1)
SYMBOL
COORDINATES(1)
SYMBOL
PAD
x
PAD
y
x
y
col 52
78
+296.3
−1162.5
col 91
117
+3096.3
−1162.5
col 53
79
+366.3
−1162.5
col 92
118
+3166.3
−1162.5
col 54
80
+436.3
−1162.5
col 93
119
+3236.3
−1162.5
col 55
81
+506.3
−1162.5
col 94
120
+3306.3
−1162.5
col 56
82
+576.3
−1162.5
col 95
121
+3376.3
−1162.5
col 57
83
+646.3
−1162.5
col 96
122
+3446.3
−1162.5
col 58
84
+716.3
−1162.5
col 97
123
+3516.3
−1162.5
col 59
85
+786.3
−1162.5
col 98
124
+3586.3
−1162.5
col 60
86
+856.3
−1162.5
col 99
125
+3656.3
−1162.5
col 61
87
+926.3
−1162.5
col 100
126
+3726.3
−1162.5
col 62
88
+996.3
−1162.5
row 55
127
+3866.3
−1162.5
col 63
89
+1066.3
−1162.5
row 54
128
+3936.3
−1162.5
col 64
90
+1136.3
−1162.5
row 53
129
+4006.3
−1162.5
col 65
91
+1206.3
−1162.5
row 52
130
+4076.3
−1162.5
col 66
92
+1276.3
−1162.5
row 51
131
+4146.3
−1162.5
col 67
93
+1346.3
−1162.5
row 50
132
+4216.3
−1162.5
col 68
94
+1416.3
−1162.5
row 49
133
+4286.3
−1162.5
col 69
95
+1486.3
−1162.5
row 48
134
+4356.3
−1162.5
col 70
96
+1556.3
−1162.5
row 47
135
+4426.3
−1162.5
col 71
97
+1626.3
−1162.5
row 46
136
+4496.3
−1162.5
col 72
98
+1696.3
−1162.5
row 45
137
+4566.3
−1162.5
col 73
99
+1766.3
−1162.5
row 44
138
+4636.3
−1162.5
col 74
100
+1836.3
−1162.5
row 43
139
+4706.3
−1162.5
col 75
101
+1976.3
−1162.5
row 42
140
+4776.3
−1162.5
col 76
102
+2046.3
−1162.5
row 41
141
+4846.3
−1162.5
col 77
103
+2116.3
−1162.5
row 40
142
+4916.3
−1162.5
col 78
104
+2186.3
−1162.5
row 39
143
+4986.3
−1162.5
col 79
105
+2256.3
−1162.5
row 38
144
+5056.3
−1162.5
col 80
106
+2326.3
−1162.5
row 37
145
+5126.3
−1162.5
col 81
107
+2396.3
−1162.5
row 36
146
+5196.3
−1162.5
col 82
108
+2466.3
−1162.5
row 35
147
+5266.3
−1162.5
col 83
109
+2536.3
−1162.5
row 34
148
+5336.3
−1162.5
col 84
110
+2606.3
−1162.5
dummy
149
+5476.3
−1162.5
col 85
111
+2676.3
−1162.5
dummy
150
+5581.3
+1162.5
col 86
112
+2746.3
−1162.5
row 56
151
+5301.3
+1162.5
col 87
113
+2816.3
−1162.5
row 57
152
+5231.3
+1162.5
col 88
114
+2886.3
−1162.5
row 58
153
+5161.3
+1162.5
col 89
115
+2956.3
−1162.5
row 59
154
+5091.3
+1162.5
col 90
116
+3026.3
−1162.5
row 60
155
+5021.3
+1162.5
2000 Dec 07
50
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
COORDINATES(1)
SYMBOL
COORDINATES(1)
SYMBOL
PAD
x
PAD
y
x
y
row 61
156
+4951.3
+1162.5
SDA_IN
195
+573.3
+1162.5
row 62
157
+4881.3
+1162.5
SDA_IN
196
+493.3
+1162.5
row 63
158
+4811.3
+1162.5
SDA_OUT
197
+65.9
+1162.5
row 64
159
+4741.3
+1162.5
VSS2
198
−233.7
+1162.5
row 65
160
+4671.3
+1162.5
VSS2
199
−313.7
+1162.5
row 66
161
+4601.3
+1162.5
VSS2
200
−393.7
+1162.5
V5
162
+4421
+1162.5
VSS2
201
−473.7
+1162.5
V4
163
+4261
+1162.5
VSS2
202
−553.7
+1162.5
V3
164
+4101
+1162.5
VSS2
203
−633.7
+1162.5
V2
165
+3941
+1162.5
SA0
204
−833.7
+1162.5
VLCDIN
166
+3806.3
+1162.5
T1
205
−1033.7
+1162.5
VLCDIN
167
+3726.3
+1162.5
VSS1
206
−1113.7
+1162.5
VLCDIN
168
+3646.3
+1162.5
VSS1
207
−1193.7
+1162.5
VLCDIN
169
+3566.3
+1162.5
VSS1
208
−1273.7
+1162.5
VLCDIN
170
+3486.3
+1162.5
VSS1
209
−1353.7
+1162.5
VLCDIN
171
+3406.3
+1162.5
VSS1
210
−1433.7
+1162.5
VLCDSENSE
172
+3326.3
+1162.5
VSS1
211
−1513.7
+1162.5
VLCDOUT
173
+3246.3
+1162.5
T3
212
−1713.7
+1162.5
VLCDOUT
174
+3166.3
+1162.5
T4
213
−1913.7
+1162.5
VLCDOUT
175
+3086.3
+1162.5
SA1
214
−2113.7
+1162.5
VLCDOUT
176
+3006.3
+1162.5
SCL
215
−2355
+1162.5
VLCDOUT
177
+2926.3
+1162.5
SCL
216
−2435
+1162.5
VLCDOUT
178
+2846.3
+1162.5
T5
217
−2958
+1162.5
VDD1
179
+2451.3
+1162.5
T6
218
−3158.7
+1162.5
VDD1
180
+2371.3
+1162.5
RES
219
−3454.7
+1162.5
VDD1
181
+2291.3
+1162.5
OSC
220
−4158.7
+1162.5
VDD1
182
+2211.3
+1162.5
T2
221
−4282.7
+1162.5
VDD1
183
+2131.3
+1162.5
row 33
222
−4498.7
+1162.5
VDD1
184
+2051.3
+1162.5
row 32
223
−4568.7
+1162.5
VDD3
185
+1921.3
+1162.5
row 31
224
−4638.7
+1162.5
VDD3
186
+1841.3
+1162.5
row 30
225
−4708.7
+1162.5
VDD3
187
+1761.3
+1162.5
row 29
226
−4778.7
+1162.5
VDD2
188
+1681.3
+1162.5
row 28
227
−4848.7
+1162.5
VDD2
189
+1601.3
+1162.5
row 27
228
−4918.7
+1162.5
VDD2
190
+1521.3
+1162.5
row 26
229
−4988.7
+1162.5
VDD2
191
+1441.3
+1162.5
row 25
230
−5058.7
+1162.5
VDD2
192
+1361.3
+1162.5
row 24
231
−5128.7
+1162.5
VDD2
193
+1281.3
+1162.5
row 23
232
−5198.7
+1162.5
VDD2
194
+1201.3
+1162.5
dummy
233
−5478.7
+1162.5
2000 Dec 07
51
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
Table 11 Bonding pad dimensions
COORDINATES(1)
SYMBOL
PAD
x
NAME
y
dummy
234
−5548.7
+1162.5
dummy
235
−5618.7
+1162.5
−5594.0
−1162.5
Circle 2
+5594.0
−1162.5
Circle 3
+5469.0
+1162.5
Circle 4
−5369.0
+1162.5
Note
1. All x/y coordinates represent the position of the centre
of each pad (in µm) with respect to the centre (x/y = 0)
of the chip (see Fig.32).
2000 Dec 07
DIMENSION
Pad pitch
70 µm (minimum value)
Pad size, aluminium
62 × 100 µm
Passivation opening at pad 36 × 76 µm
Alignment marks
Circle 1
PCF8820
52
Bump dimensions
52 × 90 × 17.5 µm
Wafer thickness
(excluding bumps)
381 µm
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
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row 56
circle 3 (1)
pad 150
V5
row 66
V3
V4
V2
VLCDIN
VLCDSENSE
VLCDOUT
VDD1
VDD3
VDD2
SDA_IN
SDA_OUT
VSS2
T1
SA0
VSS1
SCL
SA1
T4
T3
T6
T5
RES
T2
OSC
row 33
circle 4 (1)
row 23
pad 235
y
row 34
pad149
11.46 mm
circle 2 (1)
col 100
row 55
col 75
col 50
col 25
.
..
.
..
row 22
col 0
x
.
..
.
..
.
..
.
..
pad 1
row 0
0, 0
circle 1 (1)
53
2.59
mm
Philips Semiconductors
.
..
...
...
.
..
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
handbook, full pagewidth
2000 Dec 07
PC8820-1
MGT139
Product specification
Fig.32 Bonding pad locations.
PCF8820
(1) Circles 1 to 4 are alignment marks with a diameter of 100 µm.
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
15 DEVICE PROTECTION CIRCUITS
SYMBOL
VDD1
PAD
179 to 184
REMARK
INTERNAL CIRCUIT
note 1
VSS1
MGU179
VDD2
188 to 194
note 1
VSS1
VSS2
MGU180
VDD3
185 to 187
note 1
VSS1
MGU179
VSS1
206 to 211
note 1
VSS2
198 to 203
note 1
VSS1
VSS2
MGU181
VLCDIN
166 to 171
VLCDSENSE
172
VLCDOUT
173 to 178
note 1
note 1
VSS1
MGU179
V2
162
V3
163
V4
164
V5
165
VLCDIN
VSS1
MGU182
2000 Dec 07
54
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
SYMBOL
PAD
SA0
204
SA1
214
T1
205
T2
221
T3
212
T4
213
T5
217
T6
218
REMARK
PCF8820
INTERNAL CIRCUIT
VDD1
VSS1
MGU183
OSC
220
RES
219
SCL
215 and 216
note 1
SDA_IN
195 and 196
note 1
SDA_OUT
197
VSS1
MGU179
R0 to R22 (block 1)
3 to 25
R23 to R33 (block 2)
232 to 222
R34 to R55 (block 3)
148 to 127
R56 to R66 (block 4)
151 to 161
C0 to C24 (block 5)
26 to 50
C25 to C49 (block 6)
51 to 75
C50 to C74 (block 7)
76 to 100
C75 to C100 (block 8)
101 to 126
VLCDIN
1 diode per block
VSS1
MGU184
Note
1. Internally shorted via metal.
2000 Dec 07
55
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
16 TRAY INFORMATION
x
handbook, full pagewidth
A
C
y
D
B
F
E
MGT141
For the dimensions of A to F: see Table 12.
Fig.33 Tray details.
Table 12 Tray dimensions
DIMENSION
handbook, halfpage
PC8820-1
MGT142
The orientation of the IC in a pocket is indicated by the position of the
IC type name on the die surface with respect to the chamfer on the
upper left corner of the tray. Refer to Fig.32 for the orientation and
position of the type name on the die surface.
Fig.34 Tray alignment.
2000 Dec 07
56
DESCRIPTION
VALUE
A
pocket pitch in x direction
13.77 mm
B
pocket pitch in y direction
4.45 mm
C
pocket width in x direction
11.61 mm
D
pocket width in y direction
2.75 mm
E
tray width in x direction
50.8 mm
F
tray width in y direction
50.8 mm
−
no. pockets in x direction
3
−
no. pockets in y direction
10
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
17 DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
18 DEFINITIONS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
20 BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all
data sheet limits up to the point of wafer sawing for a
period of ninety (90) days from the date of Philips' delivery.
If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There are no post
packing tests performed on individual die or wafer. Philips
Semiconductors has no control of third party procedures in
the sawing, handling, packing or assembly of the die.
Accordingly, Philips Semiconductors assumes no liability
for device functionality or performance of the die or
systems after third party sawing, handling, packing or
assembly of the die. It is the responsibility of the customer
to test and qualify their application in which the die is used.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
19 DISCLAIMERS
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
2000 Dec 07
57
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 Dec 07
58
Philips Semiconductors
Product specification
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
NOTES
2000 Dec 07
59
PCF8820
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For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 70
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403512/01/pp60
Date of release: 2000
Dec 07
Document order number:
9397 750 06586