PHILIPS PCF8576C

PCF8576C
Universal LCD driver for low multiplex rates
Rev. 09 — 9 July 2009
Product data sheet
1. General description
The PCF8576C is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments and can easily
be cascaded for larger LCD applications. The PCF8576C is compatible with most
microprocessors or microcontrollers and communicates via a two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremented addressing, by hardware subaddressing.
2. Features
n Single-chip LCD controller and driver
n 40 segment drives:
u Up to twenty 7-segment numeric characters
u Up to ten 14-segment alphanumeric characters
u Any graphics of up to 160 elements
n Versatile blinking modes
n No external components required (even in multiple device applications)
n Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
n Selectable display bias configuration: static, 1⁄2 or 1⁄3
n Internal LCD bias generation with voltage-follower buffers
n 40 × 4-bit RAM for display data storage
n Auto-incremented display data loading across device subaddress boundaries
n Display memory bank switching in static and duplex drive modes
n Wide logic LCD supply range:
u From 2 V for low-threshold LCDs
u Up to 6 V for guest-host LCDs and high-threshold twisted nematic LCDs
n Low power consumption
n May be cascaded for large LCD applications (up to 2560 segments possible)
n Cascadable with 24-segment LCD driver PCF8566
n No external components
n Compatible with chip-on-glass technology
n Separate or combined LCD and logic supplies
n Optimized pinning for plane wiring in both and multiple PCF8576C applications
n Power-saving mode for extremely low power consumption in battery-operated and
telephone applications
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCF8576CH
LQFP64
plastic low profile quad flat package;
64 leads; body 10 × 10 × 1.4 mm
SOT314-2
PCF8576CT
VSO56
plastic very small outline package, 56 leads
SOT190-1
PCF8576CTT
HTSSOP56
plastic thermal enhanced thin shrink small outline package, 56 leads; SOT793-1
body width 6.1 mm; exposed die pad
PCF8576CU/10 PCF8576CU/10 wire bond die; 56 bonding pads; 3.0 × 2.82 × 0.38 mm[1]
PCF8576CU
PCF8576CU/2
PCF8576CU/10
PCF8576CU
wire bond die; 56 bonding pads; 3.0 × 2.82 × 0.38 mm[2]
PCF8576CU
PCF8576CU/2
bare die; 56 bumps; 3.0 × 2.82 × 0.40
PCF8576CU/2
[1]
Delivery form: chip on FFC.
[2]
Delivery form: chip in tray.
mm[2]
4. Marking
Table 2.
Marking codes
Type number
Marking code
PCF8576CH
PCF8576CH
PCF8576CT
PCF8576CT
PCF8576CTT
PCF8576CTT
PCF8576CU/10
PC8576C-1
PCF8576CU
PC8576C-1
PCF8576CU/2
PC8576C-2
PCF8576C_9
Product data sheet
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Rev. 09 — 9 July 2009
2 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
5. Block diagram
BP0 BP2 BP1 BP3
S0 to S39
40
VDD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY LATCH
LCD BIAS
GENERATOR
VLCD
SHIFT REGISTER
PCF8576C
CLK
TIMING
INPUT
BANK
SELECTOR
BLINKER
SYNC
DISPLAY
RAM
40 × 4 BITS
OUTPUT
BANK
SELECTOR
DISPLAY
CONTROLLER
OSC
OSCILLATOR
POWERON
RESET
COMMAND
DECODER
VSS
SCL
SDA
DATA
POINTER
INPUT
FILTERS
SUBADDRESS
COUNTER
I2C-BUS
CONTROLLER
SA0
A0
A1
A2
013aaa094
Fig 1.
Block diagram of PCF8576C
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
3 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
6. Pinning information
49 S18
50 S19
51 S20
52 S21
53 S22
54 S23
55 S24
56 S25
57 S26
58 S27
59 S28
60 S29
61 S30
62 S31
63 S32
64 S33
6.1 Pinning
n.c.
1
48 n.c.
S34
2
47 S17
S35
3
46 S16
S36
4
45 S15
S37
5
44 S14
S38
6
43 S13
S39
7
42 S12
n.c.
8
n.c.
9
41 S11
PCF8576CH
40 S10
SDA 10
39 S9
SCL 11
38 S8
SYNC 12
37 S7
13
36 S6
VDD 14
35 S5
OSC 15
34 S4
CLK
A0 16
S3 32
S2 31
S1 30
S0 29
BP3 28
BP1 27
BP2 26
BP0 25
n.c. 24
n.c. 23
n.c. 22
VLCD 21
VSS 20
SA0 19
A2 18
A1 17
33 n.c.
001aag241
Top view. For mechanical details, see Figure 32.
Fig 2.
Pin configuration of PCF8576CH (LQFP64)
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
4 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
SDA
1
56 S39
SCL
2
55 S38
SYNC
3
54 S37
CLK
4
53 S36
VDD
5
52 S35
OSC
6
51 S34
A0
7
50 S33
A1
8
49 S32
A2
9
48 S31
SA0 10
47 S30
VSS 11
46 S29
VLCD 12
45 S28
BP0 13
44 S27
BP2 14
BP1 15
43 S26
PCF8576CT
42 S25
BP3 16
41 S24
S0 17
40 S23
S1 18
39 S22
S2 19
38 S21
S3 20
37 S20
S4 21
36 S19
S5 22
35 S18
S6 23
34 S17
S7 24
33 S16
S8 25
32 S15
S9 26
31 S14
S10 27
30 S13
S11 28
29 S12
001aag240
Top view. For mechanical details, see Figure 33.
Fig 3.
Pin configuration of PCF8576CT (VSO56)
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
5 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
SDA
1
56 S39
SCL
2
55 S38
SYNC
3
54 S37
CLK
4
53 S36
VDD
5
52 S35
OSC
6
51 S34
A0
7
50 S33
A1
8
49 S32
A2
9
48 S31
SA0 10
47 S30
VSS 11
46 S29
VLCD 12
45 S28
BP0 13
44 S27
BP2 14
BP1 15
43 S26
PCF8576CTT
42 S25
BP3 16
41 S24
S0 17
40 S23
S1 18
39 S22
S2 19
38 S21
S3 20
37 S20
S4 21
36 S19
S5 22
35 S18
S6 23
34 S17
S7 24
33 S16
S8 25
32 S15
S9 26
31 S14
S10 27
30 S13
S11 28
29 S12
013aaa095
Top view. For mechanical details, see Figure 34.
Fig 4.
Pin configuration of PCF8576CTT (HTSSOP56)
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
6 of 56
PCF8576C
NXP Semiconductors
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
Universal LCD driver for low multiplex rates
34
33
32
31
30
29
28
27
26
25
24
23
22
21
S18
35
20 S3
S19
36
19 S2
S20
37
18 S1
S21
38
17 S0
S22
39
16 BP3
S23
40
15 BP1
S24
41
S25
42
S26
43
S27
44
S28
45
S29
46
S30
47
11 VSS
S31
48
10 SA0
S32
49
9
A2
S33
50
8
A1
14 BP2
PCF8576CU
13 BP0
51
52
53
54
55
56
1
2
3
4
5
6
7
S34
S35
S36
S37
S38
S39
SDA
SCL
SYNC
CLK
VDD
OSC
A0
12 VLCD
013aaa096
Top view. For mechanical details, see Figure 35, Figure 36 and Figure 37.
Fig 5.
Pin locations of PCF8576CU
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
7 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
PCF8576CH
PCF8576CT
PCF8576CTT
PCF8576CU
SDA
10
1
1
I2C-bus serial data input and output
SCL
11
2
2
I2C-bus serial clock input
SYNC
12
3
3
cascade synchronization input and output
CLK
13
4
4
external clock input/output
supply voltage
VDD
14
5
5[1]
OSC
15
6
6
internal oscillator enable input
A0 to A2
16 to 18
7 to 9
7 to 9
subaddress inputs
SA0
19
10
10
I2C-bus address input; bit 0
VSS
20
11
11
logic ground
VLCD
21
12
12
LCD supply voltage
BP0, BP2,
BP1, BP3
25 to 28
13 to 16
13 to 16
LCD backplane outputs
S0 to S39
2 to 7, 29 to 32,
34 to 47, 49 to 64
17 to 56
17 to 56
LCD segment outputs
n.c.
1, 8, 9, 22 to 24, 33, 48 -
-
not connected
[1]
The substrate (rear side of the die) is wired to VDD but should not be electrically connected.
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
8 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
7. Functional description
The PCF8576C is a versatile peripheral device designed to interface any
microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static
or multiplexed LCD containing up to 4 backplanes and up to 40 segments.
The display configurations possible with the PCF8576C depend on the number of active
backplane outputs required. Display configuration selection is shown in Table 4. All of the
display configurations given in Table 4 can be implemented in the typical system shown in
Figure 6.
Table 4.
Display configurations
Number of:
7 segment numeric
14-segment numeric
Backplanes Elements
Digits
Indicator
symbols
Characters
Indicator
symbols
4
160
20
20
10
20
160 (4 × 40)
3
120
15
15
8
8
120 (3 × 40)
2
80
10
10
5
10
80 (2 × 40)
1
40
5
5
2
12
40 (1 × 40)
VDD
R≤
tr
2CB
V
DD
V
LCD
SDA
HOST
MICROPROCESSOR/
MICROCONTROLLER
40 segment drives
SCL
PCF8576C
OSC
4 backplanes
A0
A1
A2
Dot matrix
SA0 V
SS
LCD PANEL
(up to 160
elements)
013aaa098
VSS
Fig 6.
Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCF8576C.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application.
7.1 Power-on-reset
At power-on the PCF8576C resets to the following starting conditions:
•
•
•
•
All backplane and segment outputs are set to VDD
The selected drive mode is 1:4 multiplex with 1⁄3 bias
Blinking is switched off
Input and output bank selectors are reset (as defined in Table 8)
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
9 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the
reset action to complete.
7.2 LCD bias generator
The full-scale LCD voltage (Voper) is obtained from VDD − VLCD. The LCD voltage may be
temperature compensated externally through the VLCD supply to pin VLCD.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between VDD and VLCD. The center resistor can be
switched out of the circuit to provide a 1⁄2 bias voltage level for the 1:2 multiplex
configuration.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D), are given in Table 5.
Table 5.
Preferred LCD drive modes: summary of characteristics
LCD drive
mode
Number of:
LCD bias
V on ( RMS )
V off ( RMS ) V on ( RMS )
-------------------------- ------------------------- D = -------------------------V LCD
V off ( RMS )
Backplanes Bias levels configuration
V LCD
static
1
2
static
0
1
∞
1:2 multiplex 2
3
1⁄
2
0.354
0.791
2.236
1:2 multiplex 2
4
1⁄
3
0.333
0.745
2.236
4
1⁄
3
0.333
0.638
1.915
4
1⁄
3
0.333
0.577
1.732
1:3 multiplex 3
1:4 multiplex 4
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD < 3 × Vth.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1
V on ( RMS ) =
V LCD
1 (n – 1)  1  2
--- + ----------------- × ------------ 1 + a
n
n
(1)
where VLCD is the resultant voltage at the LCD segment and where the values for n are
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
10 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 3 for 1:3 multiplex
n = 4 for 1:4 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
V off ( RMS ) =
V LCD
a 2 – 2a + n
-----------------------------2n × (1 + a)
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
V on ( RMS )
D = ----------------------- =
V off ( RMS )
2
(a + 1) + (n – 1)
------------------------------------------2
(a – 1) + (n – 1)
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2 bias
is
1⁄
2 bias
21
is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD = 6 × V off ( RMS ) = 2.449V off ( RMS )
4 × 3)
• 1:4 multiplex (1⁄2 bias): V LCD = (--------------------- = 2.309V off ( RMS )
3
These compare with V LCD = 3V off ( RMS ) when 1⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
11 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 7.
Tfr
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
−VLCD
VLCD
state 2
0V
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl745
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = VSn+1(t) − VBP0(t).
Voff(RMS) = 0 V.
Fig 7.
Static drive mode waveforms
PCF8576C_9
Product data sheet
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Rev. 09 — 9 July 2009
12 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8576C allows the use of 1⁄2 bias or 1⁄3 bias (see Figure 8 and Figure 9).
Tfr
VLCD
BP0
LCD segments
VLCD / 2
VSS
state 1
VLCD
BP1
state 2
VLCD / 2
VSS
VLCD
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
VLCD / 2
state 1
0V
−VLCD / 2
−VLCD
VLCD
VLCD / 2
state 2
0V
−VLCD / 2
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl746
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.354VLCD
Fig 8.
Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
13 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
Sn+1
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl747
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.745VLCD
Vstate2(t) = VSn(t) − VBP1(t)
Voff(RMS) = 0.333VLCD.
Fig 9.
Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
14 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as
shown in Figure 10.
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
BP2
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+1
Sn+2
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl748
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
15 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.4 1:4 multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 11.
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP3
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+1
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+3
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl749
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 11. Waveforms for the 1:4 multiplex mode with 1⁄3 bias
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
16 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8576C are timed by the frequency
fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency
fclk(ext).
The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate
for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data
rate of 100 kHz, fclk should be chosen to be above 125 kHz.
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the
output from pin CLK is the clock signal for any cascaded PCF8576s or PCF8566s in the
system.
Remark: The PCF8576C is backwards compatible with the PCF8576 (Voper up to 9 V).
Where resistor Rext (on pin OSC) to VSS is present, the internal oscillator is selected.
7.5.2 External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device. Removing the clock,
freezes the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The timing of the PCF8576C sequences the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF8576Cs in the system. The timing also generates the LCD
frame frequency which is derived as an integer division of the clock frequency (see
Table 6). The frame frequency is set by the mode set commands when an internal clock is
used or by the frequency applied to the pin CLK when an external clock is used.
Table 6.
LCD frame frequencies [1]
PCF8576C mode
Frame frequency
Nominal frame frequency (Hz)
Normal mode
f clk
f fr = -----------2880
69 [2]
Power saving mode
f clk
f fr = --------480
65 [3]
[1]
The possible values for fclk see Table 20.
[2]
For fclk = 200 kHz.
[3]
For fclk = 31 kHz.
The ratio between the clock frequency and the LCD frame frequency depends on the
mode in which the device is operating. In the power-saving mode the reduction ratio is six
times smaller; this allows the clock frequency to be reduced by a factor of six. The
reduced clock frequency results in a significant reduction in power consumption.
PCF8576C_9
Product data sheet
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PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
The lower clock frequency has the disadvantage of increasing the response time when
large amounts of display data are transmitted on the I2C-bus. When a device is unable to
process a display data byte before the next one arrives, it holds the SCL line LOW until the
first display data byte is stored. This slows down the transmission rate of the I2C-bus but
no data loss occurs.
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and one column of the display RAM.
7.8 Shift register
The shift register transfers display information from the display RAM to the display register
while previous data is displayed.
7.9 Segment outputs
The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data residing in the display register. When less than
40 segment outputs are required, the unused segment outputs should be left open-circuit.
7.10 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left as an
open-circuit.
• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
• In static drive mode: the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.11 Display RAM
The display RAM is a static 40 × 4-bit RAM which stores LCD data. A logic 1 in the RAM
bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0
indicates the off-state. There is a direct relationship between the RAM addresses and the
segment outputs, and between the individual bits of a RAM word and the backplane
outputs. The display RAM bit map Figure 12 shows the rows 0 to 3 which correspond with
the backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2
and BP3 respectively.
PCF8576C_9
Product data sheet
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PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
display RAM addresses (columns)/segment outputs (S)
0
1
2
3
4
35
36
37
38
39
0
display RAM bits
1
(rows)/
backplane outputs
2
(BP)
3
mbe525
Display RAM bit map showing direct relationship between RAM addresses and segment outputs;
also between bits in a RAM word and the backplane outputs.
Fig 12. Display RAM bit map
When display data is transmitted to the PCF8576C, the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for an acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triplets or
quadruplets. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 13; the RAM filling organization depicted
applies equally to other LCD types.
The following applies to Figure 13:
• In the static drive mode, the eight transmitted data bits are placed in row 0 of eight
successive 4-bit RAM words.
• In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into
row 0 and 1 of four successive 4-bit RAM words.
• In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to
three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
• In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into
row 0, 1, 2 and 3 of two successive 4-bit RAM words.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
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LCD segments
LCD backplanes
display RAM filling order
NXP Semiconductors
PCF8576C_9
Product data sheet
drive mode
transmitted display byte
display RAM addresses (columns)/segment outputs (S)
byte1
Sn+2
Sn+3
static
a
b
f
Sn+4
Sn+5
Sn+1
BP0
display RAM
bits (rows)/
backplane
outputs (BP)
g
e
Sn+6
Sn
Sn+7
c
DP
d
0
1
2
3
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
Sn
Sn+1
b
f
g
BP1
e
c
display RAM
bits (rows)/
backplane
outputs (BP)
DP
d
Sn+1
Sn+2
f
g e d DP
b
f
multiplex
BP1
c
BP2
display RAM
bits (rows)/
backplane
outputs (BP)
DP
d
n+1
n+2
n+3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
n
Sn
g
e
n
MSB
a b
LSB
f
g e c d DP
display RAM addresses (columns)/segment outputs (S)
byte1
byte2
byte3
BP0
a
0
1
2
3
0 b
1 DP
2 c
3 x
n+1
n+2
a
d
g
x
f
e
x
x
MSB
LSB
b DP c a d g
f
e
display RAM addresses (columns)/segment outputs (S)
byte1
byte2
byte3
byte4
byte5
a
Sn
1:4
b
f
BP0
g
multiplex
20 of 56
© NXP B.V. 2009. All rights reserved.
Sn+1
BP1
c
d
DP
BP3
display RAM
bits (rows)/
backplane
outputs (BP)
0 a
1 c
2 b
3 DP
n+1
f
e
g
d
MSB
a c b DP f
LSB
e g d
001aaj646
x = data bit unchanged.
Fig 13. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
PCF8576C
e
n
BP2
Universal LCD driver for low multiplex rates
Rev. 09 — 9 July 2009
Sn+3
1:3
c b a
a
multiplex
Sn+2
LSB
display RAM addresses (columns)/segment outputs (S)
byte1
byte2
BP0
1:2
MSB
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.12 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load data pointer command (see Table 13). After this, the data byte is
stored starting at the display RAM address indicated by the data pointer (see Figure 13).
Once each byte is stored, the data pointer is automatically incremented based on the
selected LCD configuration.
The contents of the data pointer are incremented as follows:
•
•
•
•
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early, the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten prior to further RAM accesses.
7.13 Sub-address counter
The storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed to take place only when the contents of the subaddress counter match
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is
defined by the device select command (see Table 14). If the contents of the subaddress
counter and the hardware subaddress do not match then data storage is blocked but the
data pointer will be incremented as if data storage had taken place. The subaddress
counter is also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8576C occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 14th
display data byte transmitted in 1:3 multiplex mode).
7.14 Bank selector
7.14.1 Output bank selector
The output bank selector (see Table 15), selects one of the four bits per display RAM
address for transfer to the display register. The actual bit selected depends on the LCD
drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially
by the contents of bit 1, bit 2 and then bit 3.
• In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially.
• In 1:2 multiplex mode: bits 0 and 1 are selected.
• In the static mode: bit 0 is selected.
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PCF8576C
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Universal LCD driver for low multiplex rates
The PCF8576C includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank select command may request the contents
of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 multiplex drive
mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This enables
preparation of display information in an alternative bank and the ability to switch to it once
it has been assembled.
7.14.2 Input bank selector
The input bank selector (see Table 15) loads display data into the display RAM based on
the selected LCD drive configuration. Using the bank select command, display data can
be loaded in bit 2 into static drive mode or in bits 2 and 3 into 1:2 multiplex drive mode.
The input bank selector functions independently of the output bank selector.
7.15 Blinker
The display blinking capabilities of the PCF8576C are very versatile. The whole display
can be blinked at frequencies selected by the blink command. The blinking frequencies
are integer fractions of the clock frequency; the ratios between the clock and blinking
frequencies depend on the mode in which the device is operating (see Table 7).
Table 7.
Blink frequencies
Blinking mode
Normal operating
mode ratio
Power saving mode
ratio
Blink frequency
off
-
-
blinking off
1
f clk
f blink = --------------92160
f clk
f blink = --------------15360
2 Hz
2
f clk
f blink = ------------------184320
f clk
f blink = --------------30720
1 Hz
3
f clk
f blink = ------------------368640
f clk
f blink = --------------61440
0.5 Hz
An additional feature is for an arbitrary selection of LCD segments to be blinked. This
applies to the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. Using the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blinking frequency. This mode can also be
specified by the blink command (see Table 16).
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at fixed time
intervals.
If the entire display needs to be blinked at a frequency other than the nominal blink
frequency, this can be done using the mode set command to set and reset the display
enable bit E at the required rate (see Table 9).
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PCF8576C
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Universal LCD driver for low multiplex rates
8. Basic architecture
8.1 Characteristics of the I2C-bus
The I2C-bus provides bidirectional, two-line communication between different IC or
modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When
connected to the output stages of a device, both lines must be connected to a positive
supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line at this time will
be interpreted as a control signal. Bit transfer is illustrated in Figure 14.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 14. Bit transfer
8.1.1.1
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 15.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc622
Fig 15. Definition of START and STOP conditions
8.1.2 System configuration
A device generating a message is a transmitter and a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is illustrated in
Figure 16.
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PCF8576C
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Universal LCD driver for low multiplex rates
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Fig 16. System configuration
8.1.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse.
Acknowledgement on the I2C-bus is illustrated in Figure 17.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end-of-data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
master receiver must leave the data line HIGH during the 9th pulse to not
acknowledge. The master will now generate a STOP condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
mbc602
Fig 17. Acknowledgement on the I2C-bus
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PCF8576C
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Universal LCD driver for low multiplex rates
8.1.4 PCF8576C I2C-bus controller
The PCF8576C acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8576C are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, the transferred command data and the hardware subaddress.
In single device application, the hardware subaddress inputs A0, A1 and A2 are normally
tied to VSS which defines the hardware subaddress 0. In multiple device applications
A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two
devices with a common I2C-bus slave address have the same hardware subaddress.
In the power-saving mode it is possible that the PCF8576C is not able to keep up with the
highest transmission rates when large amounts of display data are transmitted. If this
situation occurs, the PCF8576C forces the SCL line LOW until its internal operations are
completed. This is known as the clock synchronization feature of the I2C-bus and serves
to slow down fast transmitters. Data loss does not occur.
8.1.5 Input filter
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.2 I2C-bus protocol
Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576C.
The least significant bit of the slave address that a PCF8576C responds to is defined by
the level tied at its input SA0. Therefore, two types of PCF8576C can be distinguished on
the same I2C-bus which allows:
• Up to 16 PCF8576Cs on the same I2C-bus for very large LCD applications.
• The use of two types of LCD multiplex on the same I2C-bus.
The I2C-bus protocol is shown in Figure 18. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the two PCF8576C
slave addresses available. All PCF8576Cs with the corresponding SA0 level acknowledge
in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore
the whole I2C-bus transfer.
After acknowledgement, one or more command bytes (m) follow which define the status of
the addressed PCF8576Cs.
The last command byte is tagged with a cleared most significant bit, the continuation bit C.
The command bytes are also acknowledged by all addressed PCF8576Cs on the bus.
After the last command byte, a series of display data bytes (n) may follow. These display
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data is directed to the intended PCF8576C device. The acknowledgement after
each byte is made only by the (A0, A1 and A2) addressed PCF8576C. After the last
display byte, the I2C-bus master issues a STOP condition (P).
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PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
acknowledge
by A0, A1 and A2
selected
PCF8576C only
acknowledge by
all addressed
PCF8576Cs
R/W
slave address
S
S
0 1 1 1 0 0 A 0 A C
0
COMMAND
A
n ≥ 1 byte(s)
1 byte
DISPLAY DATA
A
P
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
mbe538
Fig 18. I2C-bus protocol
8.3 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. All available
commands carry a continuation bit C in their most significant bit position as shown in
Figure 19. When this bit is set, it indicates that the next byte of the transfer to arrive will
also represent a command. If this bit is reset, it indicates that the command byte is the last
in the transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8576C are defined in Table 8.
MSB
LSB
C
REST OF OPCODE
msa833
(1) C = 0; last command
(2) C = 1; commands continue
Fig 19. General format of byte command
Table 8.
Command
Definition of PCF8576C commands
OPCODE
Reference
Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
mode set
C
1
0
LP
E
B
M1
M0
Section 8.3.1 defines LCD drive mode, LCD bias
configuration, display status and power
dissipation mode
load data
pointer
C
0
P5
P4
P3
P2
P1
P0
Section 8.3.2 data pointer to define one of 40 display
RAM addresses
device select C
1
1
0
0
A2
A1
A0
Section 8.3.3 define one of eight hardware
subaddresses
bank select
C
1
1
1
1
0
I
O
Section 8.3.4 bit I: defines input bank selection
(storage of arriving display data);
bit O: defines output bank selection
(retrieval of LCD display data)
blink
C
1
1
1
0
A
BF1
BF0
Section 8.3.5 defines the blink frequency and blink
mode
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PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
8.3.1 Mode set command
Table 9.
LCD drive mode command bit description
LCD drive mode
Drive mode
Bit
Backplane
M1
M0
static
BP0
0
1
1:2
BP0, BP1
1
0
1:3
BP0, BP1, BP2
1
1
1:4
BP0, BP1, BP2, BP3
0
0
Table 10.
LCD bias configuration command bit description
LCD bias
Bit B
1⁄
3
bias
0
1⁄
2
bias
1
Table 11.
Display status command bit description[1]
Display status
Bit E
disabled (blank)
0
enabled
1
[1]
The possibility to disable the display allows implementation of blinking under external control.
Table 12.
Power dissipation mode command bit description
Display status
Bit LP
normal mode
0
power saving mode
1
8.3.2 Load data pointer command
Table 13.
Load data pointer command bit description
Description
Bits
6 bit binary value, 0 to 39
P5
P4
P3
P2
P1
P0
8.3.3 Device select command
Table 14.
Device select command bit description
Description
Bits
3 bit binary value, 0 to 7
A2
PCF8576C_9
Product data sheet
A1
A0
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PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
8.3.4 Bank select command
Table 15.
Bank select command[1]
Bank
Mode
Static
1:2 multiplex drive mode
RAM bit 0
RAM bits 0 and 1
RAM bit 2
RAM bits 2 and 3
RAM bit 0
RAM bits 0 and 1
RAM bit 2
RAM bits 2 and 3
Bit
Value
I
0
Input bank
1
Output bank
[1]
O
0
1
The bank select command has no effect in 1:3 or 1:4 multiplex drive modes.
8.3.5 Blink command
Table 16.
Blink frequency command bit description
Blink frequency
Bit
BF1
BF0
off
0
0
1
0
1
2
1
0
3
1
1
Table 17.
Blink mode command bit description
Blink mode
Bit A
normal blinking
0
alternate RAM bank blinking
1
8.4 Display controller
The display controller executes the commands identified by the command decoder. It
contains the status registers of the PCF8576C and coordinates their effects. The
controller is also responsible for loading display data into the display RAM as required by
the filling order.
9. Internal circuitry
VLCD
VSS
SDA, SCL
BP0 to BP3,
S0 to S39
CLK, OSC, A0 to A2,
SA0, SYNC
VDD
013aaa109
Fig 20. Device protection diagram
PCF8576C_9
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Rev. 09 — 9 July 2009
28 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
10. Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDD
supply voltage
VLCD
LCD supply voltage
VI
input voltage
on each of the pins SCL, SDA,
CLK, SYNC, SA0, OSC and
A0 to A2
VO
output voltage
on each of the pins
S0 to S39 and BP0 to BP3
II
Max
−0.5
8.0
Unit
V
VDD − 8.0 VDD
V
−0.5
8.0
V
−0.5
8.0
V
input current
−20
+20
mA
IO
output current
−25
+25
mA
IDD
supply current
−50
+50
mA
ISS
ground supply current
−50
+50
mA
IDD(LCD)
LCD supply current
−50
+50
mA
Ptot
total power dissipation
-
400
mW
Po
output power
-
100
mW
Tstg
storage temperature
[2]
−65
+150
°C
electrostatic discharge
voltage
HBM
[3]
-
±4000
V
MM
[4]
-
±200
V
[5]
-
100
mA
VESD
Ilu
[1]
latch-up current
[1]
[1]
Values with respect to VDD.
[2]
According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be
stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.
[3]
Pass level; Human Body Model (HBM) according to JESD22-A114.
[4]
Pass level; Machine Model (MM), according to JESD22-A115.
[5]
Pass level; latch-up testing, according to JESD78.
PCF8576C_9
Product data sheet
Min
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
29 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
11. Static characteristics
Table 19. Static characteristics
VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
Supplies
VDD
supply voltage
VLCD
LCD supply voltage
2.0
-
6.0
[1]
VDD − 6.0
-
VDD − 2.0 V
IDD
supply current:
fclk = 200 kHz
[2]
-
-
120
µA
IDD(lp)
low-power mode supply
current
VDD = 3.5 V; VLCD = 0 V; fclk = 35 kHz;
A0, A1 and A2 connected to VSS
-
-
60
µA
VIL
LOW-level input voltage
on pins CLK, SYNC, OSC,
A0 to A2 and SA0
VSS
-
0.3VDD
V
VIH
HIGH-level input voltage
on pins CLK, SYNC, OSC,
A0 to A2 and SA0
0.7VDD
-
VDD
V
VOL
LOW-level output voltage
IOL = 0 mA
-
-
0.05
V
VOH
HIGH-level output voltage
IOH = 0 mA
VDD − 0.05 -
-
V
IOL
LOW-level output current
VOL = 1.0 V; VDD = 5.0 V;
on pins CLK and SYNC
1
-
-
mA
IL
leakage current
VI = VDD or VSS; on pins
CLK, SCL, SDA, A0 to A2 and SA0
−1
-
+1
µA
IL(OSC)
leakage current on pin OSC
VI = VDD
−1
-
+1
µA
Ipd
pull-down current
VI = 1.0 V; VDD = 5.0 V;
on pins A0 to A2 and OSC
15
50
150
µA
RSYNC_N
SYNC resistance
150
kΩ
Logic
VPOR
power-on reset voltage
[3]
CI
input capacitance
[4]
20
50
-
1.0
1.6
V
-
-
7
pF
VSS
-
0.3VDD
V
I2C-bus; pins SDA and SCL
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDD
-
6.0
V
IOH(CLK)
HIGH-level output current on
pin CLK
VOH = 4.0 V; VDD = 5.0 V
−1
-
-
mA
IOL(SDA)
LOW-level output current on
pin SDA
VOL = 0.4 V; VDD = 5.0 V
3
-
-
mA
−20
-
+20
mV
LCD outputs
VBP
voltage on pin BP
Cbpl = 35 nF; on pins BP0 to BP3
VS
voltage on pin S
Csgm = 5 nF; on pins S0 to S39
RBP
resistance on pin BP
RS
resistance on pin S
−20
-
+20
mV
VLCD = VDD − 5 V; on pins BP0 to BP3
[5]
-
-
5
kΩ
VLCD = VDD − 5 V; on pins S0 to S39
[5]
-
-
7.5
kΩ
[1]
VLCD ≤ VDD − 3 V for 1⁄3 bias.
[2]
LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[3]
Resets all logic when VDD < VPOR.
[4]
Periodically sampled, not 100 % tested.
[5]
Outputs measured one at a time.
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
30 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
11.1 Typical supply current characteristics
mbe530
50
mbe529
50
−IDD(LCD)
(µA)
ISS
(µA)
normal
mode
40
40
30
30
20
20
power-saving
mode
10
10
0
0
0
100
200
0
100
ffr (Hz)
200
ffr (Hz)
VDD = 5 V; VLCD = 0 V; Tamb = 25 °C
VDD = 5 V; VLCD = 0 V; Tamb = 25 °C
Fig 22. −IDD(LCD) as a function of ffr
Fig 21. ISS as a function of ffr
mbe528
50
mbe527
50
−IDD(LCD)
(µA)
ISS
(µA)
40
40
normal mode
fclk = 200 kHz
85 °C
30
30
20
20
−40 °C
power-saving mode
fclk = 35 kHz
10
25 °C
10
0
0
0
5
VDD (V)
0
10
VLCD = 0 V; external clock; Tamb = 25 °C
Fig 23. ISS as a function of VDD
VDD (V)
10
VLCD = 0 V; external clock; Tamb = 25 °C
Fig 24. −IDD(LCD) as a function of VDD
PCF8576C_9
Product data sheet
5
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
31 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
11.2 Typical LCD output characteristics
mbe532
10
RO(max)
(kΩ)
mbe526
2.5
RO(max)
(kΩ)
RS
2.0
RS
1.5
RBP
1
RBP
1.0
0.5
10−1
0
3
VDD (V)
6
0
−40
VLCD = 0 V; Tamb = 25 °C
Fig 25. RO(max) as a function of VDD
40
80
120
Tamb (°C)
VDD = 5 V; VLCD = 0 V
Fig 26. RO(max) as a function of Tamb
PCF8576C_9
Product data sheet
0
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
32 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
Table 20. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
normal mode; VDD = 5 V 125
200
315
kHz
31
48
kHz
Timing characteristics: driver timing waveforms (see Figure 27)
[1]
clock frequency
fclk
21
power saving mode;
VDD = 3 V
tclk(H)
clock HIGH time
1
-
-
µs
tclk(L)
clock LOW time
1
-
-
µs
-
-
400
ns
1
-
-
µs
-
-
30
µs
tPD(SYNC_N) SYNC propagation delay
tSYNC_NL
SYNC LOW time
tPD(drv)
driver propagation delay
VLCD = VDD − 5 V
Timing characteristics: I2C-bus (see Figure 28)
[2]
tBUF
bus free time between a STOP and START
condition
4.7
-
-
µs
tHD;STA
hold time (repeated) START condition
4.0
-
-
µs
tSU;STA
set-up time for a repeated START condition
4.7
-
-
µs
tLOW
LOW period of the SCL clock
4.7
-
-
µs
tHIGH
HIGH period of the SCL clock
4.0
-
-
µs
tr
rise time of both SDA and SCL signals
-
-
1
µs
tf
fall time of both SDA and SCL signals
-
-
0.3
µs
Cb
capacitive load for each bus line
-
-
400
pF
tSU;DAT
data set-up time
250
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP condition
4.0
-
-
µs
[1]
fclk < 125 kHz, I2C-bus maximum transmission speed is derated.
[2]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
33 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
1/fCLK
tclk(H)
tclk(L)
0.7VDD
CLK
0.3VDD
0.7VDD
SYNC
0.3VDD
tPD(SYNC_N)
tPD(SYNC_N)
tSYNC_NL
0.5 V
BP0 to BP3,
and S0 to S39
(VDD = 5 V)
0.5 V
tPD(drv)
mce424
Fig 27. Driver timing waveforms
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA
tSU;STO
mga728
Fig 28. I2C-bus timing waveforms
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
34 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
13. Application information
13.1 Cascaded operation
In large display configurations, up to 16 PCF8576Cs can be recognized on the same
I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable
I2C-bus slave address (SA0).
Table 21.
Addressing cascaded PCF8576C
Cluster
Bit SA0
Pin A2
Pin A1
Pin A0
Device
1
0
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
0
0
0
8
0
0
1
9
0
1
0
10
0
1
1
11
1
0
0
12
1
0
1
13
1
1
0
14
1
1
1
15
2
1
Cascaded PCF8576Cs are synchronized. They can share the backplane signals from one
of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCF8576Cs of the cascade contribute
additional segment outputs but their backplane outputs are left open-circuit (see
Figure 29).
The PCF8576C can also be cascaded with the PCF8566. The connections are identical to
the PCF8576C cascade.
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
35 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
VDD
SDA 1
SCL 2
SYNC
VLCD
5
12
17 to 56 40 segment drives
LCD PANEL
PCF8576CT
3
CLK
13,15,
14,16
4
OSC 6
A0
A1
A2
BP0 to BP3
(open-circuit)
(up to 2560
elements)
SAO VSS
VLCD
VDD
R≤
tr
2CB
VLCD
VDD
5
HOST
MICROPROCESSOR/
MICROCONTROLLER
SDA
SCL
SYNC
CLK
OSC
12
1
17 to 56
2
40 segment drives
PCF8576CT
3
13,15,
14,16
4
4 backplanes
BP0 to BP3
6
mbe533
7
VSS
A0
8
A1
9
A2
10
11
SA0 VSS
Fig 29. Cascaded PCF8576C configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8576Cs. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the defining a multiplex mode when PCF8576Cs
with differing SA0 levels are cascaded).
SYNC is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF8576C asserts the SYNC line
and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is
restored by the first PCF8576C to assert SYNC. The timing relationship between the
backplane waveforms and the SYNC signal for the various drive modes of the PCF8576C
are shown in Figure 30.
For single plane wiring of packaged PCF8576Cs and chip-on-glass cascading, see
Figure 31.
.
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
36 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
Tfr =
1
ffr
BP0
SYNC
(a) static drive mode.
BP0
(1/2 bias)
BP0
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Excessive capacitive coupling between SCL or CLK and SYNC will cause erroneous
synchronization. If this is a problem you can increase the capacitance of the SYNC line (e.g. by an
external capacitor between SYNC and VDD.) Degradation of the positive edge of the SYNC pulse
can be countered by an external pull-up resistor.
Fig 30. Synchronization of the cascade for the various PCF8576C drive modes
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
37 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
SDA
SCL
SYNC
CLK
VDD
VSS
VLCD
SDA
1
56
S39
1
56
S79
SCL
2
55
S38
2
55
S78
SYNC
3
54
S37
3
54
S77
CLK
4
53
S36
4
53
S76
VDD
5
52
S35
5
52
S75
OSC
6
51
S34
6
51
S74
A0
7
50
S33
7
50
S73
A1
8
49
S32
8
49
S72
A2
9
48
S31
9
48
S71
SA0
10
47
S30
10
47
S70
VSS
11
46
S29
11
46
S69
VLCD
12
45
S28
12
45
S68
BP0
13
44
S27
BP0
13
44
S67
BP2
14
43
S26
BP2
14
43
S66
BP1
15
42
S25
BP1
15
42
S65
BP3
16
41
S24
BP3
16
41
S64
S0
17
40
S23
S40
17
40
S63
S1
18
39
S22
S41
18
39
S62
S2
19
38
S21
S42
19
38
S61
S3
20
S43
20
34
S17
34
S57
S7
24
33
S16
S47
24
33
S56
S8
25
32
S15
S48
25
32
S55
S9
26
31
S14
S49
26
31
S54
S10
27
30
S13
S50
27
30
S53
S11
28
29
S12
S51
28
29
S52
open
PCF8576CT
S0
S10
S11
S12
S13
S39
S40
segments
backplanes
S50
PCF8576CT
S51
S52
S53
S79
mbe537
Fig 31. Single plane wiring of packaged PCF8576CTs
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
38 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
14. Package outline
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
wM
θ
bp
pin 1 index
64
Lp
L
17
detail X
16
1
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
1.45
1.05
1.45
1.05
θ
7o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT314-2
136E10
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 32. Package outline SOT314-2 (LQFP64) of PCF8576CH
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
39 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
HE
v M A
Z
56
29
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
detail X
28
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
3.3
0.3
0.1
3.0
2.8
0.25
0.42
0.30
0.22
0.14
21.65
21.35
11.1
11.0
0.75
15.8
15.2
2.25
1.6
1.4
1.45
1.30
0.2
0.1
0.1
0.90
0.55
inches
0.13
0.012
0.004
0.12
0.11
0.01
0.017 0.0087 0.85
0.012 0.0055 0.84
0.44
0.62
0.0295
0.43
0.60
0.089
0.063
0.055
0.057
0.035
0.008 0.004 0.004
0.051
0.022
θ
7o
o
0
Notes
1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
97-08-11
03-02-19
SOT190-1
Fig 33. Package outline SOT190-1 (VSO56) of PCF8576CT
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
40 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
HTSSOP56: plastic thermal enhanced thin shrink small outline package; 56 leads;
body width 6.1 mm; exposed die pad
D
SOT793-1
A
E
X
c
y
exposed die pad
v M A
HE
Dh
Z
56
29
(A 3)
A A2
Eh
θ
A1
pin 1 index
Lp
L
detail X
1
28
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
Dh
E (2)
Eh
e
HE
L
Lp
v
w
y
Z (1)
θ
mm
1.2
0.15
0.05
1.05
0.80
0.25
0.27
0.17
0.20
0.09
14.1
13.9
4.3
4.1
6.2
6.0
4.3
4.1
0.5
8.3
7.9
1
0.8
0.4
0.2
0.08
0.1
0.4
0.1
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT793-1
143E36T
MO-153
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
03-03-04
Fig 34. Package outline SOT793-1 (HTSSOP56) of PCF8576CTT
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
41 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
15. Bare die outline
Wire bond die; 56 bonding pads; 3.0 x 2.82 x 0.38 mm
PCF8576CU/10
D
A
34
21
C1
20
35
e
X
x
0
E
0
y
(4)
50
8
C2
51
56
1
7
F
P4
P3
P2
P1
detail X
0
0.5
scale
Dimensions
Unit
mm
1 mm
A
D
E
e(3)
P1(1)
P2(2)
P3(1)
P4(2)
max
0.610
nom 0.38 2.82 3.00
0.110 0.097 0.110 0.097
min
0.096
Note
1. Pad size
2. Passivation opening
3. Dimension not drawn to scale
4. Marking code: PC8576C-1
Outline
version
pcf8576cu_10_do
References
IEC
JEDEC
JEITA
PCF8576CU/10
European
projection
Issue date
09-06-02
Fig 35. Bare die outline of PCF8576CU/10
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
42 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
Wire bond die; 56 bonding pads; 3.0 x 2.82 x 0.38 mm
PCF8576CU
D
A
34
21
C1
20
35
e
X
x
0
E
0
y
(4)
50
8
C2
51
56
1
7
F
P4
P3
P2
P1
detail X
0
0.5
scale
Dimensions
Unit
mm
1 mm
A
D
E
e(3)
P1(1)
P2(2)
P3(1)
P4(2)
max
0.610
nom 0.38 2.82 3.00
0.110 0.097 0.110 0.097
min
0.096
Note
1. Pad size
2. Passivation opening
3. Dimension not drawn to scale
4. Marking code: PC8576C-1
Outline
version
pcf8576cu_do
References
IEC
JEDEC
JEITA
PCF8576CU
European
projection
Issue date
29-06-02
Fig 36. Bare die outline of PCF8576CU
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
43 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
Bare die; 56 bumps; 3.0 x 2.82 x 0.40 mm
PCF8576CU/2
D
34
21
C1
20
35
e
X
x
E
0
0
y
(2)
50
8
C2
51
56
1
7
F
Y
L
A
A2
A1
b
detail X
detail Y
0
0.5
scale
Dimensions
Unit
mm
1 mm
A
A1
A2
b
max
nom 0.398 0.0175 0.380 0.094
min
D
E
e(1)
L
0.610
2.82
3.00
0.094
0.096
Note
1. Dimension not drawn to scale
2. Marking code: PC8576C-2
Outline
version
pcf8576cu_2_do
References
IEC
JEDEC
JEITA
PCF8576CU/2
European
projection
Issue date
09-06-02
Fig 37. Bare die outline of PCF8576CU/2
PCF8576C_9
Product data sheet
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Rev. 09 — 9 July 2009
44 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 22. Pad and bump description for PCF8576CU
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip.
Symbol
Pad
X (µm)
Y (µm)
Description
SDA
1
−74
−1380
I2C-bus serial data input/output
SCL
2
148
−1380
I2C-bus serial clock input
SYNC
3
355
−1380
cascade synchronization input/output
CLK
4
534
−1380
external clock input/output
VDD
5
742
−1380
supply voltage
OSC
6
913
−1380
internal oscillator enable input
A0
7
1087
−1380
subaddress input
A1
8
1290
−1284
subaddress input
A2
9
1290
−1116
subaddress input
SA0
10
1290
−945
subaddress input
VSS
11
1290
−751
logic ground
VLCD
12
1290
−485
LCD supply voltage
BP0
13
1290
125
LCD backplane output
BP2
14
1290
285
LCD backplane output
BP1
15
1290
458
LCD backplane output
BP3
16
1290
618
LCD backplane output
S0
17
1290
791
LCD segment output
S1
18
1290
951
LCD segment output
S2
19
1290
1124
LCD segment output
S3
20
1290
1284
LCD segment output
S4
21
1074
1380
LCD segment output
S5
22
914
1380
LCD segment output
S6
23
741
1380
LCD segment output
S7
24
581
1380
LCD segment output
S8
25
408
1380
LCD segment output
S9
26
248
1380
LCD segment output
S10
27
75
1380
LCD segment output
S11
28
−85
1380
LCD segment output
S12
29
−258
1380
LCD segment output
S13
30
−418
1380
LCD segment output
S14
31
−591
1380
LCD segment output
S15
32
−751
1380
LCD segment output
S16
33
−924
1380
LCD segment output
S17
34
−1084
1380
LCD segment output
S18
35
−1290
1243
LCD segment output
S19
36
−1290
1083
LCD segment output
S20
37
−1290
910
LCD segment output
S21
38
−1290
750
LCD segment output
S22
39
−1290
577
LCD segment output
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
45 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 22. Pad and bump description for PCF8576CU
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip.
Symbol
Pad
X (µm)
Y (µm)
Description
S23
40
−1290
417
LCD segment output
S24
41
−1290
244
LCD segment output
S25
42
−1290
84
LCD segment output
S26
43
−1290
−89
LCD segment output
S27
44
−1290
−249
LCD segment output
S28
45
−1290
−422
LCD segment output
S29
46
−1290
−582
LCD segment output
S30
47
−1290
−755
LCD segment output
S31
48
−1290
−915
LCD segment output
S32
49
−1290
−1088
LCD segment output
S33
50
−1290
−1248
LCD segment output
S34
51
−1083
−1380
LCD segment output
S35
52
−923
−1380
LCD segment output
S36
53
−750
−1380
LCD segment output
S37
54
−590
−1380
LCD segment output
S38
55
−417
−1380
LCD segment output
S39
56
−257
−1380
LCD segment output
Table 23.
Alignment marks
Symbol
X (µm)
Y (µm)
C1
−1290
1385
C2
−1295
−1385
F
1305
−1405
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
17. Packing information
17.1 Tray information
Tray information for the PCF8576CU and PCF8576CU/2 is shown in Figure 38, Figure 39
and Table 24.
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
46 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
G
A
C
H
D
B
F
E
001aai237
marking code
Fig 38. Tray details
001aaj619
Fig 39. Tray alignment
Table 24.
Tray dimensions
Symbol
Description
Value
A
pocket pitch; x direction
5.59 mm
B
pocket pitch; y direction
6.35 mm
C
pocket width; x direction
3.22 mm
D
pocket width; y direction
3.50 mm
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
47 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 24.
Tray dimensions
Symbol
Description
Value
E
tray width; x direction
50.67 mm
F
tray width; y direction
50.67 mm
G
cut corner to pocket 1,1 center
5.78 mm
H
cut corner to pocket 1,1 center
6.29 mm
J
tray thickness
3.94 mm
K
tray cross section
1.76 mm
L
tray cross section
2.46 mm
M
pocket depth
0.89 mm
x
number of pockets; x direction
8
y
number of pockets; y direction
7
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
48 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
17.2 Film frame carrier information
100 m
S aw lane
200 m
detail X
Marking code
Straight edge
of the wafer
X
013aaa112
Fig 40. Layout of wafer on film frame carrier of PCF8576CU/10
PCF8576C_9
Product data sheet
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Rev. 09 — 9 July 2009
49 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCF8576C_9
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PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 41) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 25 and 26
Table 25.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 26.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 41.
PCF8576C_9
Product data sheet
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Rev. 09 — 9 July 2009
51 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 41. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
52 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
19. Abbreviations
Table 27.
Abbreviations
Acronym
Description
DC
Direct Current
FFC
Film Frame Carrier
HBM
Human Body Model
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MM
Machine Model
MOS
Metal Oxide Semiconductor
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
PCB
Printed-Circuit Board
POR
Power-On Reset
RC
Resistance-Capacitance
RAM
Random Access Memory
RMS
Root Mean Square
SCL
Serial Clock Line
SDA
Serial Data Line
SMD
Surface Mount Device
PCF8576C_9
Product data sheet
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Rev. 09 — 9 July 2009
53 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
20. Revision history
Table 28.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF8576C_9
20090709
Product data sheet
-
PCF8576C_8
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Symbols updated and checked with NXP Symbols Library
Changed values in limiting values table (see Table 18) from relative to absolute values
Added TT type
Added bare die outline drawings
Added FFC information
Rewritten chapter 7.3 (see Section 7.3)
PCF8576C_8
20041122
Product specification
-
PCF8576C_7
PCF8576C_7
20011002
Product specification
-
PCF8576C_6
PCF8576C_6
19980730
Product specification
-
PCF8576C_5
PCF8576C_5
19971114
Product specification
-
PCF8576C_4
PCF8576C_4
19970402
Product specification
-
PCF8576C_3
PCF8576C_3
19970203
Product specification
-
PCF8576C_2
PCF8576C_2
19961209
Product specification
-
PCF8576C_1
PCF8576C_1
19950630
Product specification
-
-
PCF8576C_9
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 09 — 9 July 2009
54 of 56
PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
21.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF8576C_9
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Rev. 09 — 9 July 2009
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PCF8576C
NXP Semiconductors
Universal LCD driver for low multiplex rates
23. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.5.1
7.5.2
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.14.1
7.14.2
7.15
8
8.1
8.1.1
8.1.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional description . . . . . . . . . . . . . . . . . . . 9
Power-on-reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
LCD bias generator. . . . . . . . . . . . . . . . . . . . . 10
LCD voltage selector . . . . . . . . . . . . . . . . . . . 10
LCD drive mode waveforms . . . . . . . . . . . . . . 12
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 12
1:2 Multiplex drive mode . . . . . . . . . . . . . . . . . 13
1:3 Multiplex drive mode . . . . . . . . . . . . . . . . . 15
1:4 multiplex drive mode . . . . . . . . . . . . . . . . . 16
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 17
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Display register . . . . . . . . . . . . . . . . . . . . . . . . 18
Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 18
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 18
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sub-address counter . . . . . . . . . . . . . . . . . . . 21
Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output bank selector. . . . . . . . . . . . . . . . . . . . 21
Input bank selector . . . . . . . . . . . . . . . . . . . . . 22
Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Basic architecture . . . . . . . . . . . . . . . . . . . . . . 23
Characteristics of the I2C-bus . . . . . . . . . . . . . 23
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
START and STOP conditions . . . . . . . . . . . . . 23
System configuration . . . . . . . . . . . . . . . . . . . 23
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24
PCF8576C I2C-bus controller . . . . . . . . . . . . . 25
Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 25
Command decoder . . . . . . . . . . . . . . . . . . . . . 26
Mode set command . . . . . . . . . . . . . . . . . . . . 27
Load data pointer command . . . . . . . . . . . . . . 27
Device select command . . . . . . . . . . . . . . . . . 27
Bank select command . . . . . . . . . . . . . . . . . . 28
8.3.5
8.4
9
10
11
11.1
11.2
12
13
13.1
14
15
16
17
17.1
17.2
18
18.1
18.2
18.3
18.4
19
20
21
21.1
21.2
21.3
21.4
22
23
Blink command. . . . . . . . . . . . . . . . . . . . . . . .
Display controller . . . . . . . . . . . . . . . . . . . . . .
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Typical supply current characteristics. . . . . . .
Typical LCD output characteristics . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Cascaded operation . . . . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Tray information . . . . . . . . . . . . . . . . . . . . . . .
Film frame carrier information . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 9 July 2009
Document identifier: PCF8576C_9