INTEGRATED CIRCUITS DATA SHEET 74LVC32245A; 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state Product specification File under Integrated Circuits, IC24 1999 Sep 01 Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC32245A; 74LVCH32245A FEATURES DESCRIPTION • 5 V tolerant inputs/outputs for interfacing with 5 V logic The 74LVC(H)32245A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment. • Wide supply voltage range of 1.2 to 3.6 V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTE flow-trough standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce The 74LVC(H)32245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The 74LVC(H)32245A features two output enable (nOE) inputs for easy cascading and two send or receive (nDIR) inputs for direction control. nOE controls the outputs so that the buses are effectively isolated. • Direct interface with TTL levels • Bus hold on data inputs (74LVCH32245A only) • Typical output ground bounce voltage: VOLP < 0.8 V at VCC = 3.3 V; Tamb = 25 °C • Typical output VOH undershoot voltage: VOHV > 2 V at VCC = 3.3 V; Tamb = 25 °C To ensure the high-impedance state during power-up or power-down, input nOE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. • Power-off disabled outputs, permitting live insertion • Plastic fine-pitch ball grid array package. The 74LVCH32245A bus hold data inputs eliminates the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level (see Fig.2). QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL PARAMETER tPHL/tPLH propagation delay nAn to nBn; nBn to nAn CI input capacitance CI/O input/output capacitance CPD power dissipation capacitance per buffer CONDITIONS CL = 50 pF; VCC = 3.3 V VI = GND to VCC; note 1 Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; Σ(CL × VCC2 × fo) = sum of the outputs. 1999 Sep 01 2 TYPICAL UNIT 3.0 ns 5.0 pF 10 pF 30 pF Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC32245A; 74LVCH32245A FUNCTION TABLE See note 1. INPUT OUTPUT nOE nDIR nAn nBn L L A=B inputs L H inputs B=A H X Z Z Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGES TYPE NUMBER 74LVC32245AEC TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +85 °C 96 LFBGA96 plastic SOT536-1 96 LFBGA96 plastic SOT536-1 74LVCH32245AEC PINNING SYMBOL DESCRIPTION nDIR direction control nOE output enable input (active LOW) nAn data inputs/outputs nBn data inputs/outputs GND ground (0 V) VCC DC supply voltage 1999 Sep 01 3 Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC32245A; 74LVCH32245A MNA475 handbook, full pagewidth 6 1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A6 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A6 5 1A0 1A2 1A4 1A6 2A0 2A2 2A4 2A7 3A0 3A2 3A4 3A6 4A0 4A2 4A4 4A7 4 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 3 1DIR GND VCC GND GND VCC GND 2DIR 3DIR GND VCC GND GND VCC GND 4DIR 2 1B0 1B2 1B4 1B6 2B0 2B2 2B7 3B0 3B2 3B4 3B6 4B0 4B2 4B4 4B7 1 1B1 1B3 1B5 1B7 2B1 2B3 2B51 2B6 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B6 A B C D E J K L M N P R T 2B4 F G H Fig.1 Pin configuration. handbook, halfpage VCC data input to internal circuit MNA473 Fig.2 Bus hold circuit. 1999 Sep 01 4 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... H3 1OE A5 E5 A6 E6 1B1 B5 F5 1B2 B6 5 G6 1A6 1A7 D1 2A7 M6 2B7 4B6 T5 3B7 M1 R2 R1 4A6 M2 3A7 H2 4B5 T6 3B6 H1 4B4 4A5 L1 3A6 P1 4A4 L2 R6 3B5 M5 2B6 H5 1B7 2A6 D2 3B4 3A5 G1 4B3 R5 P2 4A3 K1 3A4 G2 L6 2B5 H6 1B6 D6 2B4 2A5 C1 3B3 L5 4B2 P6 N1 4A2 K2 3A3 F1 2A4 C2 1A5 1B5 D5 2B3 G5 3B2 K6 4B1 P5 N2 4A1 J1 3A2 F2 2A3 B1 1A4 1B4 C6 2B2 F6 3B1 K5 4B0 N6 T4 4A0 J2 3A1 E1 2A2 B2 1A3 1B3 C5 2B1 A1 1A2 J6 4OE N5 3B0 4DIR J4 3A0 E2 2A1 T3 3OE J5 2B0 3DIR H4 2A0 A2 1A1 J3 2OE A4 1A0 1B0 2DIR Philips Semiconductors 1DIR 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state ook, full pagewidth 1999 Sep 01 A3 T1 4A7 4B7 T2 MNA476 Product specification 74LVC32245A; 74LVCH32245A Fig.3 Logic symbol. Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC32245A; 74LVCH32245A RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN. VCC DC supply voltage VI DC input voltage VO DC output voltage for max. speed performance for low-voltage applications 2.7 MAX. 3.6 V 1.2 3.6 V 0 5.5 V output HIGH or LOW state 0 VCC V 3-state 0 5.5 V Tamb operating ambient temperature see DC and AC characteristics per device −40 +85 °C tr,tf (∆t/∆f) input rise and fall times ratio VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. −0.5 MAX. +6.5 UNIT VCC DC supply voltage VI DC input voltage note 1 −0.5 +6.5 V IIK DC input diode current VI < 0 − −50 mA IOK DC output diode current VO > VCC or VO < 0; note 1 − ±50 mA VO DC output voltage output HIGH or LOW state; note 1 −0.5 VCC + 0.5 V IO DC output source or sink current ICC, IGND DC VCC or GND current Tstg storage temperature PD power dissipation per package output 3-state; note 1 −0.5 +6.5 V VO = 0 to VCC − ±50 mA − ±100 mA −65 +150 °C − 1000 mW temperature range: −40 to +85 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 70 °C the value of PD derates linearly with 1.8 mW/K. 1999 Sep 01 V 6 Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC32245A; 74LVCH32245A DC CHARACTERISTICS Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH −40 to +85 PARAMETER HIGH-level input voltage VCC (V) 1.2 2.7 to 3.6 2.0 VIL VOH VOL LOW-level input voltage HIGH-level output voltage LOW-level output voltage TYP.(1) MAX. MIN. VCC UNIT − − − − − − GND 2.7 to 3.6 − − 0.8 1.2 V V VI = VIH or VIL IO = −12 mA 2.7 VCC − 0.5 − − IO = −100 µA 3.0 VCC − 0.2 VCC − IO = −18 mA 3.0 VCC − 0.6 − − IO = −24 mA 3.0 VCC − 0.8 − − IO = 12 mA 2.7 − − 0.40 IO = 100 µA 3.0 − − 0.20 V VI = VIH or VIL V 3.0 − − 0.55 II input leakage current VI = 5.5 V or GND; note 2 3.6 − ±0.1 ±5 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND 3.6 − 0.1 ±5 µA Ioff power off leakage supply current VI or VO = 5.5 V 0.0 − 0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − 0.1 40 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 0.6 V; IO = 0 2.7 to 3.6 − 5 500 µA IBHL bus hold LOW sustaining current VI = 0.8 V; notes 3, 4 and 5 3.0 75 − − µA IBHH bus hold HIGH sustaining current VI = 2.0 V; notes 3, 4 and 5 3.0 −75 − − µA IBHLO bus hold LOW overdrive current notes 3, 4 and 6 3.6 500 − − µA IBHHO bus hold HIGH overdrive current notes 3, 4 and 6 3.6 −500 − − µA IO = 24 mA Notes 1. All typical values are at VCC = 3.3 V and Tamb = 25 °C. 2. For bus hold parts the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal. 3. Valid for data inputs of bus hold parts only (LVCH32xxx-A). 4. For data inputs only. Control inputs do not have a bus hold circuit. 5. The specified sustaining current at the data input holds the input below the specified VI level. 6. The specified overdrive current at the data input forces the data input to the opposite logic input level. 1999 Sep 01 7 Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC32245A; 74LVCH32245A AC CHARACTERISTICS Ground = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω. Tamb = −40 to +85 °C TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH tPZH/tPZL tPHZ/tPLZ propagation delay nAn to nBn; nBn to nAn see Figs 4 and 6 3-state output enable time nOE to nAn; nOE to nBn see Figs 5 and 6 3-state output disable time nOE to nAn; nOE to nBn see Figs 5 and 6 VCC (V) MIN. 1.5 − 5.5 3.0 to 3.6 1.5 3.0 4.5 2.7 1.5 − 7.1 3.0 to 3.6 1.5 4.0 6.1 2.7 1.5 − 6.6 3.0 to 3.6 1.5 4.0 5.6 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. AC WAVEFORMS handbook, halfpage VI VM INPUT GND t PHL t PLH VOH nBn, nAn VM OUTPUT VOL MNA477 VM = 1.5 V at VCC ≥ 2.7 V or VM = 0.5 × VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.4 Input nAn, nBn to output nBn, nAn propagation delay times. 1999 Sep 01 8 UNIT MAX. 2.7 Note nAn, nBn TYP.(1) ns ns ns Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC32245A; 74LVCH32245A VI handbook, full pagewidth nOE INPUT VM GND t PLZ t PZL VCC OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY OUTPUT HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs enabled outputs disabled MNA478 VM = 1.5 V at VCC ≥ 2.7 V or VM = 0.5 × VCC at VCC < 2.7 V; VX = VOL + 0.3 V at VCC ≥ 2.7 V or VX = VOL + 0.1 V at VCC < 2.7 V; VY = VOH − 0.3 V at VCC ≥ 2.7 V or VY = VOH − 0.1 V at VCC < 2.7 V; VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 3-state enable and disable times. S1 handbook, full pagewidth VCC PULSE GENERATOR VI RL 500 Ω VO 2 × VCC open GND D.U.T. CL 50 pF RT RL 500 Ω MNA479 TEST S1 VCC Definitions for test circuit: RL = load resistor. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. VI tPLH/tPHL open tPLZ/tPZL 2 × VCC < 2.7 V tPHZ/tPZH GND 2.7 to 3.6 V 2.7 V VCC Fig.6 Load circuitry for switching times. 1999 Sep 01 9 Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC32245A; 74LVCH32245A PACKAGE OUTLINE LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 D ball A1 index area A2 A E A1 detail X b A ∅w M ZD e y v A ZE T R P N M L K J H G F E D C B A e X 1 2 3 4 5 6 DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e v w y ZD ZE mm 1.5 0.41 0.31 1.2 0.9 0.51 0.41 5.6 5.4 13.6 13.4 0.8 0.2 0.15 0.1 0.93 0.58 0.93 0.58 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ 5 10 mm scale EUROPEAN PROJECTION ISSUE DATE 98-11-25 99-06-03 SOT536-1 1999 Sep 01 0 10 Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state SOLDERING 74LVC32245A; 74LVCH32245A If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Sep 01 11 Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC32245A; 74LVCH32245A Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Sep 01 12 Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state NOTES 1999 Sep 01 13 74LVC32245A; 74LVCH32245A Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state NOTES 1999 Sep 01 14 74LVC32245A; 74LVCH32245A Philips Semiconductors Product specification 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state NOTES 1999 Sep 01 15 74LVC32245A; 74LVCH32245A Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245004/01/pp16 Date of release: 1999 Sep 01 Document order number: 9397 750 06259