SCDS192 − APRIL 2005
D Supports SSTL_18 Signaling Levels
D Suitable for DDR-II Applications
D D−Port Outputs Are Precharged by Bias
D
D
D
Voltage (VBIAS)
Internal Termination for Control Inputs
High Bandwidth (334 MHz Min)
Low and Flat ON-State Resistance (ron)
Characteristics, (ron = 17 W Max)
D Internal 400-W Pulldown Resistors
D Low Differential and Rising/Falling Edge
Skew
D Latch-Up Performance Exceeds 100 mA Per
D
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
description/ordering information
The SN74CBTU4411 is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low
ON-state resistance (ron). The device utilizes an internal charge pump to elevate the gate voltage of the pass
transistor, providing a low and flat ron. The low and flat ron allows for minimal propagation delay and supports
rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to
minimize capacitive loading and signal distortion on the data bus. Matched ron and I/O capacitance among
channels results in extremely low differential and rising/falling edge skew. This allows the device to show optimal
performance in DDR-II applications.
The device is organized as an 11-bit 1-of-4 multiplexer/demultiplexer with a single switch-enable (EN) input.
When EN is low, the switch is enabled and the H port is connected to one of the D ports. Ports D0 to D9 for the
disabled channels are connected to VBIAS through a 400 Ω resistor. DQS_EN determines the output voltage
for the disabled D10 ports. When DQS_EN is low, this voltage is VBIAS. When DQS_EN is high, the disabled
D10 ports are connected to an internal voltage (VBIAS_DQS) source, which is approximately equal to 0.7 VDD.
When EN is high, all the channels are disabled. Ports D0 to D9 are connected to VBIAS. For the D10 port, the
disabled output voltage is determined by the DQS_EN input. When DQS_EN is low, this voltage is VBIAS. When
DQS_EN is high, this voltage is VDD.
The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. The EN and TC inputs
determine the internal termination for S0 and S1 inputs. When EN is low, the termination is determined by the
TC input. When both EN and TC are low, termination resistors are disconnected from the S inputs. When EN
is low and TC is high, both pullup and pulldown resistors are connected to the S inputs. When EN is high, only
the pulldown termination resistors are connected to the S inputs, regardless of the voltage level at the TC input.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 85°C
LFBGA − GST
Tape and reel
SN74CBTU4411GSTR
CTU4411
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%)
"!-('%& '!!"# %! &*)''$%!& *)" %.) %)"#& ! )/$& &%"(#)%&
&%$-$"- 0$""$%1 "!-('%! *"!')&&2 -!)& !% )')&&$",1 ',(-)
%)&%2 ! $,, *$"$#)%)"&
POST OFFICE BOX 655303
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1
SCDS192 − APRIL 2005
GST PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
G
H
J
K
L
terminal assignments
1
2
3
4
5
6
7
8
A
S1
DQS_EN
1D0
2D0
1D1
TC
S0
VDD
VDD
0D0
B
GND
H0
3D0
0D1
C
VREF
VBIAS
2D10
D
E
2
9
10
11
2D1
3D1
0D2
1D2
H1
GND
H2
2D2
EN
0D3
3D2
GND
H3
1D3
3D10
2D3
3D3
F
1D10
H10
GND
0D4
G
0D10
GND
H4
1D4
H
3D9
2D9
2D4
3D4
J
1D9
H9
1D5
0D5
K
0D9
GND
H8
0D8
H7
0D7
GND
H6
0D6
H5
2D5
L
3D8
2D8
1D8
3D7
2D7
1D7
3D6
2D6
1D6
VDD
3D5
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SCDS192 − APRIL 2005
FUNCTION TABLES
INPUTS
EN
DQS_EN
S1
S0
INPUT/OUTPUT
Hn
FUNCTION
L
L
L
L
0Dn
Hn = 0Dn
1Dn, 2Dn, 3Dn connected to VBIAS
L
L
L
H
1Dn
Hn = 1Dn
0Dn, 2Dn, 3Dn connected to VBIAS
L
L
H
L
2Dn
Hn = 2Dn
0Dn, 1Dn, 3Dn connected to VBIAS
L
L
H
H
3Dn
Hn = 3Dn
0Dn, 1Dn, 2Dn connected to VBIAS
L
H
L
L
0Dn
L
H
L
H
1Dn
L
H
H
L
2Dn
L
H
H
H
3Dn
H
L
X
X
Z
H
H
X
X
Z
H0−H9 = 0D0−0D9
1D0−1D9, 2D0−2D9, 3D0−3D9 connected to VBIAS
H10 = 0D10
1D10, 2D10, 3D10 connected to VBIAS_DQS†
H0−H9 = 1D0−1D9
0D0−0D9, 2D0−2D9, 3D0−3D9 connected to VBIAS
H10 = 1D10
0D10, 2D10, 3D10 connected to VBIAS_DQS†
H0−H9 = 2D0−2D9
0D0−0D9, 1D0−1D9, 3D0−3D9 connected to VBIAS
H10 = 2D10
0D10, 1D10, 3D10 connected to VBIAS_DQS†
H0−H9 = 3D0−3D9
0D0−0D9, 1D0−1D9, 2D0−2D9 connected to VBIAS
H10 = 3D10
0D10, 1D10, 2D10 connected to VBIAS_DQS†
0Dn, 1Dn, 2Dn, 3Dn connected to VBIAS
0D0−0D9, 1D0−1D9, 2D0−2D9, 3D0−3D9 connected to VBIAS
0D10, 1D10, 2D10, 3D10 connected to VDD
† VBIAS_DQS is an internal voltage condition.
INPUTS
EN
FUNCTION
TC
L
L
L
H
Termination resistors connected with S inputs
X
Pulldown termination resistor connected and pullup
termination resistor disconnected from the S inputs
H
Termination resistors disconnected from S inputs
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3
SCDS192 − APRIL 2005
logic diagram (positive logic)
D1
VBIAS
B5
H0
A4
SW1
A5
SW1
0D0
1D0
A6
SW1
2D0
B6
3D0
SW1
F2
G1
H10
0D10
SW2
F1
SW2
1D10
E1
2D10
SW2
E2
SW2
VDD
EN
TC
C2
B1
M1†
VREF
r1†
S0
B2
r2†
M2†
VDD
M1†
r1†
S1
A1
r2†
M2†
A2
DQS_EN
† r1 + ron (M1), r2 + ron (M2) = 160 Ω Typical.
4
POST OFFICE BOX 655303
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CONTROL DECODE
LOGIC
3D10
SCDS192 − APRIL 2005
simplified schematic, each FET switch (SW1)
H†
D‡
VDD
r3§
Charge
Pump
M3§
EN¶
VBIAS
† Applicable for ports H0 through H9
‡ Applicable for ports D0 through D9
§ r3 + ron (M3) = 400 Ω Typical.
¶ EN is the internal enable signal applied to the switch.
simplified schematic, each FET switch (SW2)
VDD
EN_DQS1#
M4||
r4||
H10
VDD
VBIAS_DQS
D10
r6h
r5k
Charge
Pump
M5k
EN1#
EN2#
M6h
EN_DQS2#
VBIAS
# EN_DQS1, EN_DQS2, EN1, and EN2 are the internal enable signals applied to the switch.
|| r4 + ron (M4) = 1 kΩ Typical.
k r + r (M5) = 400 Ω Typical.
5 on
h r + r (M6) = 2.3 kΩ Typical.
6 on
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5
SCDS192 − APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Control input clamp current, IIK (VIN < 0 or VIN > 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
I/O port clamp current, II/OK (VI/O < 0 or VI/O > 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Continuous current through VDD or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
VDD
VREF
Supply voltage
VBIAS
BIAS supply voltage
Reference supply voltage
TYP
MAX
UNIT
1.7
1.8
1.9
V
0.49 VDD
0.5 VDD
0.51 VDD
V
0.3 VDD
0.33 VDD
V
0
High-level control input voltage (S)
VIH
MIN
High-level control input voltage (EN, TC, DQS_EN)
VREF +250 mV
0.65 VDD
Low-level control input voltage (S)
VIL
VI/O
TA
V
VREF −250 mV
0.35 VDD
Low-level control input voltage (EN, TC, DQS_EN)
Data input/output voltage
0
Operating free-air temperature
0
VDD
85
V
V
°C
NOTE 6: All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
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SCDS192 − APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK‡
Control
inputs§
TA = 70 °C
MIN MAX
TEST CONDITIONS
VDD = 1.7 V,
IIN = −18 mA
VDD = 1.7 V,
VDD = 1.7 V,
DQS_EN = VDD,
DQS_EN = VDD
VDD = 1.9 V,
VIN = VDD or GND
IOZ¶
VDD = 1.9 V,
VO = 0 to 1.9 V, Switch OFF,
VI = 0,
VBIAS open
ICC
VDD = 1.9 V,
TC = GND,
EN = GND,
II/O = 0,
Switch ON
S0, S1 = VIH or
or OFF
VIL,
VBIAS_DQS D10
VOH
D10
IIN
Control
inputs§
EN = VDD,
TA = 0 °C TO 85 °C
TYP†
MAX
MIN
1.1
IO = 100 µA
1.6
0.7
EN = VDD
UNIT
−1.8
V
1.275
V
1.8
V
±1
µA
±10
µA
2.5
mA
500
µA
0.5
mA/MHz#
3.5
pF
VDD = 1.9 V,
TC = GND,
EN = GND,
II/O = 0,
S0 or S1 input switching at
50% duty cycle, Data I/O are
open
S port
VDD = 1.9 V,
TC = GND,
EN = GND,
VIN = VREF ± 250 mV
EN, TC,
DQS_EN
inputs
VDD = 1.9 V,
VIN = 0 or 1.9 V
H port
VI/O = 0.5 VDD ±
0.4 V
Switch OFF,
VBIAS open
2.5
pF
Cio(ON)
VI/O = 0.5 VDD ±
0.4 V,
Switch ON,
VBIAS =
GND
4.6
pF
ron||
VDD = 1.7 V,
VI = 0.5 VDD ± 0.5 V,
10
17
Ω
∆ron (flat)k
VDD = 1.7 V,
DQS_EN = VDD,
IO = 10 mA
VI = 0.5 VDD ± 0.25 V
1.5
3
Ω
VI = 0.5 VDD ± 0.5 V
2.5
5
Ω
110
160
210
Ω
280
400
520
DQS_EN = VDD, EN = GND
1600
2300
3000
DQS_EN = VDD, EN = GND
700
1000
1300
ICCD
Cin
Cio(OFF)
rterm
S port
rpullup
D10
D10
2.5
IO = 10 mA
VDD = 1.7 V
DQS_EN = GND
D0−D10
rpulldown
2.5
VDD = 1.7 V
VDD = 1.7 V,
6
pF
Ω
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
† All typical values are at VDD = 1.8 V (unless otherwise noted), TA = 25°C.
‡ VIK refers to the clamp voltage due to the internal diode, which is connected from each control input to GND.
§ For the leakage current test on S0 and S1, EN and TC inputs are set to low.
¶ For I/O ports, the parameter IOZ includes the input leakage current. IOZ applies only to the H port.
# The frequency of S0 and S1 inputs, for example, for a data I/O rate of 533 Mbit/s, with a burst of 4, the required frequency is for S0 or S1 input
is ≅ 66 MHz (533/8). The total ICC due to switching S0, S1 will be approximately 27 mA (66 MHz × 0.4 mA/MHz).
|| Measured by the voltage drop between the D and H terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (D or H) terminals.
k ∆r (flat) is the difference of maximum r and minimum r for a specific channel in a specific device.
on
on
on
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7
SCDS192 − APRIL 2005
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
D or H port
fmax
TA = 0 °C TO 85 °C
MIN
TYP
MAX
MHz
84
H or D
D or H
S
D
750
2100
ps
S
D
750
2100
ps
tosk
85
ps
tesk
40
ps
ten (tPZL, tPZH)‡
tdis (tPLZ, tPHZ)‡
297
tstart§
20
† EN = GND, TC = GND
‡ VBIAS = open
§ tstart is the time required for the charge-pump circuit output voltage to reach a steady state value after VDD is applied.
8
UNIT
334
S port†
tpd
TA = 70 °C
MIN
MAX
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ps
µs
SCDS192 − APRIL 2005
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
VDD
ZO = 40 Ω
VIN
50 Ω
VG1
TEST CIRCUIT
DUT
ZO = 40 Ω
ZO = 40 Ω
VI
T1†
RL
VO
VDD
2 y VDD
GND
120 Ω
VG2
CL
(see Note A)
RL
TEST
VDD
T1†
RL
VI
CL
V∆
tPLZ/tPZL
1.8 V ± 0.1 V
2 y VDD
1 kΩ
GND
6 pF
0.125 V
tPHZ/tPZH
1.8 V ± 0.1 V
GND
1 kΩ
VDD
6 pF
0.125 V
Output
Control
(VIN)
(see Note B)
VREF+0.25 V
VREF
VREF
VREF −0.25 V
tPZL
Output
Waveform 1 (VO)
T1† at 2 y VDD
(see Note C)
tPLZ
VOH
0.5 VDD
tPZH
Output
Waveform 2 (VO)
T1† at GND
(see Note C)
VOL + V∆
VOL
tPHZ
0.5 VDD
VOH − V∆
VOH
VOL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
† T1 is an external terminal.
NOTES: A. CL includes probe and jig capacitance.
B. Output control applies to select (S0, S1) inputs.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. All input pulses are supplied by generators having the following characteristics: ZOS = 50 Ω,rising and falling edge rate is 1 V/ns.
E. The outputs are measured one at a time, with one transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
Figure 1. Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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9
SCDS192 − APRIL 2005
PARAMETER MEASUREMENT INFORMATION
(Skew and Propagation Delay Times)
VDD
ZO = 40 Ω
VIN
50 Ω
VG1
TEST CIRCUIT
DUT
ZO = 40 Ω
ZO = 40 Ω
VI
RL
VO
T1†
VDD
2 y VDD
GND
120 Ω
VG2
CL
(see Note A)
RL
TEST
VDD
T1†
RL
VI
CL
tpd
1.8 V ± 0.1 V
VDD
150 Ω
see Waveform
6 pF
tosk
1.8 V ± 0.1 V
VDD
150 Ω
see Waveform
6 pF
tesk
1.8 V ± 0.1 V
VDD
150 Ω
see Waveform
6 pF
† T1 is an external terminal.
VREF
+0.35 V
Input
(H or D)
Output 1
(D or H)
VREF
−0.35 V
VOH
50%
50%
VOL
VREF
+0.35 V
50%
Input
(H or D)
VREF
−0.35 V
tPHL
tPLH
Skew
VOH
VOH
Output 2
(D or H)
VOL
50%
Output
(D or H)
VOL
CL includes probe and jig capacitance.
tosk is the difference in output voltage from channel to channel in a specific device.
tPLH and tPHL are the same as tpd and tesk = |tPLH − tPHL|
All input pulses are supplied by generators having the following characteristics: ZOS = 50 Ω,rising and falling edge rate is 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
Figure 2. Test Circuit and Voltage Waveforms
10
50%
VOLTAGE WAVEFORMS
(tesk and tpd) (see Note C)
SKEW BETWEEN ANY TWO OUTPUTS
(tosk) (see Note B)
NOTES: A.
B.
C.
D.
E.
50%
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SCDS192 − APRIL 2005
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11
PACKAGE OPTION ADDENDUM
www.ti.com
13-Mar-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74CBTU4411GSTR
PREVIEW
NFBGA
GST
72
2000
TBD
Call TI
SN74CBTU4411ZSTR
ACTIVE
NFBGA
ZST
72
2000
Pb-Free
(RoHS)
SNAGCU
Lead/Ball Finish
MSL Peak Temp (3)
Call TI
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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