Philips Semiconductors Product specification PowerMOS transistor GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope suitable for surface mounting featuring high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance. Intended for use in Switched Mode Power Supplies (SMPS) and general purpose switching applications. PINNING - SOT223 PIN BUK482-200A QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance PIN CONFIGURATION DESCRIPTION 1 gate 2 drain 3 source 4 drain (tab) MAX. UNIT 200 2.0 8.3 0.9 V A W Ω SYMBOL d 4 g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDS VDGR ±VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) IDM Drain current (pulse peak value) Source-drain diode current (DC) Source-drain diode current (pulse peak value) Total power dissipation Storage temperature Junction Temperature IDR IDRM Ptot Tstg Tj CONDITIONS MIN. MAX. UNIT Tsp = 25 ˚C Tsp = 100 ˚C Tsp = 25 ˚C - 200 200 30 2.0 1.3 8.0 V V V A A A Tsp = 25 ˚C - 2.0 A Tsp = 25 ˚C - 8.0 A Tsp = 25 ˚C -55 - 8.3 150 150 W ˚C ˚C MIN. MAX. UNIT - 50 8 mJ mJ RGS = 20 kΩ AVALANCHE LIMITING VALUE SYMBOL PARAMETER WDSS CONDITIONS Drain-source non-repetitive ID = 2 A ; VDD ≤ 50 V ; VGS = 10 V ; unclamped inductive turn-off RGS = 50 Ω energy Tj = 25˚C prior to surge Tj = 100˚C prior to surge January 1998 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor BUK482-200A THERMAL RESISTANCES SYMBOL PARAMETER Rth j-sp Thermal resistance junction to solder point Thermal resistance junction to ambient Rth j-a CONDITIONS pcb mounted; minimum footprint pcb mounted; pad area as in fig:17 MIN. TYP. MAX. UNIT - - 15 K/W - 156 70 - K/W K/W STATIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current VGS = 0 V; ID = 0.25 mA 200 - - V VDS = VGS; ID = 0.25 mA VDS = 200 V; VGS = 0 V; Tj = 25 ˚C VDS = 200 V; VGS = 0 V; Tj = 125 ˚C VGS = ±30 V; VDS = 0 V VGS = 10 V; ID = 2 A 2.0 - 3.0 0.1 0.1 10 0.53 4.0 10 1.0 100 0.9 V µA mA nA Ω - 0.87 1.0 V MIN. TYP. MAX. UNIT 0.5 2.6 - S VGS(TO) IDSS IGSS RDS(ON) VSD Gate source leakage current Drain-source on-state resistance Source-drain diode forward voltage IF = 2 A ;VGS = 0 V DYNAMIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 2 A Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 305 60 24 400 100 50 pF pF pF Qg(tot) Qgs Qgd Total gate charge Gate to source charge Gate to drain (Miller) charge VGS = 10 V; ID = 2 A; VDS = 160 V - 13 2 5 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 2.75 A; VGS = 10 V; RGS = 50 Ω; RGEN = 50 Ω - 10 30 30 20 15 45 40 30 ns ns ns ns trr Source-drain diode reverse recovery time Source-drain diode reverse recovery charge IF = 2 A; -dIF/dt = 100 A/µs; - 88 - ns VGS = 0 V; VR = 100 V - 370 - nC Qrr January 1998 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor 120 BUK482-200A Normalised Power Derating PD% 10 BUK482-200A ID / A ID 110 ) ON 100 = / DS tp = 10 us V S( RD 90 80 100 us 1 1 ms 70 60 10 ms 50 40 0.1 100 ms 30 DC 20 10 0 0 20 40 60 80 Tamb / C 100 120 0.01 140 100 1000 Fig.4. Safe operating area. Tamb = 25 ˚C. ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% 10 VDS / V Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tamb) 120 1 10 BUK482-200A ID / A VGS = 20 V 110 10 100 8 90 6.5 80 6 70 6 60 50 4 5.5 40 30 5 2 20 4.5 4 10 0 0 20 40 60 80 Tamb / C 100 120 0 140 4 2 10 1.5 1 1 8 10 tp D= BUK482-200A RDS(ON) / Ohms VGS = 5V PD 6 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS BUK482-200A Zth(j-sp) K/W 2 VDS / V Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tamb); conditions: VGS ≥ 10 V 100 0 5.5 V 6.5 V 6V 10 V tp 20 V T 0.1 0.5 t T 0.01 1us 10us 100us 1ms 10ms tp / sec 100ms 1s 0 10s Fig.3. Transient thermal impedance. Zth j-sp = f(t); parameter D = tp/T January 1998 0 1 2 3 4 ID / A 5 6 7 8 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor 8 BUK482-200A VGS(TO) / V BUK482-200A ID / A max. 4 7 6 typ. 3 5 min. 4 2 3 25 C Tj = 150 C 2 1 1 0 0 0 2 4 6 8 -60 10 -40 -20 0 VGS / V BUK482-200A gfs / S 40 60 Tj / C 80 100 120 140 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj 5 20 1E-01 SUB-THRESHOLD CONDUCTION ID / A 1E-02 4 Tj = 25 C typ 98 % 150 C 2 1E-04 1 1E-05 0 2% 1E-03 3 1E-06 0 1 2 3 4 ID / A 5 6 7 0 8 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V 2.4 2.2 2.0 1.8 1.6 1.4 2 VGS / V 3 4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) a 1 1000 BUK482-200A C / pF Ciss 100 Coss 1.2 1.0 0.8 0.6 0.4 0.2 Crss 10 0 -60 -40 -20 0 20 40 60 Tj / C 80 1 100 120 140 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 2 A; VGS = 10 V January 1998 0 50 100 VDS / V 150 200 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor 15 BUK482-200A BUK482-200A VGS / V 120 VDS = 40 V WDSS% Normalised Avalanche Energy 110 160 V 100 90 80 10 70 60 50 40 30 20 5 10 0 0 0 5 10 Qg / nC 15 20 20 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 2 A; parameter VDS 8 40 60 80 100 Tamb/ C 120 140 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tamb); conditions: ID = 2 A BUK482-200A IF / A VDD + 7 L 6 VDS 5 - VGS 4 Tj = 150 C -ID/100 25 C 3 T.U.T. 0 2 RGS 1 0 0 0.5 VSDS / V 1 1.5 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj January 1998 R 01 shunt 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor BUK482-200A PRINTED CIRCUIT BOARD Dimensions in mm. 36 18 60 4.5 4.6 9 10 7 15 50 Fig.17. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick). January 1998 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor BUK482-200A MECHANICAL DATA Dimensions in mm 6.7 6.3 Net Mass: 0.11 g B 3.1 2.9 0.32 0.24 0.2 4 A A 0.10 0.02 16 max M 7.3 6.7 3.7 3.3 13 2 1 10 max 1.8 max 1.05 0.80 2.3 0.60 0.85 4.6 3 0.1 M B (4x) Fig.18. SOT223 surface mounting package. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to surface mounting instructions for SOT223 envelope. 3. Epoxy meets UL94 V0 at 1/8". January 1998 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor BUK482-200A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1998 8 Rev 1.000