Philips Semiconductors Product specification TrenchMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. The device features very low on-state resistance and has integral zener diodes giving ESD protection. It is intended for use in DC-DC converters and general purpose switching applications. QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Drain-source voltage Drain current (DC) Tsp = 25 ˚C Drain current (DC) Tamb = 25 ˚C Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V Ptot Tj RDS(ON) PINNING - SOT223 PIN PHT6N06LT PIN CONFIGURATION MAX. UNIT 55 5.5 2.5 8.3 150 150 V A A W ˚C mΩ SYMBOL DESCRIPTION d 4 1 gate 2 drain 3 source 4 drain (tab) g 2 1 s 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) ID Drain current (DC) IDM Drain current (pulse peak value) Ptot Total power dissipation Tstg, Tj Storage & operating temperature RGS = 20 kΩ Tsp = 25 ˚C Tamb = 25 ˚C Tsp = 100 ˚C Tamb = 100 ˚C Tsp = 25 ˚C Tamb = 25 ˚C Tsp = 25 ˚C Tamb = 25 ˚C - - 55 55 55 ±13 5.5 2.5 3.8 1.75 22 10 8.3 1.8 150 V V V A A A A A A W W ˚C MIN. MAX. UNIT - 2 kV ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage Human body model (100 pF, 1.5 kΩ) January 1998 1 Rev 1.100 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N06LT THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-sp Rth j-amb From junction to solder point From junction to ambient Mounted on any PCB Mounted on PCB of Fig.17 TYP. MAX. UNIT 12 - 15 70 K/W K/W STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage VGS = 0 V; ID = 0.25 mA VGS(TO) Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; IGSS Gate source leakage current VGS = ±5 V ±V(BR)GSS RDS(ON) Gate source breakdown voltage VGS = ±1 mA Drain-source on-state VGS = 5 V; ID = 5 A resistance Tj = 150˚C Tj = 150˚C Tj = 150˚C MIN. TYP. MAX. UNIT 55 50 1.0 0.6 10 - 1.5 0.05 0.02 120 - 2.0 2.3 10 100 1 5 150 277 V V V V V µA µA µA µA V mΩ mΩ MIN. TYP. MAX. UNIT DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 5 A; Tj = 25˚C 3 5 - S Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 5 A; VDD = 44 V; VGS = 5 V - 4.5 1 2.5 - nC nC nC Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 250 65 35 330 80 50 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 5 A; VGS = 5 V; RG = 10 Ω; - 11 38 25 20 17 60 38 38 ns ns ns ns MIN. TYP. MAX. UNIT Tj = 25˚C REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = -55 to 175˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR Tsp = 25˚C - - 5.5 A IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Tsp = 25˚C IF = 2 A; VGS = 0 V - 0.85 30 1.1 A V trr Qrr Reverse recovery time Reverse recovery charge IF = 2 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 43 0.16 - ns µC January 1998 2 Rev 1.100 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N06LT AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 1.9 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tsp = 25 ˚C January 1998 3 MIN. TYP. MAX. UNIT - - 15 mJ Rev 1.100 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 120 PHT6N06LT Normalised Power Derating PD% 1E+02 BUKX8150-55 Zth / (K/W) 110 3E+01 100 90 1E+01 0.5 80 70 3E+00 60 50 1E+00 0.2 0.1 0.05 40 3E-01 0.02 30 1E-01 20 10 3E-02 0 0 20 40 60 80 100 Tmb / C 120 D= t T 1E-05 1E-03 t/s tp T 1E-01 1E+01 Fig.4. Transient thermal impedance. Zth j-sp = f(t); parameter D = tp/T Normalised Current Derating ID% tp 0 1E-02 1E-07 140 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tsp) 120 PD 10 110 Drain current, ID (A) 10 4 VGS = 3.6 V 3.8 100 90 8 5 3.4 80 70 6 60 50 3.2 3.0 4 40 2.8 30 20 10 2 2.6 2.4 2.2 0 0 20 40 60 80 Tmb / C 100 120 0 140 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 5 V 0 2 4 6 8 Drain-source voltage, VDS (V) 10 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS 400 RDS(ON)mOhm BUKX8150-55 3 100 ID/A 350 tp = RDS(ON) = VDS/ID 10 300 1 us 10 us 3.2 250 100 us DC 1 3.4 200 3.6 1 ms 4 150 10 ms 5 100 100 ms 0.1 1 10 55 50 VDS/V Fig.3. Safe operating area. Tsp = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp January 1998 1 2 3 4 5 ID/A 6 7 8 9 10 11 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 4 Rev 1.100 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N06LT 10 2.5 ID/A VGS(TO) / V BUK98xx-55 max. 8 2 typ. 6 1.5 4 1 min. 0.5 2 Tj/C = 150 0 0 1 25 2 VGS/V 3 4 0 -100 5 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj 7 0 50 Tj / C 100 150 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) Sub-Threshold Conduction 1E-01 6 1E-02 5 1E-03 4 2% typ 98% 1E-04 3 1E-05 2 1 2 3 4 5 6 7 Drain current, ID (A) 8 9 10 1E-05 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V 2.5 -50 BUK98XX-55 a 0 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 600 Rds(on) normalised to 25degC 500 2 pF 400 300 1.5 Ciss 200 1 100 0.5 -100 -50 0 50 Tmb / degC 100 150 0 0.01 200 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5 A; VGS = 5 V January 1998 Coss Crss 0.1 1 VDS/V 10 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 5 Rev 1.100 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N06LT 6 120 110 VGS/V 5 WDSS% 100 90 4 VDS = 14V 80 VDS = 44V 70 60 3 50 40 2 30 20 1 10 0 0 0 1 2 QG/nC 3 4 20 5 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 5 A; parameter VDS 40 60 80 100 Tmb / C 120 140 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tsp); conditions: ID = 1.9 A 10 IF/A 8 L VDS 6 Tj/C = 150 25 - VGS -ID/100 4 T.U.T. 0 2 0 VDD + RGS 0 0.2 0.4 0.6 0.8 VSDS/V 1 1.2 1.4 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj January 1998 R 01 shunt 6 Rev 1.100 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N06LT PRINTED CIRCUIT BOARD Dimensions in mm. 36 18 60 4.5 4.6 9 10 7 15 50 Fig.17. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick). January 1998 7 Rev 1.100 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N06LT MECHANICAL DATA Dimensions in mm 6.7 6.3 Net Mass: 0.11 g B 3.1 2.9 0.32 0.24 0.2 4 A A 0.10 0.02 16 max M 7.3 6.7 3.7 3.3 13 2 1 10 max 1.8 max 1.05 0.80 2.3 0.60 0.85 4.6 3 0.1 M B (4x) Fig.18. SOT223 surface mounting package. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to surface mounting instructions for SOT223 envelope. 3. Epoxy meets UL94 V0 at 1/8". January 1998 8 Rev 1.100 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N06LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1998 9 Rev 1.100