INTEGRATED CIRCUITS SCC2681T Dual asynchronous receiver/transmitter (DUART) Product data 2004 Apr 06 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T • Programmable baud rate for each receiver and transmitter DESCRIPTION The Philips Semiconductors SCC2681 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip MOS-LSI communications device that provides two independent full-duplex asynchronous receiver/transmitter channels in a single package. The SCC2681T features a faster bus cycle time than the standard SCC2681. The quick bus cycle eliminates or reduces the need for wait states with fast CPUs and permits high throughput in I/O intensive systems. Higher external clock rates may be used with the transmitter, receiver and counter timer which in turn provide greater versatility in baud rate generation. The SCC2681T interfaces directly with microprocessors and may be used in a polled or interrupt driven system. It is manufactured in CMOS technology. selectable from: – 22 fixed rates: 50 to 115.2 k baud – Non-standard rates to 115.2 – Non-standard user-defined rate derived from programmable counter/timer – External 1× or 16× clock • Parity, framing, and overrun error detection • False start bit detection • Line break detection and generation • Programmable channel mode The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of eighteen fixed baud rates, a 16× clock derived from a programmable counter/timer, or an external 1× or 16× clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems. – Normal (full-duplex) – Automatic echo – Local loopback – Remote loopback • Multi-function programmable 16-bit counter/timer • Multi-function 7-bit input port – Can serve as clock or control inputs – Change of state detection on four inputs Each receiver is quadruple buffered to minimize the potential of receiver over-run or to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided to disable a remote DUART transmitter when the receiver buffer is full. – 100 kΩ typical pull-up resistors • Multi-function 8-bit output port – Individual bit set/reset capability Also provided on the SCC2681T are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control. – Outputs can be programmed to be status/interrupt/DMA signals – Auto 485 turn-around • Versatile interrupt system – Single interrupt output with eight maskable interrupting conditions For a complete functional description and programming information for the SCC2681T, refer to the SCC2681 product specification. – Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs • Maximum data transfer rates: FEATURES • Fast bus cycle times reduce or eliminate CPU wait states • Dual full-duplex asynchronous receiver/transmitters • Quadruple buffered receiver data registers • Programmable data format – 1× – 1 MB/sec transmitter and receiver – 16× – 500 kB/sec receiver and 250 kB/sec transmitter • Automatic wake-up mode for multidrop applications • Start-end break interrupt/status • Detects break which originates in the middle of a character • On-chip crystal oscillator • Single +5 V power supply • Commercial temperature range – 5 to 8 data bits plus parity – Odd, even, no parity or force parity – 1, 1.5 or 2 stop bits programmable in 1/16-bit increments • 16-bit programmable Counter/Timer ORDERING INFORMATION VCC = +5 V ± 10%, Tamb = 0 °C to +70 °C DESCRIPTION 44-Pin Plastic Lead Chip Carrier (PLCC) NOTE: For a full register description and programming information see the SCC2681. 2004 Apr 06 2 SCC2681TC1A44 DWG # SOT187-2 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T BLOCK DIAGRAM 8 D0–D7 CHANNEL A BUS BUFFER TRANSMIT HOLDING REG TxDA TRANSMIT SHIFT REGISTER RDN OPERATION CONTROL WRN ADDRESS DECODE CEN A0–A3 RESET RECEIVE HOLDING REG (3) RxDA 4 RECEIVE SHIFT REGISTER R/W CONTROL MRA1, 2 CRA SRA INTERRUPT CONTROL INTRN IMR INTERNAL DATABUS TIMING BAUD RATE GENERATOR RxDB CONTROL TIMING TxDB CHANNEL B (AS ABOVE) ISR INPUT PORT CHANGE OF STATE DETECTORS (4) 7 IP0-IP6 IPCR ACR CLOCK SELECTORS COUNTER/ TIMER OUTPUT PORT FUNCTION SELECT LOGIC X1/CLK XTAL OSC 8 OP0-OP7 OPCR X2 OPR CSRA CSRB ACR U CTLR CTLR VCC GND SD00099 Figure 1. Block Diagram NOTE: Refer to SCC2681 for functional description. 2004 Apr 06 3 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T CEN RESET X2 X1/CLK RxDA n.c. TxDA OP0 OP2 OP4 OP6 39 38 37 36 35 34 33 32 31 30 29 PIN CONFIGURATION IP2 40 28 D0 IP6 41 27 D2 IP5 42 26 D4 IP4 43 25 D6 24 INTRN VCC 44 SCC2681TC1A44 14 15 16 17 OP1 OP3 OP5 OP7 D1 13 D3 18 TxDB 19 6 11 5 A2 12 IP1 n.c. D5 RxDB D7 20 9 21 4 10 3 A1 RDN IP3 WRN GND 8 n.c. 22 7 23 2 A3 1 A0 IP0 n.c. SD00737 Figure 2. Pin configuration PIN DESCRIPTION MNEMONIC PIN TYPE D0–D7 21, 25, 20, 26, 19, 27, 18, 28 I/O Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. NAME AND FUNCTION CEN 39 I Chip Enable: Active LOW input signal. When LOW, data transfers between the CPU and the DUART are enabled on D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is HIGH, the DUART places the D0–D7 lines in the three-state condition. WRN 9 I Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. RDN 10 I Read Strobe: When low and CEN is also LOW, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RDN. A0–A3 2, 4, 6, 7 I Address Inputs: Select the DUART internal registers and ports for read/write operations. RESET 38 I Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the HIGH state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Clears Test modes, sets MR pointer to MR1. INTRN 24 O Interrupt Request: Active-LOW, open-drain output which signals the CPU that one or more of the eight maskable interrupting conditions are true. X1/CLK 36 I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing. X2 37 I Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected. It must not be grounded. RxDA 35 I Channel A Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’ is LOW. RxDB 11 I Channel B Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’ is LOW. 2004 Apr 06 4 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T MNEMONIC PIN TYPE NAME AND FUNCTION TxDA 33 O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is HIGH, ‘space’ is LOW. TxDB 13 O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is HIGH, ‘space’ is LOW. OP0 32 O Output 0: General purpose output, or channel A request to send (RTSAN, active-LOW). Can be deactivated automatically on receive or transmit. OP1 14 O Output 1: General purpose output, or channel B request to send (RTSBN, active-LOW). Can be deactivated automatically on receive or transmit. OP2 31 O Output 2: General purpose output, or channel A transmitter 1× or 16× clock output, or channel A receiver 1× clock output. OP3 15 O Output 3: General purpose output, or open-drain, active-LOW counter/timer interrupt output, or channel B transmitter 1× clock output, or channel B receiver 1× clock output. OP4 30 O Output 4: General purpose output, or channel A open-drain, active-LOW, RxRDYA/FFULLA interrupt output. OP5 16 O Output 5: General purpose output, or channel B open-drain, active-LOW, RxRDYB/FFULLB interrupt output. OP6 29 O Output 6: General purpose output, or channel A open-drain, active-LOW, TxRDYA interrupt output. OP7 17 O Output 7: General purpose output, or channel B open-drain, active-LOW TxRDYB interrupt output. IP0 8 I Input 0: General purpose input, or channel A clear to send active-LOW input (CTSAN). Pin has an internal VCC pull-up device supplying 1 to 4 µA of current. IP1 5 I Input 1: General purpose input, or channel B clear to send active-LOW input (CTSBN). Pin has an internal VCC pull-up device supplying 1 to 4 µA of current. IP2 40 I Input 2: General purpose input, or counter/timer external clock input. Pin has an internal VCC pull-up device supplying 1 to 4 µA of current. IP3 3 I Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 µA of current. IP4 43 I Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 µA of current. IP5 42 I Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 µA of current. IP6 41 I Input 6: General purpose input, or channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 µA of current. VCC 44 I Power Supply: +5 V supply input. GND 22 I Ground n.c. 1, 12, 23, 34 2004 Apr 06 not connected 5 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T ABSOLUTE MAXIMUM RATINGS1 PARAMETER SYMBOL RATING UNIT Tamb Operating ambient temperature 0 to +70 °C Tstg Storage temperature range –65 to +150 °C All voltages with respect to GND3 –0.5 to +6.0 V VSS – 0.5 to VCC + 0.5 V range2 Pin voltage range NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150 °C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 2004 Apr 06 6 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T DC ELECTRICAL CHARACTERISTICS1, 2, 3 Tamb = 0 °C to +70 °C; VCC = +5.0 V ± 10% SYMBOL PARAMETER VIL VIH VIH VIH LOW-level input voltage HIGH-level input voltage (except X1/CLK) HIGH-level input voltage (except X1/CLK) HIGH-level input voltage (X1/CLK) VOL LOW-level output voltage VOH HIGH-level output voltage (except open-drain outputs)4 IIX1 IILX1 IIHX1 X1/CLK input current X1/CLK input LOW current – operating X1/CLK input HIGH current – operating IOHX2 IOHX2S IOLX2 IOLX2S X2 output HIGH current – operating X2 output HIGH short circuit current – operating X2 output LOW current – operating X2 output LOW short circuit current – operating II Input leakage current: All except input port pins Input port pins IOZH IOZL TEST CONDITIONS Tamb ≥ 0 °C Tamb < 0 °C LIMITS UNIT Min Typ Max – 2.0 2.5 0.8 VCC – – – – 0.8 – – – V V V V IOL = 2.4 mA – – 0.4 V IOH = –400 µA VCC – 0.5 – – V VIN = 0 V to VCC VIN = 0 V VIN = VCC –10 –75 0 – – – +10 0 75 µA µA µA VOUT = VCC; X1 = 0 VOUT = 0 V; X1 = 0 VOUT = 0 V; X1 = VCC VOUT = VCC; X1 = VCC 0 –10 –75 1 – – – – +75 –1 0 10 µA mA µA mA VIN = 0 V to VCC VIN = 0 V to VCC –10 –20 – – +10 +10 µA µA Output off current HIGH, 3-state data bus Output off current LOW, 3-state data bus VIN = VCC VIN = 0 V – –10 – – 10 – µA µA IODL IODH Open-drain output LOW current in off-state Open-drain output HIGH current in off-state VIN = 0 V VIN = VCC –10 – – – – 10 µA µA ICC Power supply current5 Operating mode CMOS input levels – 10 mA – NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate. 3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters. 4. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7 kΩ to VCC. 5. All outputs are disconnected. Inputs are switching between CMOS levels of VCC – 0.2 V and VSS + 0.2 V. 2004 Apr 06 7 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4 SYMBOL LIMITS PARAMETER UNIT Min Typ Max 1.0 – – µs 0 100 120 110 15 – 10 – 75 35 15 – – – – – – – – – – – – – – – – 100 – 65 – – – ns ns ns ns ns ns ns ns ns ns ns 0 0 – – – – – – 200 ns ns ns – – – – – – – – – – – – 200 200 200 200 200 200 ns ns ns ns ns ns Reset timing (see Figure 3) tRES Reset pulse width Bus timing (see Figure 4) (Note 5) tAVEL tELAX tRLRH tEHEL tRLDA tRLDV tRHDI tRHDF tWLWH tDVWH tWHDI A0–A3 set-up to RDN and CEN, or WRN and CEN LOW RDN and CEN, or WRN and CEN LOW to A0–A3 invalid RDN and CEN LOW to RDN or CEN HIGH CEN HIGH to CEN LOW6, 7 CEN and RDN LOW to data outputs active CEN and RDN LOW to data valid CEN or RDN HIGH to data invalid CEN or RDN HIGH to data outputs floating WRN and CEN LOW to WRN or CEN HIGH Data input valid to WRN or CEN HIGH WRN or CEN HIGH to data invalid Port timing (see Figure 5) tPS tPH tPD Port input set-up time before RDN LOW Port input hold time after RDN HIGH Port output valid after WRN HIGH Interrupt timing (see Figure 6) tIR INTRN (or OP3–OP7 when used as interrupts) negated from: Read RHR (RxRDY/FFULL interrupt) Write THR (TxRDY interrupt) Reset command (delta break interrupt) Stop C/T command (counter interrupt) Read IPCR (input port change interrupt) Write IMR (clear of interrupt mask bit) Clock timing (see Figure 7) tCLK X1/CLK HIGH or LOW time fCLK X1/CLK frequency 2 tCTC CTCLK (IP2) HIGH or LOW time 55 fCTC CTCLK (IP2) frequency8 0 tRX RxC HIGH or LOW time 55 fRX RxC frequency 90 (16×)8 0 (1×)8 0 tTX TxC HIGH or LOW time fTX TxC frequency ns 4 MHz 8 MHz 8 MHz 1 MHz ns ns 3.6864 110 ns (16×)8 0 4 MHz (1×)8 0 1 MHz Transmit timing (see Figure 8) tTXD TxD output delay from TxC external clock input on IP pin – – 300 ns tTCS Output delay from TxC LOW at OP pin to TxD data output 0 – 100 ns Receive timing (see Figure ) tRXS RxD data set-up time before RxC HIGH at external clock input on IP pin 200 – – ns tRXH RxD data hold time after RxC HIGH at external clock input on IP pin 25 – – ns NOTES: 1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC supply range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a transition time of 20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.0 V. All time measurements are referenced at input voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V as appropriate. 3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters. 2004 Apr 06 8 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T 4. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7 kΩ to VCC. 5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must be negated for tEHEL to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the RDN input even if the CEN is used as the strobing signal for bus operations. 7. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes. 8. Minimum frequencies are not tested but are guaranteed by design. RESET tRES SD00028 Figure 3. Reset Timing A0–A3 tAVEL tELAX CEN (READ) tEHEL tRLRH RDN tRHDF tRLDV tRHDI tRLDA D0–D7 (READ) FLOAT INVALID VALID FLOAT CEN (WRITE) tEHEL tWLWH WRN tDVWH tWHDI D0–D7 (WRITE) VALID SD00100 Figure 4. Bus Timing 2004 Apr 06 9 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T RDN tPH tPS IP0–IP6 (a) INPUT PINS WRN tPD OP0–OP7 OLD DATA NEW DATA (b) OUTPUT PINS SD00101 Figure 5. Port Timing VM WRN tIR INTERRUPT 1 OUTPUT VOL +0.5V VOL NOTES: 1. INTRN or OP3-OP7 when used as interrupt outputs. 2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement. SD00102 Figure 6. Interrupt Timing 2004 Apr 06 10 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T tCLK tCTC tRx tTx +5 V R1 1 kΩ X1/CLK CTCLK RxC TxC X1 U1 tCLK tCTC tRx tTx RESISTOR REQUIRED WHEN U1 IS A TTL DEVICE NC X2 SCC2681T C1 = C2 = 24 pF FOR CL = 20 pF X1 3 pF 50 TO 150 kΩ 3.6864 MHz X2 TO INTERNAL CLOCK DRIVERS 4 pF NOTE: C1 AND C2 SHOULD BE BASED ON MANUFACTURER’S SPECIFICATION. PARASITIC CAPACITANCE SHOULD BE INCLUDED WITH C1 AND C2. R1 IS ONLY REQUIRED IF U1 WILL NOT DRIVE TO X1 INPUT LEVELS TYPICAL CRYSTAL SPECIFICATION FREQUENCY: 2 – 4 MHz 12 – 32 pF LOAD CAPACITANCE (CL): TYPE OF OPERATION: PARALLEL RESONANT, FUNDAMENTAL MODE SD00726 Figure 7. Clock Timing 1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT) tTXD TxD tTCS TxC (1X OUTPUT) SD00103 Figure 8. Transmit RxC (1X INPUT) tRXS tRXH RxD SD00104 2004 Apr 06 11 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T Figure 9. Receive TxD D1 D2 D3 BREAK D4 D6 TRANSMITTER ENABLED TxRDY (SR2) WRN D1 D2 D3 START BREAK D4 STOP BREAK D5 WILL NOT BE TRANSMITTED CTSN1 D6 (IP0) RTSN2 (OP0) OPR(0) = 1 OPR(0) = 1 NOTES: 1. Timing shown for MR2(4) = 1. 2. Timing shown for MR2(5) = 1. SD00094 Figure 10. Transmitter Timing D1 RxD D2 D3 D4 D5 D6 D7 D8 D6, D7, D8 WILL BE LOST RECEIVER ENABLED RxRDY (SR0) FFULL (SR1) RxRDY/ FFULL (OP5)2 RDN S D S = STATUS D = DATA S D1 D D2 OVERRUN (SR4) D5 WILL BE LOST S D S D D3 D4 RESET BY COMMAND RTS1 (OP0) OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1. 2. Shown for OPCR(4) = 1 and MR1(6) = 0. SD00105 Figure 11. Receiver Timing 2004 Apr 06 12 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) MASTER STATION BIT 9 ADD#1 1 TxD BIT 9 BIT 9 D0 SCC2681T ADD#2 1 0 TRANSMITTER ENABLED TxRDY (SR2) WRN MR1(4–3) = 11 MR1(2) = 1 ADD#1 MR1(2) = 0 D0 MR1(2) = 1 ADD#2 PERIPHERAL STATION BIT 9 RxD 0 BIT 9 ADD#1 1 BIT 9 BIT 9 D0 BIT 9 ADD#2 1 0 0 RECEIVER ENABLED RxRDY (SR0) RDN/WRN MR1(4–3) = 11 S D S = STATUS D = DATA S D ADD#1 D0 ADD#2 SD00106 Figure 12. Wake-Up Mode 2004 Apr 06 13 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 2004 Apr 06 SCC2681T SOT187-2 14 Philips Semiconductors Product data Dual asynchronous receiver/transmitter (DUART) SCC2681T REVISION HISTORY Rev Date Description _1 20040406 Product data (9397 750 12073). ECN 853-2446 01-A15014 of 15 December 2003. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 04-04 For sales offices addresses send e-mail to: [email protected]. Document order number: 2004 Apr 06 15 9397 750 12073