PCF8534A Universal LCD driver for low multiplex rates Rev. 03 — 10 November 2008 Product data sheet 1. General description The PCF8534A is a peripheral device which interfaces to almost any LCD with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 60 segments. In addition, the PCF8534A can be easily cascaded for larger LCD applications. The PCF8534A is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized using display RAM with auto-incremented addressing, hardware subaddressing and display memory switching (static and duplex drive modes). The PCF8534A complies with AEC-Q100 (automotive). 2. Features n Single-chip LCD controller and driver n Selectable backplane drive configurations: static or 2, 3 or 4 backplane multiplexing n 60 segment drives: u 30 8-segment numeric characters u 16 15-segment alphanumeric characters u Any graphics of up to 240 elements n Cascading supported for larger applications n 60 × 4-bit display data storage RAM n Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for guest-host LCDs and high threshold (automobile) twisted nematic LCDs n Internal LCD bias generation with voltage follower buffers n Selectable display bias configurations: static, 1⁄2 or 1⁄3 n Wide logic power supply range: from 1.8 V to 5.5 V n LCD and logic supplies may be separated n Low power consumption n 400 kHz I2C-bus interface n Compatible with any microprocessors or microcontrollers n No external components n Display memory bank switching in static and duplex drive modes n Auto-incremented display data loading n Versatile blinking modes n Silicon gate CMOS process PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Type number Package Name Description Delivery form Version PCF8534AH/1 LQFP80 plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm tape and reel SOT315-1 PCF8534AU/DA/1 PCF8534AU wire bond die; 76 bonding pads; 2.91 × 2.62 × 0.38 mm chip in tray PCF8534AU 4. Marking Table 2. Marking codes Type number Marking code PCF8534AH/1 PCF8534AH PCF8534AU/DA/1 PC8534A-1 5. Block diagram S0 to S59 BP0 BP1 BP2 BP3 60 VLCD BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY SEGMENT OUTPUTS DISPLAY REGISTER OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY CONTROL LCD BIAS GENERATOR VSS PCF8534A CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE OSC OSCILLATOR POWER-ON RESET SCL INPUT FILTERS SDA COMMAND DECODE WRITE DATA CONTROL I2C-BUS CONTROLLER SA0 Fig 1. DISPLAY RAM DATA POINTER AND AUTO INCREMENT SUBADDRESS COUNTER VDD A0 A1 A2 001aah614 Block diagram of PCF8534A PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 2 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 6. Pinning information 61 S11 62 S12 63 S13 64 S14 65 S15 66 S16 67 S17 68 S18 69 S19 70 S20 71 S21 72 S22 73 S23 74 S24 75 S25 76 S26 77 S27 78 S28 79 S29 80 S30 6.1 Pinning S31 1 60 S10 S32 2 59 S9 S33 3 58 S8 S34 4 57 S7 S35 5 56 S6 S36 6 55 S5 S37 7 54 S4 S38 8 53 S3 S39 9 52 S2 S40 10 51 S1 PCF8534AH S41 11 50 S0 CLK 40 SCL 39 SDA 38 n.c. 37 n.c. 36 n.c. 35 n.c. 34 BP3 33 BP2 32 BP1 31 BP0 30 41 VDD S59 29 42 SYNC S50 20 S58 28 43 OSC S49 19 S57 27 44 A0 S48 18 S56 26 45 A1 S47 17 S55 25 46 A2 S46 16 S54 24 47 SA0 S45 15 S53 23 48 VSS S44 14 S52 22 49 VLCD S43 13 S51 21 S42 12 001aag092 Top view. For mechanical details, see Figure 23. Fig 2. PCF8534AH/1 pin configuration (SOT315-1) PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 3 of 44 PCF8534A NXP Semiconductors S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 11 12 13 14 15 16 17 18 19 20 21 22 23 VSS VLCD S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 9 10 A2 SA0 F 8 3 7 CLK A1 2 A0 SCL 6 1 5 SDA OSC 70 71 72 73 74 75 76 SYNC S57 S58 S59 BP0 BP1 BP2 BP3 C2 PCF8534A-1 4 64 65 66 67 68 69 VDD S51 S52 S53 S54 S55 S56 S50 S49 S48 S47 S46 C1 63 62 61 60 59 Universal LCD driver for low multiplex rates Top view 43 42 41 40 39 38 37 S30 S29 S28 S27 S26 S25 S24 36 35 34 33 32 31 30 29 28 27 26 25 24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 001aai648 For mechanical details, see Figure 24. Fig 3. PCF8534AU/DA/1 pin configuration (bare die) PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 4 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 6.2 Pin description Table 3. Pin description Symbol Pin S31 to S59 Description SOT315 Bare die 1 to 29 44 to 72 LCD segment output 31 to 59 BP0 to BP3 30 to 33 73 to 76 LCD backplane output 0 to 3 n.c. 34 to 37 - not connected SDA 38 1 I2C-bus serial data input and output SCL 39 2 I2C-bus serial clock input CLK 40 3 external clock input and output VDD 41 4 supply voltage SYNC 42 5 cascade synchronization input and output (active LOW) OSC 43 6 enable input for internal oscillator A0 to A2 44 to 46 7 to 9 subaddress counter input 0 to 2 SA0 47 10 I2C-bus slave address input 0 VSS 48 11[1] ground VLCD 49 12 input of LCD supply voltage S0 to S30 50 to 80 13 to 43 LCD segment output 0 to 30 [1] The substrate (rear side of the die) is wired to VSS but should not be electrically connected. 7. Functional description The PCF8534A is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 60 segments. The display configurations possible with the PCF8534A depend on the number of active backplane outputs required. Display configuration selection is shown in Table 4. All of the display configurations can be implemented in the typical system shown in Figure 4. Table 4. Selection of display configurations Backplanes Segments 7-segment numeric 14-segment numeric Digits Indicator symbols Characters Indicator symbols 4 240 30 30 16 16 240 (4 × 60) 3 180 22 26 12 12 180 (3 × 60) 2 120 15 15 8 8 120 (2 × 60) 1 60 7 11 4 4 60 (1 × 60) PCF8534A_3 Product data sheet Dot matrix © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 5 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates VDD R≤ tr 2Cb HOST MICROPROCESSOR/ MICROCONTROLLER VDD VLCD 60 segment drives SDA LCD PANEL SCL PCF8534A 4 backplanes OSC A0 A1 A2 (up to 240 elements) SA0 VSS 001aah616 VSS Fig 4. Typical system configuration The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF8534A. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application. 7.1 Power-on reset At power-on the PCF8534A resets to a default starting condition: • • • • • • • • All backplane outputs are set to VLCD All segment outputs are set to VLCD The selected drive mode is: 1:4 multiplex with 1⁄3 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) The display is disabled Do not transfer data on the I2C-bus after a power-on for 1 ms to enable the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider comprising three series resistors connected between pins VLCD and VSS. The center resistor is switched out of the circuit to provide the 1⁄2 bias voltage level for the 1:2 multiplex configuration. 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD based on the selected LCD drive configuration. The operation of the voltage selector is controlled by mode set commands from the command decoder. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 6 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 5 shows the biasing configurations applicable to the preferred operating modes together with the biasing characteristics as functions of Voper and the resulting discrimination ratios (D). A practical value for Voper is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is Voper > 3Vth. Multiplex drive ratios of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller e.g.: 21 3 = 1.732 for 1:3 multiplex or ---------- = 1.528 for 1:4 multiplex 3 The advantage of these modes is the reduction of the LCD full-scale voltage Voper as follows: • 1:3 multiplex (1⁄2 bias): V oper = 6 × V off ( RMS ) = 2.449V off ( RMS ) 4 × 3) - = 2.309V off ( RMS ) • 1:4 multiplex (1⁄2 bias): V oper = (-------------------3 These compare with Voper = 3Voff(RMS) when 1⁄3 bias is used. It should be noted that Voper = VLCD. Table 5. Preferred LCD drive modes: summary of characteristics LCD drive Number of mode Backplanes Levels static 1:2 1:2 1 2 2 LCD bias V off ( RMS ) configuration ----------------------V oper V on ( RMS ) ----------------------V oper V on ( RMS ) D = ----------------------V off ( RMS ) 2 static 0 1 ∞ 3 1⁄ 2 0.354 0.791 2.234 4 1⁄ 3 0.333 0.745 2.237 0.333 0.638 1.915 0.333 0.577 1.732 1:3 3 4 1⁄ 3 1:4 4 4 1⁄ 3 PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 7 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 5. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. mgl745 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn + 1)(t) − VBP0(t). Voff(RMS) = 0 V. Fig 5. Static drive mode waveforms PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 8 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8534A allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 6 and Figure 7. Tfr VLCD BP0 LCD segments VLCD / 2 VSS state 1 VLCD BP1 state 2 VLCD / 2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V −VLCD / 2 −VLCD VLCD VLCD / 2 state 2 0V −VLCD / 2 −VLCD (b) Resultant waveforms at LCD segment. mgl746 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.354VLCD. Fig 6. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 9 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Tfr VLCD BP0 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD BP1 state 2 2VLCD / 3 VLCD / 3 VSS VLCD Sn Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl747 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 7. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 10 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 8. Tfr VLCD BP0 BP1 BP2 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD 2VLCD / 3 state 2 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl748 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 8. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 11 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 9. Tfr VLCD BP0 BP1 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD 2VLCD / 3 state 2 VLCD / 3 VSS VLCD BP2 BP3 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS VLCD Sn+3 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl749 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 9. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 12 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency fclk(ext). The clock frequency fclk determines the LCD frame frequency (ffr). 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the output from pin CLK is the clock signal for any cascaded PCF8534A in the system. After power-on, SDA must be HIGH to guarantee that the clock starts. 7.5.2 External clock Connecting pin OSC to VDD enables an external clock source. Pin CLK becomes the external clock input. A clock signal must always be applied to the device, removing the clock can freeze the LCD in a DC state. 7.6 Timing The timing of the PCF8534A sequences the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between all the PCF8534As in the system. The timing also generates the LCD frame frequency which is derived as an integer division of the clock frequency (see Table 6). When an external clock is used, the frame frequency is a fixed division of the internal clock or the frequency applied to pin CLK. Table 6. LCD frame frequencies Frame frequency Nominal frame frequency (Hz) f clk f fr = --------24 64 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display register, the LCD segment outputs and one column of the display RAM. 7.8 Segment outputs The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. When less than 60 segment outputs are required the unused segment outputs must be left open-circuit. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 13 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.9 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated based on the selected LCD drive mode. • In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required the unused outputs can be left as an open-circuit. • In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. • In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same signals and can also be paired to increase the drive capabilities. • In static drive mode: the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is static 60 × 4-bit RAM which stores LCD data. Logic 1 in the RAM bit map indicates the on-state of the corresponding LCD segment, logic 0 indicates the off-state. There is a direct relationship between RAM addresses and the segment outputs and the individual bits of a RAM word and the backplane outputs. The first RAM row corresponds to the 60 segments operated with respect to backplane BP0 (see Figure 10). In multiplexed LCD applications, the segment data of rows 1 to 4 of the display RAM are time-multiplexed with BP0, BP1, BP2 and BP3, respectively. display RAM addresses (columns)/segment outputs (S) 0 1 2 3 4 55 56 57 58 59 0 display RAM bits 1 (rows)/ backplane outputs 2 (BP) 3 001aah617 Display RAM bit map showing the direct relationship between backplane outputs, display RAM addresses and segment outputs and between bits in a RAM word and backplane outputs. Fig 10. Display RAM bit map When display data is transmitted to the PCF8534A, the display bytes received are stored in the display RAM based on the selected LCD drive mode. Data is stored as it arrives and does not wait for the acknowledge cycle. Depending on the current multiplexer mode data is stored singularly, in pairs, triplets or quadruplets. In 1:2 multiplexer mode for example, RAM data is stored every second bit. An example of a 7-segment numeric display illustrating the storage order for all drive modes is shown in Figure 11. The RAM storage organization applies equally to other LCD types. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 14 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates The following applies to Figure 11: • Static drive mode: the eight transmitted data bits are placed in row 0 to eight successive display RAM addresses. • 1:2 multiplex drive mode: the eight transmitted data bits are placed in row 0 and 1 to four successive display RAM addresses. • 1:3 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1 and 2 to three successive addresses. However, bit 2 of the third address is left unchanged. This last bit can, if necessary, be controlled by an additional transfer to this address but avoid overriding adjacent data because full bytes are always transmitted. • 1:4 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1, 2 and 3 to two successive display RAM addresses. 7.11 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load data pointer command. After this, the data byte is stored starting at the display RAM address indicated by the data pointer (see Figure 11). Once each byte is stored, the data pointer is automatically incremented based on the selected LCD configuration. The contents of the data pointer are incremented as follows: • • • • In static drive mode by eight. In 1:2 multiplex drive mode by four. In 1:3 multiplex drive mode by three. In 1:4 multiplex drive mode by two. If an I2C-bus data access terminates early, the state of the data pointer is unknown. Consequently, the data pointer must be rewritten prior to further RAM accesses. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 15 of 44 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LCD segments g Sn+7 c Sn+1 DP BP1 e Sn+1 DP b f e BP1 c Sn BP2 DP b BP0 n 6 n 7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x n n 1 n 2 n 3 a b x x f g x x e c x x d DP x x n n 1 n 2 b DP c x a d g x f e x x n n 1 a c b DP f e g d LSB c b a f g e d DP e bit/ BP BP1 c a b f LSB g e c d DP 0 1 2 3 MSB LSB b DP c a d g f e BP3 0 1 2 3 MSB a c b DP f LSB e g d DP 16 of 44 © NXP B.V. 2008. All rights reserved. mgl751 x = data bit unchanged. Fig 11. Relationship between LCD layout, drive mode, display RAM storage order and display data transmitted over the I2C-bus PCF8534A d MSB BP2 g Sn+1 0 1 2 3 a f multiplex n 5 Sn bit/ BP d 1:4 n 4 BP0 a g multiplex bit/ BP c d Sn+2 n 3 b f Sn+3 1:3 n 2 Universal LCD driver for low multiplex rates Rev. 03 — 10 November 2008 Sn+2 0 1 2 3 a g multiplex n 1 BP0 Sn 1:2 n MSB bit/ BP Sn d Sn+6 transmitted display byte Sn+1 e Sn+5 BP0 b f Sn+4 static display RAM filling order a Sn+2 Sn+3 LCD backplanes NXP Semiconductors PCF8534A_3 Product data sheet drive mode PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.12 Subaddress counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device select command (see Table 12). If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is blocked but the data pointer will be incremented as if data storage had taken place. In cascaded applications each PCF8534A in the cascade must be addressed separately. Initially, the first PCF8534A is selected by sending the device select command matching the first device's hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load data pointer command. Once the display RAM of the first PCF8534A has been written, the second PCF8534A is selected by sending the device select command again. This time however the command matches the second device's hardware subaddress. Next the load data pointer command is sent to select the preferred display RAM address of the second PCF8534A. This last step is very important because during writing data to the first PCF8534A, the data pointer of the second PCF8534A is incremented. In addition, the hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface. 7.13 Output bank selector The output bank selector (see Table 13), selects one of the four bits per display RAM address for transfer to the display register. The actual bit selected depends on the LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially by the contents of bit 1, bit 2 and then bit 3. • In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially. • In 1:2 multiplex mode: bits 0 and 1 are selected. • In the static mode: bit 0 is selected. The SYNC signal resets these sequences to the following starting points: bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex and bit 0 for static mode. The PCF8534A includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In static drive mode, the bank select command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 multiplex drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This enables preparation of display information in an alternative bank and the ability to switch to it once it has been assembled. 7.14 Input bank selector The input bank selector loads display data into the display RAM based on the selected LCD drive configuration. Using the bank select command, display data can be loaded in bit 2 into static drive mode or in bits 2 and 3 into 1:2 multiplex drive mode. The input bank selector functions independently to the output bank selector. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 17 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 7.15 Blinker The display blinking capabilities of the PCF8534A are very versatile. The whole display can be blinked at frequencies set by the blink select command (see Table 14). The blinking frequencies are fractions of the clock frequency. The ratios between the clock and blinking frequencies depend on the mode in which the device is operating (see Table 7). Table 7. Blink frequencies Assuming that fclk = 1536 Hz. Blink mode Operating mode ratio Off Blink frequency - Blinking off 1 f clk f blink = --------768 2 Hz 2 f clk f blink = ----------1536 1 Hz 3 f clk f blink = ----------3072 0.5 Hz An additional feature is for the arbitrary selection of LCD segments to be blinked. This applies to the static and 1:2 multiplex drive modes and is implemented without any communication overheads. Using the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the blink select command. In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display needs to be blinked at a frequency other than the nominal blinking frequency, this can be done using the mode set command to set and reset the display enable bit E at the required rate (see Table 10). 8. Basic architecture 8.1 Characteristics of the I2C-bus The I2C-bus provides bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When connected to the output stages of a device, both lines must be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy. 8.1.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Figure 12. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 18 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates SDA SCL data line stable; data valid change of data allowed mba607 Fig 12. Bit transfer 8.1.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 13. SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 13. Definition of START and STOP conditions 8.1.2 System configuration A device generating a message is a ‘transmitter’ and a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’. The system configuration is illustrated in Figure 14. MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL mga807 Fig 14. System configuration 8.1.3 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 19 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the master receiver must leave the data line HIGH during the 9th pulse to not acknowledge. The master will now generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 15. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 15. Acknowledgement of the I2C-bus 8.1.4 PCF8534A I2C-bus controller The PCF8534A acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8534A are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, the transferred command data and the hardware subaddress. In single device application, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two devices with a common I2C-bus slave address have the same hardware subaddress. 8.1.5 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 20 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 8.2 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8534A. The least significant bit of the slave address is bit R/W. The PCF8534A is a write-only device. It will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defined by the level tied at input SA0. Two displays controlled by PCF8534A can be recognized on the same I2C-bus which allows: • Up to 16 PCF8534As on the same I2C-bus for very large LCD applications • The use of two types of LCD multiplex on the same I2C-bus The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the available PCF8534A slave addresses. All PCF8534As with the same SA0 level acknowledge in parallel to the slave address. All PCF8534As with the alternative SA0 level ignore the whole I2C-bus transfer. After acknowledgement, the control byte is sent defining if the next byte is RAM or command information. The control byte also defines if the next byte is a control byte or further RAM/command data (see Figure 16 and Table 8). In this way it is possible to configure the device and then fill the display RAM with little overhead. MSB 7 6 5 CO RS 4 3 2 LSB 0 1 not relevant mgl753 Fig 16. Control byte format Table 8. Load data pointer command bit description Bit Symbol 7 CO 6 5 to 0 Value continue bit 0 last control byte 1 control bytes continue RS - Description register selection 0 command register 1 data register not relevant The command bytes and control bytes are also acknowledged by all addressed PCF8534As connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8534A. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART I2C-bus access. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 21 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates R/W = 0 slave address control byte S C R S 0 1 1 1 0 0 A 0 A O S 0 RAM/command byte M A S B L S P B EXAMPLES a) transmit two bytes of RAM data S S 0 1 1 1 0 0 A 0 A 0 1 0 RAM DATA A RAM DATA A A COMMAND A 0 0 A COMMAND A P A COMMAND A 0 1 A RAM DATA A A P b) transmit two command bytes S S 0 1 1 1 0 0 A 0 A 1 0 0 c) transmit one command byte and two RAM date bytes S S 0 1 1 1 0 0 A 0 A 1 0 0 RAM DATA A P mgl752 Fig 17. I2C-bus protocol 8.3 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. There are five commands: Table 9. Definition of commands Command Opcode Reference Mode set 1 1 0 0 E B M1 M0 Table 10 Load data pointer 0 P6 P5 P4 P3 P2 P1 P0 Table 11 Device select 1 1 1 0 0 A2 A1 A0 Table 12 Bank select 1 1 1 1 1 0 I O Table 13 Blink select 1 1 1 1 0 A BF1 BF0 Table 14 Table 10. Mode set command bit description Bit Symbol Value Description 7 to 4 - 1100 fixed value 3 E display status the possibility to disable the display allows implementation of blinking under external control 2 0 disabled (blank) 1 enable B LCD bias configuration 0 1⁄ 3 bias 1 1⁄ 2 bias PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 22 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 10. Mode set command bit description …continued Bit Symbol 1 to 0 M[1:0] Value Description LCD drive mode selection 01 static; 1 backplane 10 1:2 multiplex; 2 backplanes 11 1:3 multiplex; 3 backplanes 00 1:4 multiplex; 4 backplanes Table 11. Load data pointer command bit description See Section 7.11. Bit Symbol Value Description 7 - 0 fixed value 6 to 0 P[6:0] 000 0000 to 7-bit binary value of 0 to 59 011 1011 Table 12. Device select command bit description See Section 7.12. Bit Symbol Value Description 7 to 3 - 1 1100 fixed value 2 to 0 A[2:0] 000 to 111 3-bit binary value of 0 to 7 Table 13. Bank select command bit description See Section 7.10, Section 7.11, Section 7.12, Section 7.13 and Section 7.14. Bit Symbol Value Description Static 7 to 2 - 1 I 0 [1] 11 1110 fixed value input bank selection: storage of arriving display data 0 RAM bit 0 RAM bits 0 and 1 1 RAM bit 2 RAM bits 2 and 3 O output bank selection: retrieval of LCD display data 0 RAM bit 0 RAM bits 0 and 1 1 RAM bit 2 RAM bits 2 and 3 The bank select command has no effect in 1:3 or 1:4 multiplex drive modes. PCF8534A_3 Product data sheet 1:2 multiplex[1] © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 23 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 14. Blink select command bit description See Section 7.15. Bit Symbol Value 7 to 3 - 1 1110 2 A 1 to 0 [1] Description fixed value blink mode selection 0 normal blinking[1] 1 blinking by alternating display RAM banks BF[1:0] blink frequency selection 00 off 01 1 10 2 11 3 Only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes. 8.4 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8534A and coordinates their effects. The controller also loads display data into the display RAM as required by the storage order. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 24 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 9. Internal circuitry VDD VDD VSS VSS SA0 VDD CLK SCL VSS VDD VSS OSC VSS VDD SDA SYNC VSS VSS VDD A0, A1, A2 VLCD VSS VLCD VSS BP0, BP1, BP2, BP3 VSS VLCD S0 to S59 VSS 001aah615 Fig 18. Device protection diagram PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 25 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD IDD Min Max supply voltage −0.5 +6.5 V supply current −50 +50 mA VLCD LCD supply voltage −0.5 +7.5 V IDD(LCD) LCD supply current −50 +50 mA ISS ground supply current −50 +50 mA VI input voltage [1] −0.5 +6.5 V input current [1] −10 +10 mA output voltage [1] −0.5 +6.5 V [2] −0.5 +7.5 V −10 +10 mA II VO Conditions [1][2] IO output current Ptot total power dissipation - 400 mW P/out power dissipation per output - 100 mW Tstg storage temperature Vesd electrostatic discharge voltage Ilu −65 +150 °C HBM [3] - ±2000 V MM [4] - ±200 V CDM [5] - ±2000 V [6] - 100 mA latch-up current [1] Pins SDA, SCL, CLK, SYNC, SA0, OSC and A0 to A2. [2] Pins S0 to S59 and BP0 to BP3. [3] HBM: Human Body Model, according to JESD22-A114. [4] MM: Machine Model, according to JESD22-A115. [5] CDM: Charged Device Model, according to JESD22-C101. [6] Latch-up testing, according to JESD78. PCF8534A_3 Product data sheet Unit © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 26 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 11. Static characteristics Table 16. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 1.8 - 5.5 V VLCD LCD supply voltage 2.5 - 6.5 V IDD supply current IDD(LCD) LCD supply current fclk = 1536 Hz [1] - 8 20 µA fclk = 1536 Hz [1] - 24 60 µA Logic VSS − 0.5 VI input voltage VDD + 0.5 V VIL LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2 and SA0 VSS - 0.3VDD V VIH HIGH-level input voltage on pins CLK, SYNC, OSC, A0 to A2 and SA0 0.7VDD - VDD V VPOR power-on reset voltage 1.0 1.3 1.6 V IOL LOW-level output current VOL = 0.4 V; VDD = 5 V; on pins CLK and SYNC 1 - - mA IOH HIGH-level output current VOH = 4.6 V; VDD = 5 V; on pin CLK −1 - - mA IL leakage current VI = VDD or VSS; on pins SA0, A0 to A2 and CLK −1 - +1 µA CI input capacitance −1 - +1 µA - - 7 pF VSS − 0.5 - 5.5 V pin SCL VSS - 0.3VDD V pin SDA VSS - 0.2VDD V 0.7VDD - 5.5 V 3 - - mA VI = VDD; on pin OSC [2] I2C-bus; pins SDA and SCL VI input voltage VIL LOW-level input voltage VIH HIGH-level input voltage IOL LOW-level output current VOL = 0.4 V; VDD = 5 V; on pin SDA IL leakage current VI = VDD or VSS Ci input capacitance −1 - +1 µA [2] - - 7 pF LCD outputs Output pins BP0, BP1, BP2 and BP3 VBP voltage on pin BP Cbpl = 35 nF [3] −100 - +100 mV RBP resistance on pin BP VLCD = 5 V [4] - 1.5 10 kΩ Csgm = 35 nF [5] −100 - +100 mV VLCD = 5 V [4] - 6.0 13.5 kΩ Output pins S0 to S59 voltage on pin S VS resistance on pin S RS [1] LCD outputs are open circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [2] Not tested, design specification only. [3] Cbpl = backplane capacitance. [4] Outputs measured individually and sequentially. [5] Csgm = segment capacitance. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 27 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 12. Dynamic characteristics Table 17. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 960 1536 3046 Hz 797 1536 3046 Hz Clock Internal: output pin CLK oscillator frequency fosc VDD = 5 V [1] External: input pin CLK fclk(ext) external clock frequency VDD = 5 V tclk(H) HIGH-level clock time 130 - - µs tclk(L) LOW-level clock time 130 - - µs Synchronization: input pin SYNC tPD(SYNC_N) SYNC propagation delay - 30 - ns tSYNC_NL SYNC LOW time 1 - - µs - - 30 µs Outputs: pins BP0 to BP3 and S0 to S59 tPD(drv) I2C-bus: driver propagation delay VLCD = 5 V timing[2] Pin SCL fSCL SCL frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - µs tHIGH HIGH period of the SCL clock 0.6 - - µs tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - µs tSU;STO set-up time for STOP condition 0.6 - - µs tHD;STA hold time (repeated) START condition 0.6 - - µs tSU;STA set-up time for a repeated START condition 0.6 - - µs tr rise time of both SDA and SCL signals - - 0.3 µs tf fall time of both SDA and SCL signals - - 0.3 µs Cb capacitive load for each bus line - - 400 pF tw(spike) spike pulse width - - 50 ns [1] Typical output (duty cycle δ = 50 %). [2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 28 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 1 / fclk tclk(H) tclk(L) 0.7VDD CLK 0.3VDD 0.7VDD SYNC 0.3VDD tPD(SYNC_N) tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3, and S0 to S59 (VDD = 5 V) 0.5 V tPD(drv) 001aah618 Fig 19. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 20. I2C-bus timing waveforms PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 29 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 13. Application information 13.1 Cascaded operation Large display configurations of up to 16 PCF8534As can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). Table 18. Addressing cascaded PCF8534A Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device 1 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 0 0 0 8 0 0 1 9 0 1 0 10 0 1 1 11 1 0 0 12 1 0 1 13 1 1 0 14 1 1 1 15 2 1 If cascaded PCF8534As are synchronized, they can share the backplane signals from one of the devices in the cascade. This is cost-effective in large LCD applications because the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8534As in the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 21). PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 30 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates VDD VLCD SDA 60 segment drives SCL SYNC PCF8534A CLK BP0 to BP3 (open-circuit) OSC A0 A1 SA0 VSS A2 LCD PANEL VLCD VDD R≤ tr 2Cb HOST MICROPROCESSOR/ MICROCONTROLLER VDD VLCD 60 segment drives SDA SCL SYNC PCF8534A CLK BP0 to BP3 OSC A0 VSS 4 backplanes A1 A2 SA0 VSS 001aah619 Fig 21. Cascaded PCF8534A configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8534As. Synchronization is guaranteed after a power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by defining a multiplex mode when PCF8534As with different SA0 levels are cascaded). SYNC is organized as an input/output pin. The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCF8534A asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCF8534A to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8534A are shown in Figure 22. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 31 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Fig 22. Synchronization of the cascade for various PCF8534A drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, the device will not be able to synchronize properly. Table 19 shows the maximum contact resistance values. Table 19. SYNC contact resistance Number of devices Maximum contact resistance 2 6000 Ω 3 to 5 2200 Ω 6 to 10 1200 Ω 11 to 16 700 Ω PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 32 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 14. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 80 21 1 detail X 20 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 12.1 11.9 0.5 HD HE 14.15 14.15 13.85 13.85 L Lp v w y 1 0.75 0.30 0.2 0.15 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 θ 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT315-1 136E15 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 23. Package outline SOT315-1 (LQFP80) PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 33 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 15. Bare die outline Wire bond die; 76 bonding pads; 2.91 x 2.62 x 0.38 mm PCF8534AU D e A 63 44 C1 C2 e 64 43 PC8534A-1(3) x 0 76 E 0 y 1 24 3 F 4 23 X 0 0.5 1 mm scale P4 P3 DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A D E e P1(1) P2(2) P3(1) P4(2) P2 0.38 2.91 2.62 0.06 0.05 0.10 0.09 0.08 P1 detail X Notes 1. Pad size 2. Passivation opening 3. Marking code OUTLINE VERSION REFERENCES IEC JEDEC JEITA PCF8534AU EUROPEAN PROJECTION ISSUE DATE 08-08-06 Fig 24. PCF8534AU die outline PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 34 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 20. Symbol Bonding pad locations Pad Coordinates[1] X (µm) Y (µm) Description SDA 1 −1384.4 −280 I2C-bus serial data input and output SCL 2 −1384.4 −760.5 I2C-bus serial clock input CLK 3 −1384.4 −945 external clock input and output VDD 4 −978.7 −1238 supply voltage SYNC 5 −829.3 −1238 cascade synchronization input and output OSC 6 −714.3 −1238 enable input for internal oscillator A0 7 −584.3 −1238 subaddress counter input A1 8 −454.3 −1238 A2 9 −324.3 −1238 SA0 10 −194.3 −1238 I2C-bus slave address input 0 VSS 11 −64.3 −1238 ground VLCD 12 68.7 −1238 input of LCD supply voltage S0 13 173.7 −1238 LCD segment output S1 14 253.7 −1238 S2 15 333.7 −1238 S3 16 413.7 −1238 S4 17 493.7 −1238 S5 18 573.7 −1238 S6 19 653.7 −1238 S7 20 733.7 −1238 S8 21 813.7 −1238 S9 22 893.7 −1238 S10 23 973.7 −1238 S11 24 1384.4 −841 S12 25 1384.4 −761 S13 26 1384.4 −681 S14 27 1384.4 −601 S15 28 1384.4 −521 S16 29 1384.4 −441 S17 30 1384.4 −361 S18 31 1384.4 −281 S19 32 1384.4 −201 S20 33 1384.4 −121 S21 34 1384.4 −41 S22 35 1384.4 39 S23 36 1384.4 119 S24 37 1384.4 301.6 S25 38 1384.4 381.6 S26 39 1384.4 461.6 S27 40 1384.4 541.6 PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 35 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 20. Symbol Bonding pad locations …continued Pad Coordinates[1] X (µm) Y (µm) S28 41 1384.4 621.6 S29 42 1384.4 701.6 S30 43 1384.4 781.6 S31 44 896.5 1239.4 S32 45 816.5 1239.4 S33 46 736.5 1239.4 S34 47 576.5 1239.4 S35 48 496.5 1239.4 S36 49 416.5 1239.4 S37 50 336.5 1239.4 S38 51 256.5 1239.4 S39 52 176.5 1239.4 S40 53 96.5 1239.4 S41 54 16.5 1239.4 S42 55 −63.5 1239.4 S43 56 −143.5 1239.4 S44 57 −223.5 1239.4 S45 58 −303.5 1239.4 S46 59 −463.5 1239.4 S47 60 −543.5 1239.4 S48 61 −623.5 1239.4 S49 62 −703.5 1239.4 S50 63 −783.5 1239.4 S51 64 −1384.4 935 S52 65 −1384.4 855 S53 66 −1384.4 775 S54 67 −1384.4 695 S55 68 −1384.4 615 S56 69 −1384.4 535 S57 70 −1384.4 375 S58 71 −1384.4 295 S59 72 −1384.4 215 BP0 73 −1384.4 125 BP1 74 −1384.4 45 BP2 75 −1384.4 −35 BP3 76 −1384.4 −115 [1] Description LCD segment output LCD backplane output All coordinates are referenced in µm to the center of the die (see Figure 24). PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 36 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates REF REF C1 C2 REF F 001aai649 Fig 25. Alignment marks Table 21. Alignment mark locations [1] Symbol X (µm) Y (µm) C1 −1387 1190 C2 1335 1242 F −1345 −1173 [1] All coordinates are referenced in µm to the center of the die (see Figure 24). 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 37 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 17. Packing information A 1.1 2.1 1.2 2.2 C x.1 3.1 D 1.3 F B 1.y y E x 001aai625 Fig 26. Tray details for PCF8534AU/DA/1 PC8534A-1 001aai650 Fig 27. Tray alignment for PCF8534AU/DA/1 PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 38 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates Table 22. Tray dimensions Symbol Description Value A pocket pitch in x direction 5.5 mm B pocket pitch in y direction 4.9 mm C pocket width in x direction 3.08 mm D pocket width in y direction 2.79 mm E tray width in x direction 50.8 mm F tray width in y direction 50.8 mm N number of pockets, x direction 8 M number of pockets, y direction 9 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 39 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 23 and 24 Table 23. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 24. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28. PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 40 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 25. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model IC Integrated Circuit LCD Liquid Crystal Display MM Machine Model RAM Random Access Memory PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 41 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 20. Revision history Table 26. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8534A_3 20081110 Product data sheet - PCF8534A_2 Modifications: PCF8534A_2 Modifications: PCF8534A_1 • Added bare die product and document sections 20080604 • • • Product data sheet PCF8534A_1 Added Caution to Section 10 on page 26. Changed Figure 22 on page 32. 20080423 Product data sheet PCF8534A_3 Product data sheet - Changes in Section 7.10 on page 14 and Section 7.12 on page 17. - - © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 42 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 21.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 21.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF8534A_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 November 2008 43 of 44 PCF8534A NXP Semiconductors Universal LCD driver for low multiplex rates 23. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 8 8.1 8.1.1 8.1.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.3 8.4 9 10 11 12 13 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 6 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 6 LCD drive mode waveforms . . . . . . . . . . . . . . . 8 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 8 1:2 Multiplex drive mode . . . . . . . . . . . . . . . . . . 9 1:3 Multiplex drive mode . . . . . . . . . . . . . . . . . 11 1:4 Multiplex drive mode . . . . . . . . . . . . . . . . . 12 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 13 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 13 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Display register . . . . . . . . . . . . . . . . . . . . . . . . 13 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 13 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Subaddress counter . . . . . . . . . . . . . . . . . . . . 17 Output bank selector. . . . . . . . . . . . . . . . . . . . 17 Input bank selector . . . . . . . . . . . . . . . . . . . . . 17 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Basic architecture . . . . . . . . . . . . . . . . . . . . . . 18 Characteristics of the I2C-bus . . . . . . . . . . . . . 18 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 START and STOP conditions . . . . . . . . . . . . . 19 System configuration . . . . . . . . . . . . . . . . . . . 19 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 19 PCF8534A I2C-bus controller . . . . . . . . . . . . . 20 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 Command decoder . . . . . . . . . . . . . . . . . . . . . 22 Display controller . . . . . . . . . . . . . . . . . . . . . . 24 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 25 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 Static characteristics. . . . . . . . . . . . . . . . . . . . 27 Dynamic characteristics . . . . . . . . . . . . . . . . . 28 Application information. . . . . . . . . . . . . . . . . . 30 13.1 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 21 21.1 21.2 21.3 21.4 22 23 Cascaded operation . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 33 34 37 38 39 39 39 40 40 41 42 43 43 43 43 43 43 44 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 November 2008 Document identifier: PCF8534A_3