INTEGRATED CIRCUITS 74ALVT16899 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Product specification IC23 Data Handbook 1998 Jun 30 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. FEATURES • Symmetrical (A and B bus functions are identical) • Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions The 74ALVT16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. • Independent transparent latches for A-to-B and B-to-A directions • Selectable ODD/EVEN parity • Continuously checks parity of both A bus and B bus latches as FUNCTIONAL DESCRIPTION: ERRA and ERRB The 74ALVT16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. • Open-collector ERR output • Ability to simultaneously generate and check parity • Can simultaneously read/latch A and B bus data • Output capability: +64 mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) and 200 V per Machine Model Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. • Power up 3-State • Power-up reset • No bus current loading when output is tied to 5 V bus • Live insertion/extraction permitted • Bus-hold data inputs eliminate the need for external pull-up Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of: resistors to hold unused inputs DESCRIPTION • Transparent latch / 1 bus latched / both buses latched • Feed-through parity / generate parity • Check in bus parity / check out bus parity / check in and out bus The 74ALVT16899 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V. The 74ALVT16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus parity QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 2.5 V 3.3 V tPLH tPHL Propagation delay An to Bn or Bn to An CL = 50pF 2.0 2.2 1.5 1.7 ns tPLH tPHL Propagation delay An to ERRA CL = 50pF 9.8 7.0 7.8 5.1 ns CIN Input capacitance VI = 0V or VCC 3 3 pF CI/O Output capacitance Outputs disabled; VO = 0V or VCC 9 9 pF ICCZ Quiescent supply current Outputs disabled 40 70 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT16899 AV16899 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT16899 DGG AV16899 DGG SOT364-1 1998 Jun 30 2 853-2090-19651 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 PIN CONFIGURATION ODD/EVEN 1 56 SEL OEA 2 55 LEA 1B0 1A0 3 54 GND 4 53 GND 1A1 5 52 1B1 1A2 6 51 1B2 1A3 7 50 1B3 1A4 8 49 1B4 VCC 9 48 VCC 1A5 10 47 1B5 1A6 11 46 1B6 1A7 12 45 1B7 1APAR 13 44 1BPAR 1ERRA 14 43 1ERRB GND 15 42 GND 2ERRA 16 41 2ERRB 2APAR 17 40 2BPAR 2A7 18 39 2B7 2A6 19 38 2B6 2A5 20 37 2B5 VCC 21 36 VCC 2A4 22 35 2B4 2A3 23 34 2B3 2A2 24 33 2B2 2A1 25 32 2B1 GND 26 31 GND 2A0 27 30 2B0 LEB 28 29 OEB SV01731 PIN DESCRIPTION SYMBOL PIN NUMBER 1A0 - 1A7 2A0 - 2A7 3, 5, 6, 7, 8, 10, 11, 12 27, 25, 24, 23, 22, 20, 19, 18 Latched A bus 3-State inputs/outputs 1B0 - 1B7 2B0 - 2B7 54, 52, 51, 50, 49, 47, 46, 45 30, 32, 33, 34, 35, 37, 38, 39 Latched B bus 3-State inputs/outputs 1APAR 2APAR 13, 17 A bus parity 3-State input/output 1BPAR 2BPAR 44, 40 B bus parity 3-State input/output ODD/EVEN 1 OEA, OEB 2, 29 NAME AND FUNCTION Parity select input (Low for EVEN parity) Output enable inputs (gate A to B, B to A) SEL 56 LEA, LEB 55, 28 Latch enable inputs (transparent High) 1ERRA, 1ERRB 2ERRA, 2ERRB 14, 43, 16, 41 Error signal outputs (active-Low) GND 4, 15, 26, 31, 42, 53 VCC 9, 21, 36, 48 1998 Jun 30 Mode select input (Low for generate) Ground (0V) Positive supply voltage 3 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 LOGIC SYMBOL 3 5 6 7 8 10 11 12 13 27 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1APAR 25 24 23 22 20 19 18 17 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2APAR 55 LEA 55 LEA 28 LEB 28 LEB 56 SEL 14 56 SEL 2ERRA 16 43 1 ODD/EVEN 2ERRB 41 1ERRA 1 ODD/EVEN 2 OEA 2 OEA 29 OEB 29 OEB 1ERRB 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1BPAR 54 52 51 50 49 47 46 45 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2BPAR 44 30 32 33 34 35 37 38 39 40 SH00083 PARITY AND ERROR FUNCTION TABLE INPUTS SEL H H xPAR (A or B) Σ of High Inputs xPAR (B or A) ERRt ERRr* H Even Odd H H H L H L L L L H L H H H L Even Odd H L H Even Odd H H L H L H L L H L H L H L L Even Odd L H H Even Odd H L H L H H H L L H H H L H L Even Odd L L H Even Odd L H L H H H L Even Odd L H H L H H L H L t r * ODD/EVEN OUTPUTS L = High voltage level = Low voltage level = Transmit–if the data path is from A→B then ERRt is ERRA = Receive–if the data path is from A→B then ERRr is ERRB Blocked if latch is not transparent 1998 Jun 30 4 PARITY MODES Odd Mode Feed-through/check parity Even Mode Odd Mode Even Mode Generate parity Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 BLOCK DIAGRAM OE 9–bit Transparent Latch LEA OEB 9–bit Output Buffer LE A0 A1 1 mux Parity Generator B0 B1 0 A2 A3 B2 B3 B4 A4 A5 B5 B6 A6 A7 B7 BPAR APAR 9–bit Transparent Latch 9–bit Output Buffer OEA OE LE 1 mux Parity Generator 0 LEB ERRA SEL ERRB (1 of 2 parity blocks) ODD/ EVEN SH00084 FUNCTION TABLE INPUTS OPERATING MODE OEB OEA SEL LEA LEB H H X X X 3-State A bus and B bus (input A & B simultaneously) H L L L H B → A, transparent B latch, generate parity from B0 - B7, check B bus parity H L L H H B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity H L L X L B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity H L H X H B → A, transparent B latch, parity feed-through, check B bus parity H L H H H B → A, transparent A & B latch, parity feed-through, check A & B bus parity L H L H X A → B, transparent A latch, generate parity from A0 - A7, check A bus parity L H L H H A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity L H L L X A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity L H H H L A → B, transparent A latch, parity feed-through, check A bus parity L H H H H A → B, transparent A & B latch, parity feed-through, check A & B bus parity L L X X X Output to A bus and B bus (NOT ALLOWED) H = High voltage level L = Low voltage level X = Don’t care 1998 Jun 30 5 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC IIK DC input diode current VI DC input voltage3 IOK DC output diode current VOUT CONDITIONS RATING DC supply voltage V -50 mA VI < 0 DC output voltage3 IOUT DC output out ut current Tstg Storage temperature range UNIT -0.5 to +4.6 -0.5 to +7.0 V VO < 0 -50 mA Output in Off or High state -0.5 to +7.0 V Output in Low state 128 Output in High state -64 mA °C -65 to +150 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC 2.5V RANGE LIMITS PARAMETER DC supply voltage 3.3V RANGE LIMITS UNIT MIN MAX MIN MAX 2.3 2.7 3.0 3.6 V 0 5.5 0 5.5 V VI Input voltage VIH High-level input voltage VIL Input voltage 0.7 0.8 V IOH High-level output current –8 –32 mA Low-level output current 8 32 Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 24 64 IOL ∆t/∆v Input transition rise or fall rate; Outputs enabled Tamb Operating free-air temperature range 1998 Jun 30 1.7 2.0 10 –40 6 +85 –40 V mA 10 ns/V +85 °C Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 DC ELECTRICAL CHARACTERISTICS (3.3V 0.3V RANGE) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK VOH Input clamp voltage output High-level out ut voltage VOL output Low–level out ut voltage VRST Power-up output low voltage6 VCC = 3.0V; IIK = –18mA VCC = 3.0 to 3.6V; IOH = –100µA VCC = 3.0V; IOH = –32mA IHOLD Off current Bus Hold current Data inputs VCC 2.0 2.3 0.2 0.25 0.4 VCC = 3.0V; IOL = 32mA 0.3 0.5 VCC = 3.0V; IOL = 64mA 0.4 0.55 VCC = 3.6V; IO = 1mA; VI = VCC or GND 0.55 Control pins ins VCC = 3.6V; VI = 5.5V Data pins4 0.1 ±1 0.1 10 0.1 20 0.5 1 VCC = 3.6V; VI = 0V 0.1 -5 VCC = 0V; VI or VO = 0 to 4.5V 0.1 ±100 VCC = 3V; VI = 0.8V 75 130 VCC = 3V; VI = 2.0V –75 –140 VI = 0V to 3.6V; VCC = 3.6V7 ±500 UNIT V V 0.07 VCC = 3.6V; VI = VCC IOFF –1.2 VCC–0.2 VCC = 3.0V; IOL = 16mA VCC = 0 or 3.6V; VI = 5.5V Input leakage current MAX –0.85 VCC = 3.0V; IOL = 100µA VCC = 3.6V; VI = VCC or GND II TYP1 V V µA µA µA Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 3.0V 10 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC OE/OE = Don’t care 33 ±100 µA IOZH 3-State output High current VCC = 3.6V; VO = 3.0V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 3.6V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 0.05 0.1 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 4.6 7.0 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05 0.06 0.1 VCC = 3V to 3.6V; One input at VCC–0.6V, Other inputs at VCC or GND 0.04 0.4 IEX IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 mA mA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Jun 30 7 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 AC CHARACTERISTICS (3.3V 0.3V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM UNIT MIN TYP1 MAX tPLH tPHL Propagation delay An to Bn or Bn to An 1 0.5 0.5 1.5 1.7 2.7 2.8 ns tPLH tPHL Propagation delay An to BPAR or Bn to APAR 4 2.5 2.0 5.0 4.6 8.0 7.3 ns tPLH tPHL Propagation delay An to ERRA or Bn to ERRB 5 2.5 2.5 7.8 5.1 11.5 8.5 ns tPLH tPHL Propagation delay APAR to BPAR or BPAR to APAR 3 1.0 1.0 2.9 3.0 6.9 6.4 ns tPLH tPHL Propagation delay APAR to ERRA or BPAR to ERRB 8 2.5 1.0 5.1 2.5 8.0 3.6 ns tPLH tPHL Propagation delay ODD/EVEN to APAR or BPAR 7 1.5 1.5 3.8 3.4 6.5 5.4 ns tPLH tPHL Propagation delay ODD/EVEN to ERRA or ERRB 6 2.5 1.5 6.6 4.0 10.0 6.6 ns tPLH tPHL Propagation delay SEL to APAR or BPAR 10 1.0 1.0 2.6 2.4 4.0 3.4 ns tPLH tPHL Propagation delay SEL to ERRA or ERRB 5 2.5 1.5 7.8 4.8 10.8 7.1 ns tPLH tPHL Propagation delay LEA to Bn or LEB to An 11 1.0 1.0 2.2 2.2 3.8 3.8 ns tPLH tPHL Propagation delay LEA to BPAR or LEB to APAR 11 2.5 2.0 5.3 4.9 8.5 7.6 ns tPLH tPHL Propagation delay LEA to ERRA or LEB to ERRB 9 2.5 2.5 7.4 5.6 11.0 9.2 ns tPZH tPZL Output enable time OEA to An, APAR or OEB to Bn, BPAR 13, 14 1.0 0.5 2.4 1.8 5.8 3.3 ns 13, 14 2.5 1.0 5.2 2.4 8.0 3.5 ns tPHZ Output disable time tPLZ OEA to An, APAR or OEB to Bn, BPAR NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC SETUP REQUIREMENTS (3.3V 0.3V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V UNIT MIN TYP 12 1.0 1.0 0.1 0.1 ns Hold time, High or Low An, APAR to LEA or Bn, BPAR to LEB 12 1.0 1.0 –0.1 0.1 ns Pulse width, High LEA or LEB 12 1.0 – ns ts(H) ts(L) Setup time, High or Low An, APAR to LEA or Bn, BPAR to LEB th(H) th(L) tw(H) 1998 Jun 30 WAVEFORM 8 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 DC ELECTRICAL CHARACTERISTICS (2.5V 0.2V RANGE) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK VOH VOL VRST Input clamp voltage output High-level out ut voltage Low-level output voltage Power-up output low voltage7 VCC = 2.3V; IIK = –18mA VCC = 2.3 to 3.6V; IOH = –100µA VCC = 2.3V; IOH = –8mA –1.2 VCC–0.2 VCC 1.8 2.5 0.07 0.2 0.3 0.5 VCC = 2.3V; IOL = 8mA 0.4 VCC = 2.7V; IO = 1mA; VI = VCC or GND 0.55 Control pins ins VCC = 2.7V; VI = 5.5V Data pins4 VCC = 2.7V; VI = VCC UNIT V V VCC = 2.3V; IOL = 24mA VCC = 0 or 2.7V; VI = 5.5V Input leakage current MAX –0.85 VCC = 2.3V; IOL = 100µA VCC = 2.7V; VI = VCC or GND II TYP1 0.1 ±1 0.1 10 0.1 20 0.1 10 V V µA VCC = 2.7V; VI = 0 0.1 -5 Off current VCC = 0V; VI or VO = 0 to 4.5V 0.1 ±100 Bus Hold current VCC = 2.3V; VI = 0.7V 115 µA Data inputs VCC = 2.3V; VI = 1.7V 10 µA Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 2.3V 10 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don’t care 33 ±100 µA IOZH 3-State output High current VCC = 2.7V; VO = 2.3V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 2.7V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0 0.04 0.1 VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0 3.5 4.5 VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO = 05 0.04 0.1 VCC = 2.3V to 2.7V; One input at VCC–0.6V, Other inputs at VCC or GND 0.04 0.4 IOFF IHOLD6 IEX IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 µA mA mA NOTES: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V ± 0.2V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. Not guaranteed. 7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 1998 Jun 30 9 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 AC CHARACTERISTICS (2.5V 0.2V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 2.5V ± 0.2V WAVEFORM UNIT MIN TYP1 MAX tPLH tPHL Propagation delay An to Bn or Bn to An 1 1.0 1.0 2.0 2.2 3.5 3.9 ns tPLH tPHL Propagation delay An to BPAR or Bn to APAR 4 3.0 3.0 7.0 6.5 10.5 10.2 ns tPLH tPHL Propagation delay An to ERRA or Bn to ERRB 5 4.5 3.5 9.8 7.0 14.5 11.5 ns tPLH tPHL Propagation delay APAR to BPAR or BPAR to APAR 3 1.0 1.0 3.0 3.5 4.3 5.5 ns tPLH tPHL Propagation delay APAR to ERRA or BPAR to ERRB 8 3.0 1.5 6.7 3.6 10.0 5.4 ns tPLH tPHL Propagation delay ODD/EVEN to APAR or BPAR 7 2.5 2.5 5.2 5.0 7.8 7.8 ns tPLH tPHL Propagation delay ODD/EVEN to ERRA or ERRB 6 4.0 4.0 8.6 8.1 12.0 10.6 ns tPLH tPHL Propagation delay SEL to APAR or BPAR 10 1.5 1.5 3.7 3.2 5.5 5.3 ns tPLH tPHL Propagation delay SEL to ERRA or ERRB 5 4.5 3.0 9.4 7.6 14.0 11.5 ns tPLH tPHL Propagation delay LEA to Bn or LEB to An 11 1.0 1.0 3.0 3.0 4.8 4.6 ns tPLH tPHL Propagation delay LEA to BPAR or LEB to APAR 11 2.5 2.5 7.5 7.4 12.2 11.2 ns tPLH tPHL Propagation delay LEA to ERRA or LEB to ERRB 9 4.5 3.5 9.7 8.5 15.0 13.4 ns tPZH tPZL Output enable time OEA to An, APAR or OEB to Bn, BPAR 13, 14 1.5 1.0 4.0 2.6 6.0 4.6 ns 13, 14 1.5 1.0 4.5 3.7 6.5 5.0 ns tPHZ Output disable time tPLZ OEA to An, APAR or OEB to Bn, BPAR NOTE: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. AC SETUP REQUIREMENTS (2.5V 0.2V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 2.5V ±0.2V UNIT MIN TYP 12 –1.0 1.2 –0.4 0.4 ns Hold time, High or Low An, APAR to LEA or Bn, BPAR to LEB 12 –1.0 1.2 –0.4 0.5 ns Pulse width, High LEA or LEB 12 1.0 – ns ts(H) ts(L) Setup time, High or Low An, APAR to LEA or Bn, BPAR to LEB th(H) th(L) tw(H) 1998 Jun 30 WAVEFORM 10 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 AC WAVEFORMS VM = 1.5V or VCC/2 whichever is less; VIN = GND to 3.0V nOE INPUT 3.0V or VCC, whichever is less nAx INPUT VM 3.0V or VCC whichever is less VM VM 0V VM tPZL tPLZ 0 VM nYx OUTPUT tPLH tPHL VX VOH nYx OUTPUT VM tPHZ tPZH VM VOL VOH VOL VY VM nYx OUTPUT 0V SW00160 Waveform 1. SW00204 Waveform 2. 3-State Output Enable and Disable Times Input (nAx) to Output (nYx) Propagation Delays 1 SEL An, APAR (Bn, BPAR) INPUT VM VM tPLH tPHL Bn, BPAR (An, APAR) VM OUTPUT VM SA00293 Waveform 3. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR SEL 0 ODD/EVEN 0 LEA (LEB) An (Bn) 1 ODD PARITY EVEN PARITY VM tPHL VM ODD PARITY INPUT tPLH BPAR (APAR) VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00294 Waveform 4. Propagation Delay, An to BPAR or Bn to APAR 1998 Jun 30 11 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 ODD/EVEN 0 APAR (BPAR) 0 LEA (LEB) SEL An (Bn) 1 ODD PARITY EVEN PARITY VM ODD PARITY INPUT tPHL tPLH ERRA (ERRB) VM VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00295 Waveform 5. Propagation Delay, An to ERRA or Bn to ERRB 1 APAR (BPAR) An (Bn) ODD/EVEN EVEN PARITY INPUT VM VM tPLH ERRA (ERRB) INPUT tPHL VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA00296 Waveform 6. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB 1998 Jun 30 12 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 SEL 0 APAR (BPAR) 0 An (Bn) EVEN PARITY ODD/EVEN VM INPUT VM tPLH BPAR (APAR) INPUT tPHL VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA00297 Waveform 7. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR ODD/EVEN 0 An (Bn) APAR (BPAR) EVEN PARITY VM INPUT VM tPHL tPLH ERRA (ERRB) INPUT VM VM OUTPUT NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00298 Waveform 8. Propagation Delay, APAR to ERRA or BPAR to ERRB 1998 Jun 30 13 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 1 ODD/EVEN APAR (BPAR) 0 An (Bn) EVEN PARITY ODD PARITY LEA (LEB) VM EVEN PARITY INPUT VM tPHL tPLH ERRA (ERRB) INPUT VM VM OUTPUT NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o SA00299 Waveform 9. Propagation Delay, LEA to ERRA or LEB to ERRB 1 ODD/EVEN APAR (BPAR) 0 An (Bn) SEL EVEN PARITY VM INPUT VM tPLH BPAR (APAR) INPUT tPHL VM VM OUTPUT NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00300 Waveform 10. Propagation Delay, SEL to BPAR or SEL to APAR 1998 Jun 30 14 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 1 SEL APAR, An] (BPAR, Bn) INPUT LEA (LEB) VM INPUT VM tPHL tPLH Bn, BPAR (An, APAR) VM OUTPUT VM SA00301 Waveform 11. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An ÉÉÉ ÉÉÉ ÉÉÉ APAR, BPAR, An, Bn VM ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ VM ts(H) VM th(H) VM ts(L) th(L) LEA, LEB VM VM VM tw(H) The shaded areas indicate when the input is permitted to change for predictable output performance. SA00302 Waveform 12. Data Setup and Hold Times, Pulse Width High OEA, OEB VM VM tPZH tPHZ An, APAR, Bn, BPAR VOH –0.3V VM 0V SA00303 Waveform 13. 3-State Output Enable Time to High Level and Output Disable Time from High Level OEA, OEB VM VM tPZL An, APAR, Bn, BPAR tPLZ VM VOL +0.3V SA00304 Waveform 14. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1998 Jun 30 15 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 TEST CIRCUIT AND WAVEFORM VCC VX VIN RX VOUT PULSE GENERATOR 90% VM CL AMP (V) VM 10% D.U.T. RT tW 90% NEGATIVE PULSE 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% POSITIVE PULSE Test Circuit for Open Collector Outputs VM VM 10% SWITCH POSITION TEST SWITCH tPLZ/tPZL 6 V or VCC × 2 open tPLH/tPHL tPHZ/tPZH GND LOAD VALUES OUTPUT RX ERROR All other 100 500 0V VX Input Pulse Definition VCC switch DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tW INPUT PULSE REQUIREMENTS FAMILY Amplitude 3.0V or VCC, 74ALVT16 which ever is less Rep. Rate tw ≤ 10MHz 500ns tR tF ≤ 2.5ns ≤ 2.5ns SV01732 1998 Jun 30 16 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1998 Jun 30 17 74ALVT16899 SOT371-1 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Jun 30 18 74ALVT16899 SOT364-1 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) NOTES 1998 Jun 30 19 74ALVT16899 Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 20 Date of release: 05-96 9397-750-04066