PHILIPS BUK135-50L

Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
DESCRIPTION
Monolithic logic level protected
power MOSFET using TOPFET2
technology assembled in a 5 pin
surface mounting plastic package.
APPLICATIONS
General purpose switch for
automotive systems and other
applications.
FEATURES
TrenchMOS output stage with
low on-state resistance
Separate input pin for higher
frequency drive
5 V logic compatible input
Separate supply pin for logic
and protection circuits with low
operating current
Overtemperature protection
Drain current limiting
Short circuit load protection
Latched overload trip state reset
by the protection pin
Diagnostic flag pin indicates
protection supply connected,
overtemperature condition,overload
tripped state, or open circuit load
(detected in the off-state)
ESD protection on all pins
Overvoltage clamping
BUK135-50L
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
SYMBOL
PARAMETER
VPS
Protection supply voltage
MAX.
UNIT
50
30
90
150
28
V
A
W
˚C
mΩ
NOM.
UNIT
5
V
FUNCTIONAL BLOCK DIAGRAM
DRAIN
PROTECTION SUPPLY
FLAG
OC LOAD
O/V
DETECT
CLAMP
POWER
INPUT
MOSFET
RIG
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT426
PIN
PIN CONFIGURATION
DESCRIPTION
1
input
2
flag
3
(connected to mb)
4
protection supply
5
source
D
mb
TOPFET
P
F
I
P
3
1 2
S
4 5
Fig. 2.
mb
SYMBOL
Fig. 3.
drain
July 2002
1
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
BUK135-50L
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VIS = 0 V
-
50
V
VPS = 5 V; Tmb = 25˚C
-
A
VPS = 0 V; Tmb = 85˚C
-5
-5
-5
self limited
30
5
5
5
A
mA
mA
mA
-
90
W
-55
-
175
150
260
˚C
˚C
˚C
MIN.
MAX.
UNIT
-
2
kV
Continuous voltage
VDS
Drain source voltage1
Continuous currents
ID
Drain current
II
IF
IP
Input current
Flag current
Protection supply current
Thermal
Ptot
Total power dissipation
Tmb = 25˚C
Tstg
Tj
Tsold
Storage temperature
Junction temperature2
Mounting base temperature
continuous
during soldering
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage
Human body model;
C = 250 pF; R = 1.5 kΩ
OVERLOAD PROTECTION LIMITING VALUE
With an adequate protection supply
connected, TOPFET can protect
itself from two types of overload overtemperature and short circuit
load.
SYMBOL
VDS
For overload conditions an n-MOS
transistor turns on between the
input and source to quickly
discharge the power MOSFET
gate capacitance.
PARAMETER
REQUIRED CONDITION
Overload protection3
protection supply
Drain source voltage
VPS ≥ 4 V
The drain current is limited to
reduce dissipation in case of short
circuit load. Refer to OVERLOAD
CHARACTERISTICS.
MIN.
MAX.
UNIT
0
35
V
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Inductive load turn off
IDM = 20 A; VDD ≤ 20 V
EDSM
Non-repetitive clamping energy
Tmb = 25˚C
-
350
mJ
EDRM
Repetitive clamping energy
Tmb ≤ 95˚C; f = 250 Hz
-
45
mJ
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 All control logic and protection functions are disabled during conduction of the source drain diode. If the protection circuit was previously
latched, it would be reset by this condition.
July 2002
2
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
BUK135-50L
THERMAL CHARACTERISTIC
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
-
1.2
1.39
K/W
MIN.
TYP.
MAX.
UNIT
Thermal resistance
Rth j-mb
Junction to mounting base
-
OUTPUT CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified.
SYMBOL
V(CL)DSS
IDSS
RDS(ON)
PARAMETER
CONDITIONS
Off-state
VIS = 0 V
Drain-source clamping voltage
ID = 10 mA
50
-
70
V
IDM = 4 A; tp ≤ 300 µs; δ ≤ 0.01
50
60
70
V
-
0.1
100
10
µA
µA
-
21
50
28
mΩ
mΩ
MIN.
TYP.
MAX.
UNIT
0.6
1.1
1.6
2.6
2.1
V
V
VIS = 5 V
-
16
100
µA
II = 1 mA
5.5
6.4
8.5
V
-
1.7
-
kΩ
1
2.7
4
mA
1
Drain source leakage current
VPS = 0 V; VDS = 40 V
Tmb = 25˚C
On-state
tp ≤ 300 µs; δ ≤ 0.01; VPS ≥ 4 V
Drain-source resistance
IDM = 10 A; VIS ≥ 4.4 V
Tmb = 25˚C
INPUT CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
Normal operation
VIS(TO)
Input threshold voltage2
IIS
Input current
V(CL)IS
Input clamping voltage
RIG
IISL
ID = 1 mA
3
Tmb = 25˚C
Internal series resistance
to gate of power MOSFET
Overload protection latched
VPS ≥ 4 V
Input current
VIS = 5 V
1 The drain current required for open circuit load detection is switched off when there is no protection supply, in order to ensure a low off-state
quiescent current. Refer to OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS.
2 The measurement method is simplified if VPS = 0 V, in order to distinguish ID from IDSP. Refer to OPEN CIRCUIT LOAD DETECTION
CHARACTERISTICS.
3 This is not a directly measurable parameter.
July 2002
3
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
BUK135-50L
PROTECTION SUPPLY CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2.5
3.45
4
V
Protection & detection
VPSF
Threshold voltage1
IF = 100 µA; VDS = 5 V
IPS, IPSL
Normal operation or
protection latched
Supply current
VPS = 4.5 V
-
210
450
µA
V(CL)PS
Clamping voltage
IP = 1.5 mA
5.5
6.5
8.5
V
VPS ≤ 1 V
1
10
1.8
45
3
120
V
µs
Overload protection latched
VPSR
tpr
Reset voltage
Reset time
OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS
An open circuit load condition can be detected while the TOPFET is in the off-state. Refer to TRUTH TABLE.
VPS = 5 V. Limits are for -40˚C ≤ Tmb ≤ 150˚C and typicals are for Tmb = 25˚C.
SYMBOL
IDSP
VDSF
VISF
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIS = 0 V; 2 V ≤ VDS ≤ 40 V
0.9
1.8
2.7
mA
3
VIS = 0 V
0.2
1
2
V
4
ID = 100 µA
0.3
0.8
1.1
V
MIN.
TYP.
MAX.
UNIT
28.5
44
60
A
75
185
250
W
2
Off-state drain current
Drain threshold voltage
Input threshold voltage
OVERLOAD CHARACTERISTICS
Tmb = 25˚C unless otherwise specified.
SYMBOL
ID
PD(TO)
PARAMETER
CONDITIONS
Short circuit load
VPS > 4 V
Drain current limiting
VIS = 5 V;
Overload protection
VPS > 4 V
Overload power threshold
device trips if PD > PD(TO)
-40˚C ≤ Tmb ≤ 150˚C
TDSC
Characteristic time
which determines trip time
250
380
600
µs
Tj(TO)
Overtemperature protection
Threshold temperature
VPS = 5 V
from ID ≥ 4 A or VDS > 0.2 V
150
170
-
˚C
5
1 When VPS is less than VPSF the flag pin indicates low protection supply voltage. Refer to TRUTH TABLE.
2 The drain source current which flows in a normal load when the protection supply is high and the input is low.
3 If VDS < VDSF then the flag indicates open circuit load.
4 For open circuit load detection, VIS must be less than VISF.
5 Trip time td sc varies with overload dissipation PD according to the formula td sc ≈ TDSC / ln[ PD / PD(TO)].
July 2002
4
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
BUK135-50L
TRUTH TABLE
For normal, open-circuit load and overload conditions or inadequate protection supply voltage.
Assumes proper external pull-up for flag pin. Refer to FLAG CHARACTERISTICS.
CONDITION
PROTECTION
INPUT
FLAG
OUTPUT
Normal on-state
1
1
0
ON
Normal off-state
1
0
0
OFF
Open circuit load
1
1
0
ON
Open circuit load
1
0
1
OFF
Short circuit load1
1
1
1
OFF
Over temperature
1
X
1
OFF
Low protection supply voltage
0
1
1
ON
Low protection supply voltage
0
0
1
OFF
KEY ‘0’ equals low
‘1’ equals high
‘X’ equals don’t care.
FLAG CHARACTERISTICS
The flag is an open drain transistor which requires an external pull-up circuit.
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Flag ‘low’
normal operation; VPS = 5 V
VFSF
Flag voltage
IF = 100 µA
-
0.8
1
V
IFSF
Flag saturation current
VFS = 5 V
-
10
-
mA
Flag ‘high’
overload or fault
IFSO
Flag leakage current
VFS = 5 V
-
0.1
10
µA
V(CL)FS
Flag clamping voltage
IF = 100 µA
5.5
6.2
8.5
V
-
47
-
kΩ
Application information
RF
Suitable external pull-up
resistance
VFF = 5 V
SWITCHING CHARACTERISTICS
Tmb = 25˚C; RI = 50 Ω; RIS = 50 Ω; VDD = 15 V; resistive load RL = 10 Ω.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
td on
Turn-on delay time
VIS: 0 V ⇒ 5 V
-
1.8
5
µs
tr
Rise time
-
3.5
8
µs
td off
Turn-off delay time
-
11
30
µs
tf
Fall time
-
5
12
µs
VIS: 5 V ⇒ 0 V
1 In this condition the protection circuit is latched. To reset the latch the protection pin must be taken low. Refer to PROTECTION SUPPLY
CHARACTERISTICS.
July 2002
5
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
BUK135-50L
CAPACITANCES
Tmb = 25 ˚C; f = 1 MHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Ciss
Input capacitance
VDS = 25 V; VIS = 0 V
-
710
1050
pF
Coss
Crss
Output capacitance
VDS = 25 V; VIS = 0 V
-
370
550
pF
Reverse transfer capacitance
VDS = 25 V; VIS = 0 V
-
26
40
pF
Cpso
Protection supply pin
capacitance
VPS = 5 V
-
22
-
pF
Cfso
Flag pin capacitance
VFS = 5 V; VPS = 0 V
-
12
-
pF
PD%
120
Normalise Power Derating
80
ID / A
BUK135-50L
70
100
VIS / V =
7
60
6
80
50
5
60
40
4
30
40
3
20
20
10
0
0
0
20
40
60
80
100
120
140
0
O
2
4
6
8
10
12
14
16
VDS / V
Tmb / C
Fig.4. Normalised limiting power dissipation.
PD% = 100⋅PD/PD(25˚C) = f(Tmb)
Fig.6. Typical output characteristics, Tj = 25˚C.
ID = f(VDS); parameter VIS; tp = 300 µs & tp < td sc
y
40
ID / A
BUK135-50L
80
ID / A
BUK135-50L
70
VIS / V =
60
30
7
6
50
20
5
40
4
30
10
20
3
10
0
2
0
0
20
40
60
80
100
120
140
0
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
VDS / V
O
Tmb / C
Fig.5. Continuous drain current.
ID = f(Tamb); condition: VIS = 5 V
July 2002
0.2
Fig.7. Typical on-state characteristics, Tj = 25˚C.
ID = f(VDS); parameter VIS; tp = 300 µs
6
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
Normalised R
a
2
BUK135-50L
DS(ON) =
O
f(T j )
Tj (TO) C
200
BUK135-50L
Data below 4V is for
information only. All
spec. values are for
normal operation at
4V and above.
1.8
190
1.6
1.4
180
1.2
1
0.8
170
0.6
0.4
160
0.2
0
150
-50
0
50
100
150
3
O
Tj / C
RDS(ON) / mOhm
5
6
VPS / V
7
8
Fig.11. Typical overtemperature protection threshold.
Tj(TO) = f(VPS); conditions: VIS = 5 V
Fig.8. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25˚C = f(Tj); ID = 10 A; VIS = 4.4 V
50
4
BUK135-50L
100E-6
IDSS / A
BUK135-50L
max.
10E-6
40
1E-6
30
max.
typ.
typ.
100E-9
20
10E-9
10
1E-9
0
0
1
2
3
4
VIS / V
5
6
7
-50
8
ID / A
y
100
150
O
Fig.12. Typical drain source leakage current.
IDSS = f(Tj); conditions: VDS = 40 V; VPS = VIS = 0 V
BUK135-50L
70
50
Tj / C
Fig.9. Typical on-state resistance, Tj = 25˚C. RDS(ON)
= f(VIS); conditions: ID = 10 A; VPS = 4 V; tp = 300 µs
80
0
3.5
IIS / mA
BUK135-50L
3.0
VDS = 13V
60
2.5
50
2.0
40
1.5
30
Latched
1.0
20
Unlatched
0.5
10
0
0
0
1
2
3
4
5
6
7
8
0
VIS / V
Fig.10. Typical transfer characteristics, Tj = 25˚C.
ID = f(VIS); conditions: VPS ≥ 4 V tp = 300 µs
July 2002
1
2
3
VIS / V
4
5
6
7
Fig.13. Typical DC input characteristics, Tj = 25˚C.
IIS & IISL = f(VIS); normal operation & protection latched
7
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
10E-3
BUK135-50L
BUK135-50L
IIS & I ISL
2.5
IDSP / mA
BUK135-50L
IISL
2.0
1E-3
1.5
1.0
00E-6
IDSP is constant from Vds = 2V to 40V
0.5
IIS
10E-6
0
-50
0
50
O
Tj / C
100
150
0
VIS(TO) / V
2
VDS / V
3
4
5
Fig.17. Off state drain current characteristic.
IDSP = f(VDS); conditions: Tj = 25˚C; VPS = 5 V; VIS = 0 V
Fig.14. Typical DC input currents. IIS & IISL = f(Tj);
normal & latched; conditions: VIS = 5 V; VPS = 5 V
3.0
1
BUK135-50L
2.5
BUK135-50L
IDSP / mA
2.5
2.0
2.0
max .
1.5
typ.
1.5
1.0
1.0
min.
0.5
0.5
0.0
-50
0
50
100
0
150
0
O
Tj / C
Fig.15. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
10
2
3
4
VPS / V
5
6
7
8
Fig.18. Off state drain current vs protection supply.
IDSP = f(VPS); Tj = 25˚C; VDS = 13 V; VIS = 0 V
BUK135-50L
IIS / mA
1
IDSP / mA
BUK135-50L
2.5
8
6
2.0
4
2
1.5
0
0
2
4
VIS / V
6
-50
8
50
O
100
150
Tj / C
Fig.16. Typical input clamping characteristic.
II = f(VIS); normal operation, Tj = 25˚C
July 2002
0
Fig.19. Typical off state drain current IDSP = f(Tj);
conditions: VDS = 13 V; VPS = 5 V; VIS = 0 V
8
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
2
VDSF / V
BUK135-50L
BUK135-50L
3.0
VPSR / V
BUK135-50L
2.8
Normal load
2.6
2.4
typ.
2.2
2.0
1
1.8
Open circuit load
1.6
1.4
1.2
1.0
0
-50
0
50
100
-50
150
0
50
100
150
O
O
Tj / C
Tj / C
Fig.23. Typical protection reset voltage.
VPSR = f(Tj); tlr = 100 µs
Fig.20. Open circuit detection threshold voltage.
VDSF = f(Tj); VPS ≥ 4 V ; VIS = 0 V
VISF / V
BUK135-50L
10E-6
1.0
BUK135-50L
IFS / A
Normal operation
VPS = 0 or 5V
max.
1E-6
typ.
typ.
0.5
Open circuit detection
00E-9
10E-9
0
-50
0
50
100
150
-50
O
0
Tj / C
IPS / mA
100
150
Fig.24. Typical flag characteristics. IFS = f(Tj);
fault & overload operation; VIS = 5 V; VFS = 5 V
Fig.21. Open circuit input threshold voltage.
VISF = f(Tj); VPS ≥ 4 V ; ID = 100 µA
2
50
O
Tj / C
BUK135-50L
4.0
VPSF / V
BUK135-50L
3.8
3.6
1
3.4
3.2
3.0
0
0
1
2
3
4
VPS / V
5
6
7
-50
8
50
O
100
150
Tj / C
Fig.22. Typical DC protection supply characteristics.
IPS = f(VPS); normal or overload operation; Tj = 25 ˚C
July 2002
0
Fig.25. Typical protection threshold voltage.
VPSF = f(Tj); VDS = 5 V ; IF = 100 µA
9
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
BUK135-50L
V(CL)DSR
VDS
VII
VDD
VDD
+
0
L
ID
VIS
0
RI = RIS
-
D
TOPFET
RF
P
F
I
P
F
I
VIS
-ID/100
P
D.U.T.
P
S
RIS
R 01
shunt
S
Fig.26. Clamping energy test circuit, RIS = 100 Ω.
EDSM = 0.5 ⋅ LID2 ⋅ V(CL)DSR /(V(CL)DSR − VDD )
EDSM / J
1.2
TOPFET
VDS
+ VPS
0
D
RI
Fig.29. Test circuit for resistive load switching times.
VIS = 5 V
BUK135-50L
16
BUK135-50L
VIS & V DS / V
VDS
14
1.0
O
12
25 C
0.8
10
0.6
8
0.4
VIS
6
O
150 C
4
0.2
2
0
0
0.1
1
L / mH
10
0
100
Fig.27. Typical non-repetitive clamping energy.
EDSM = f(L); conditions: VIS = 0 V
4
ID / A
5
10
15
20
25
30
Time / µs
35
40
45
50
Fig.30. Typical switching waveforms, resistive load.
RL = 10 Ω; adjust VDD to obtain ID = 1.5 A; Tj = 25˚C
BUK135-50L
65
VDSS / V
BUK135-50L
ID =
3
4A
2
10mA
1
0
60
50
60
VDS / V
70
-50
50
O
100
150
Tj / C
Fig.31. Overvoltage clamping characteristic.
VDS = f(Tj); conditions: VIS = 0 V; tp ≤ 300 µs
Fig.28. Typical clamping characteristic, 25˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 300 µs
July 2002
0
10
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
80
ID / A
BUK135-50L
BUK135-50L
10000
Capacitance / pF
BUK135-50L
70
60
max.
Ciss
1000
50
typ.
40
Coss
30
100
min.
20
Crss
10
0
-50
0
50
100
10
150
0
O
Tj / C
IS / A
20
VDS / V
30
40
50
Fig.34. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VIS = 0 V; f = 1 MHz
Fig.32. Typical overload current, VDS = 5 V.
ID = f(Tj); conditions: VIS = 5 V; VPS = 4 V; tp = 300 µs
15
10
BUK135-50L
Zth / ( K / W )
BUK135-50L
1E+00
0.5
10
1E+01
0.2
0.1
0.05
PD
tp
0.02
T
5
0
0.5
1
1E-06
VSD / V
1E-05
1E-04
1E-03
1E-02
1E-01
1E-03
1E+00 1E+01
t/s
Fig.33. Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V; tp = 300 µs
July 2002
1E-02
T
0
0
1E-01
D = tp
Fig.35. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
11
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
BUK135-50L
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D2-PAK); 5 leads
(one lead cropped)
SOT426
A
A1
E
D1
mounting
base
D
HD
3
1
2
4
e
e
Lp
5
b
e
c
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
1.70
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
SOT426
Fig.36. SOT426 surface mounting package1, centre pin connected to mounting base.
1 Epoxy meets UL94 V0 at 1/8". Net mass: 1.5 g.
For soldering guidelines and SMD footprint design, please refer to Data Handbook SC18.
July 2002
12
Rev 1.100
Philips Semiconductors
Product Specification
Logic level TOPFET
SMD version of BUK124-50L
BUK135-50L
DEFINITIONS
DATA SHEET STATUS
DATA SHEET
STATUS1
PRODUCT
STATUS2
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for
product development. Philips Semiconductors reserves the right to
change the specification in any manner without notice
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in
order to improve the design, manufacturing and supply. Changes will
be communicated according to the Customer Product/Process
Change Notification (CPCN) procedure SNW-SQ-650A
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design.
2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is
available on the Internet at URL http://www.semiconductors.philips.com.
July 2002
13
Rev 1.100