KI MI fo r Co nf id en tia l Re le a se MT6226 GSM/GPRS Baseband Processor Technical Brief Revision 1.01 MT K Sep 12, 2005 Revision Date 1.00 Aug 26, 2005 First Release 1.01 Sep 12, 2005 MI Revision History Revision 1.01 KI MT6226 GSM/GP RS Baseband Processor Technical Brief Co mments MT K Co nf id en tia l Re le a se fo r Typo fixed 2/33 MediaTek Inc. Confidential MI TABLE OF CONTENTS Revision 1.01 KI MT6226 GSM/GP RS Baseband Processor Technical Brief Revision History ...................................................................................................................................... 2 1. System Overvie w............................................................................................................................... 4 Platform Feature ............................................................................................................................................................................7 MODEM Features.........................................................................................................................................................................9 Multi-Media Features.................................................................................................................................................................10 General Description ....................................................................................................................................................................12 fo r 1.1 1.2 1.3 1.4 2 ProductDescription ........................................................................................................................ 14 Re le a se Pin Outs.........................................................................................................................................................................................14 Top Marking Definit ion .............................................................................................................................................................17 DC Characteristics ......................................................................................................................................................................18 Pin Description ............................................................................................................................................................................19 Power Description.......................................................................................................................................................................27 MT K Co nf id en tia l 2.1 2.2 2.3 2.4 2.5 3/33 MediaTek Inc. Confidential 1. System Overview Typical application is shown in Figure 1. Multi-med ia Subsystem The MT6226 mu lti-media subsystem provides connection to CMOS/CCD image sensor and supports resolution up to VGA. With its advanced image signal and data processing technology, MT6226 allo ws efficient processing of image and video data. It also has built-in JPEG CODEC and MPEG-4/ H.263 CODEC, thus enabling real-t ime creation and playback of high-quality images and video. In addition to advanced image and video features, MT6226 also utilizes high resolution DA C, d igital audio, and audio Time Clock, PWM, Serial LCD Controller, and General Purpose Programmable I/Os. For connectivity and data storage, the MT6226 supports UART, IrDA, USB 1.1 Slave and MMC/SD/MS/MS Pro. Furthermore, for large amount of data transfer, h igh performance DMA (Direct Memory Access) and hardware flow control are implemented, which great ly enhances the performance and reduces MCU processing load. Audio Interface Using a highly integrated mixed-signal Audio Front-End, the MT6226 architecture allo ws for easy audio interfacing with direct connection to the audio transducers. The audio interface integrates D/A and A/D Converters for Vo ice band, as well as high resolution Stereo D/A Converters for Audio band. In addition, MT6226 also provides Stereo Input and Analog Mux. Co nf id en tia l synthesis technology to provide superior audio features for all future mu lti-media needs. To provide comp lete user interface, MT6226 b rings together all the necessary peripheral blocks for mu lti-media GSM/GPRS phone. The peripheral b locks consists of the Keypad Scanner with the capability to detect multip le key presses, SIM Controller, Alerter, Real fo r handheld multi-med ia. User Interface Re le a se The revolutionary MT6226 is a lead ing edge single-chip solution for GSM/GPRS mobile phones targeting the emerg ing applications in dig ital audio and video. Based on 32-bit A RM7EJ-STM RISC processor, MT6226 not only features high performance GPRS Class 12 MODEM, but also provides comprehensive and advanced solutions for Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief In order to provide more flexibility and bandwidth for mu lti-media products, an additional 18 -bit parallel interface is incorporated. This interface enables connection to LCD modules as well as connection to NAND flash MT6226 supports AMR codec to adaptively optimize speech and audio quality. Moreover, HE-AAC codec is devices to allow fo r mu lti-media data storage capabilities. implemented to deliver CD-quality audio at low bit rates. External Memory Interface Overall, MT6226’s audio features provide a rich platform for mu lti-media applications. Providing the greatest capacity for expansion, MT6226 supports up to 8 state-of-the-art devices through its 16-b it host interface. Devices such as burst/page mode Flash, page mode SRAM, Pseudo SRAM, Co lor/Parallel LCD, MT K and mult i-med ia co mpanion chip are all supported through this interface. To minimize power consumption and ensure low noise, this interface is designed for flexible I/ O voltage and allows lo wering of supply voltage down to 1.8V. The driving strength is configurable for signal integrity adjustment. The data bus also employs retention technology to prevent the bus from floating during turn over. Radio Interface MT6226 integrates a mixed-signal Baseband front-end in order to provide a well-organized radio interface with flexib ility for efficient customization. It contains gain and offset calibration mechanis ms, and filters with programmab le coefficients for comprehensive compatibility control on RF modules. This approach also allo ws the usage of a high resolution D/A Converter for controlling VCXO or crystal, thus reducing the need for expensive TCVCXO. MT6226 achieves great MODEM performance by utilizing 14-bit h igh resolution A/D 4/33 MediaTek Inc. Confidential Converter in the RF downlink path. Fu rthermore, to reduce the need for extra external current-driv ing component, the driving strength of some BPI outputs is designed to be configurable. Power Management The MT6226 offers various low-power features to help reduce system power consumption. These features include Pause Mode of 32KHz clocking at Standby State, Power Down Mode for individual peripherals, and Processor Sleep Mode. In addit ion, MT6226 is also fabricated in advanced low leakage CMOS process, hence providing an overall u ltra low leakage solution. Package Re le a se The JTA G interface enables in-circuit debugging of software program with the ARM 7EJ-S core. With this standardized debugging interface, the MT6226 prov ides developers with a wide set of options in choosing ARM development kits fro m different third party vendors. fo r Debug Function Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief MT K Co nf id en tia l The MT6226 device is offered in a 13mm×13mm, 296-ball, 0.65 mm pitch, TFBGA package. 5/33 MediaTek Inc. Confidential SRAM PSRAM FLASH IMAGE SENSOR NAND FLASH LCD JTAG 18-BIT PARALLEL INTERFACE SPEECH/AUDIO INPUT AFC SPEECH/AUDIO OUTPUT SYSCLK Re le a se MT6227 HIFISTEREO OUTPUT B2PSI AUXADC PWM RF MODULE BPI BSI CHIP UID ALERTER POWER MANAGEMENT CIRCUITRY SUPPLY VOLTAGES SIM USIM SERIAL LCD USB MMC/SD/MS MSPRO Co nf id en tia l I2S TCVCXO APC TX I/Q RX I/Q FM STEREO RADIO INPUT AUDIO DAC IMAGE INPUT fo r DEBUGGER Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief SERIAL LCD UART IRDA KEYPAD 1 4 2 5 3 6 7 8 0 9 # * MT K Figure 1 Typical application of MT6226 6/33 MediaTek Inc. Confidential Processor Sleep Mode Pause Mode of 32KHz clocking at Standby State fo r 7-channel Au xiliary 10-b it A/D Converter for charger and battery monitoring and photo sensing Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief Test and Debug Built-in dig ital and analog loop back modes for both Audio and Baseband Front-End MT K Co nf id en tia l JTA G port for debugging embedded MCU Re le a se DAI port co mply ing with GSM Rec.11.10 8/33 MediaTek Inc. Confidential 1.2 MODEM Features Radi o Interface and B aseband Front End GSM channel coding, equalization and A5/1 and A5/2 ciphering GM SK modulator with analog I and Q channel outputs fo r GPRS GEA 1 and GEA 2 ciphering 10-bit D/A Converter for uplink baseband I and Q signals Programmab le GSM/ GPRS Modem Packet Switched Data with CS1/ CS2/ CS3/CS4 coding schemes Calibrat ion mechanism o f offset and gain mis match for baseband A/D Converter and D/A Converter 10-bit D/A Converter for Automatic Power Control 13-bit h igh resolution D/A Converter for Automatic Frequency Control Programmab le Radio RX filter Re le a se 14-bit high resolution A/D Converter for downlink baseband I and Q signals Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief GSM Circu it Switch Data GPRS Class 12 Voice Interface and Voice Front End Two microphone inputs sharing one low noise amp lifier with programmable gain and automatic gain control (A GC) mechanis m Voice power amp lifier with programmable gain 2nd order Sig ma-Delta A/D Converter for voice uplink path Co nf id en tia l 2 Channels bi-directional Baseband Serial Interface (BSI) with 3-wire or 4-wire control D/A Converter for voice down lin k path 10-Pin Baseband Parallel Interface (BPI) with Supports half-duple x hands-free operation programmab le driving strength Co mpliant with GSM 03.50 Multi-band support Voice and Modem CODEC Dial tone generation Voice Memo Noise Reduction Echo Suppression / Echo Cancellation Advanced Sidetone Oscillat ion Reduction Dig ital sidetone generator with programmab le gain MT K Two programmab le acoustic compensation filters GSM/GPRS quad vocoders for adaptive mult irate (AMR), enhanced full rate (EFR), fu ll rate (FR) and half rate (HR) FR erro r concealment 9/33 MediaTek Inc. Confidential Multi-Media Features LCD/ NAND Flash Interface Automatic focus control 18-bit Parallel Interface supports 8/16 bit NAND flash and 8/9/16/18 b it Parallel LCD Automatic White Balance Control Edge Enhancement Support 8/16 bit NAND Flash Controller with 1 -bit ECC correction for mass storages Flexib le I/ O voltage of 1.8V ~ 2.8V JPEG Decoder 2 Chip selects available for high-density NAND Serial LCD Interface with 8/9 bit fo rmat support LCD Controller Hardware accele rated display Supports simultaneous connection to up to 2 parallel LCD and 1 serial LCD modules Supports format: RGB332, RGB444, RGB565, RGB666, RGB888 modes Supports all possible YUV fo rmats, including grayscale format Supports all DC/AC Huffman table parsing Supports all quantization table parsing Supports restart interval Supports SOS, DHT, DQT and DRI marker parsing Co nf id en tia l Supports LCD panel maximu m resolution up to 800x600 at 16bpp ISO/ IEC 10918-1 JPEG Baseline and Progressive Re le a se flash device fo r 1.3 Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief Supports hardware display rotation Capable of co mb ining display memo ries with up to 4 blending layers IEEE Std 1180-1990 IDCT Standard Co mp liant Supports progressive image processing to minimize storage space requirement Supports reload-able DMA for VLD stream JPEG Encoder Accelerated Gamma correction with programmab le gamma table. Image Signal Processor ISO/ IEC 10918-1 JPEG baseline mode ISO/ IEC 10918-2 Co mpliance 8/10 bit Bayer format image input Supports YUV422 and grayscale formats YUV422 format image input Standard DC and A C Huffman tables Capable of p rocessing image of size up to VGA Provides 14 levels of encode quality Lens shading compensation Image Data Processing Defect pixel correct ion Optical black correct ion Horizontal scaling in averaging method Color Correction Matrix Vertical scaling in bilinear method Gamma Co rrection Simu ltaneous scaling for MPEG-4 encode and LCD display MT K Synchronous flash light control High throughput hardware scalar capable of tailoring image to arbitrary size Automatic Exposure Control 10/33 MediaTek Inc. Confidential Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief Line drawing: normal line, dotted line Pixel format transform Font caching: normal font, Italic font Boundary padding Supports 16-bpp RGB565 and 8-bpp index color modes with one color palette inside Accelerated Pixel-based luminance/chrominance Co mmand queue with 32 levels processing: hue/saturation/intensity/color adjustment, Gamma correction and grayscale/invert/sepia-tone effects Hardware accelerated image edit ing MPEG-4/ H.263 CODEC Hardware Video CODEC ISO/ IEC 14496-2 simple profile: decode @ level 0/1/2/ 3 encode @ level 0 Audi o CODEC Wavetable synthesis with up to 64 tones Advanced wavetable synthesizer capable of generating simulated stereo Re le a se Accelerated Programmab le Spatial Filtering : Linear filter, Non-linear filter and Multi-pass artistic effects fo r YUV and RGB co lor space conversion Wavetable including GM fu ll set of 128 instruments and 47 sets of percussions PCM Playback and Record Dig ital Audio Playback HE-AAC decode support Audi o Interface and Audio Front End Supports I2S interface Co nf id en tia l Supported visual tools for decoder: I-VOP, P -VOP, AC/DC pred iction, 4-M V, Unrestricted M V, Error Resilience, Short Header Error Resilience for decoder: Slice Resynchronization, Data Partit ioning, Reversible VLC Supported visual tools for encoder: I-VOP, P -VOP, Half-pel, DC predict ion, Unrestricted M V, Reversible VLC, Short Header High resolution D/A Converters for Stereo Audio playback Stereo analog input for stereo audio source Analog mult iplexer for Stereo Audio Stereo to Mono Conversion FM radio recording Supports encoding motion vector of range up to –64/+63.5 pixels ITU-T H.263 profile 0 @ level 10 AAC/HE-AAC/AMR audio decode support AMR audio encode support 2D Accelerator MT K Rectangle fill BitBlt: mult i-BitBlt without transform, 7 rotate, mirror (transparent) Bit Blt Alpha blending 11/33 MediaTek Inc. Confidential 1.4 General Description Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief fo r Figure 2 details the block diagram of MT6226. Based on a dual-processor architecture, MT6226 integrates both an ARM7EJ -S core and a digital signal processor core. ARM 7EJ-S is the main processor that is responsible for running high-level GSM/GPRS protocol software as well as mu lti-media applications. The digital signal processor handles the low-level MODEM as well as advanced audio functions. Except for some mixed-signal circuit ries, the other build ing blocks in MT6226 are connected to either the microcontroller or the digital signal processor. Specifically, MT6226 consists of the following subsystems: Re le a se Microcontroller Un it (M CU) Subsystem - includes an ARM7EJ-S RISC processor and its accompanying memo ry management and interrupt handling logics. Dig ital Signal Processor (DSP) Subsystem - includes a DSP and its accompanying memory, memo ry controller, and interrupt controller. MCU/ DSP Interface - where the MCU and the DSP exchange hardware and software informat ion. Microcontroller Peripherals - includes all user interface modules and RF control interface modules. Microcontroller Coprocessors - runs computing-intensive processes in place of M icrocontroller. DSP Peripherals - hard ware accelerators for GSM/GPRS channel codec. Multi-med ia Subsystem - integrates several advanced accelerators to support multi-media applications. Co nf id en tia l Voice Front End - the data path for converting analog speech fro m and to digital speech. Audio Front End - the data path for converting stereo audio from stereo audio source Baseband Front End - the data path for converting digital signal from and to analog signal of RF modules. Timing Generator - generates the control signals related to the TDMA frame t iming. Power, Reset and Clock subsystem - manages the power, reset, and clock d istribution inside MT6226. MT K Details of the individual subsystems and blocks are described in following Chapters. 12/33 MediaTek Inc. Confidential MIC-0 MIC-1 ADC PATCH UNIT DSP COPROCES SOR TRAP UNIT MEMORY DAC DSP COPROCES SOR AUDIO PATH + AUDIO-L DAC AUDIO-R DAC DSP STEREO-L MCU/DSP INTERFACE RX-I ADC ADC TX-I DAC TX-Q DAC BRIDGE BASEBAND PATH INTERRUPT CONTROL AUX ADC ADC DAC AFC APC DAC APC SERIAL RF CONTROL BSI PARALLEL RF CONTROL SYSTEM CLOCK 13/26MHZ DMA CONTROL ON-CHIP S RA M 2D ENGINE Co nf id en tia l AFC BOOT ROM ARM7EJ-S AUX ADC USB USB EXTERNAL MEMORY INTERFACE FLASH SRAM PSRAM LCD CONTROLLER NAND LCD NAND FLASH INTERFA CE GRAPHIC MEMORY CONTROLLER IMAGE POST PROC IMAGE DMA DSP COPROCES SOR INTERRUPT CONTROL Re le a se STEREO-R RX-Q fo r + VOICE Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief TDMA TIMER GIF DECODE MPEG-4 VIDEO CODEC JPEG CODEC IMAGE RESIZER IMAGE SIGNAL PROC IMAGE SENSOR I2C IMAGE SENSOR BPI GPT CLOCK GEN 32K OSC 32KHZ CRYSTAL RTC WAKE UP SIM WDT RESET GPIO ALERTER KEYPAD SCAN PWM USER INTERFACE B2PSI SERIAL LCD IRDA MMC SD/MS MS PRO UART MT6227 SERIALPORT CONNECTIVITY MT K Figure 2 MT6226 block diagram. 13/33 MediaTek Inc. Confidential 2 2.1 Product Description Pin Outs Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief fo r One type of package for this product, TFBGA 13mm* 13mm, 296-ball, 0.65 mm pitch Pac kage, is offered. MT K Co nf id en tia l Re le a se Pin outs and the top view are illustrated in Figure 3 for this package. Outline and dimension of package is illustrated in Figure 4, while the definition of package is shown in Table 1. 14/33 MediaTek Inc. Confidential Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A NC SYSCL K NC AFC_B YP AUXA DIN6 AUXA DIN3 AVDD_ RFE BUPAI N BDLAI N AU_VI N1_P AGND _AFE AU_O UT0_P AVSS_ BUF AU_F MINR AU_M OUTR VSS33 B XOUT AVDD_ RTC AVDD_ PLL AFC AUXA DIN5 AUXA DIN2 APC BUPAI P BDLAI P AU_VI N1_N AU_VR EF_P AU_O UT0_N AVDD_ BUF AU_F MINL AU_M OUTL VSS33 _IS C BBWA KEUP XIN AVSS_ PLL AUX_R EF AUXA DIN4 AUXA DIN1 AVSS_ RFE BUPA QN BDLA QN AU_VI N0_N AU_VR EF_N AU_MI CBIAS _P AU_M_ BYPR AU_M_ BYPL AVDD_ MBUF VDDK GPIO4 D VDDK VSS33 TESTM ODE NC PLL_O UT AUXA DIN0 AVDD_ GSMR FTX BUPA QP BDLA QP AU_VI N0_P AVDD_ AFE AU_MI CBIAS _N AU_R BIAS AVSS_ MBUF NC KROW 1 E JTMS JT DI JTCK JTRST # IBOOT NC NC AVSS_ GSMR FTX AGND _RFE AVSS_ AFE VDDK VSS33 NC VSS33 _IS VDD33 _IS KROW 4 F VDD33 BPI_B US1 BPI_B US0 JRTCK JTDO NLD17 G BPI_B US6 BPI_B US5 BPI_B US4 BPI_B US3 BPI_B US2 NLD16 H BSI_C S0 VSS33 BPI_B US9 BPI_B US8 BPI_B US7 CMDA T9 CMPC LK CMMC LK CMHR EF J LSDA LSA0 LSCK BSI_C LK BSI_D ATA CMDA T8 NLD8 NLD9 K VDD33 LPCE1 # LSCE1 # LSCE0 # NC CMDA T7 NLD11 L LWR# LPA0 LRD# LRST# LPCE0 # CMDA T6 NLD13 M VDDK VSS33 NLD5 NLD6 NLD7 CMDA T5 CMDA T4 N NLD0 NLD1 NLD2 NLD3 NLD4 P NRE# NWE# NALE NCLE NRNB R VDD33 PWM2 PWM1 NCE# MIRQ EA14 EA10 EA7 NC EA0 EWAIT ECS4# ECS0# T SRCL KENA SRCL KENAI SRCL KENA N ALERT ER EA18 EA15 EA11 EA8 EA4 EA1 EPDN# ECS5# U SYSRS T# GPIO0 EINT1 EA23 EA19 EA16 EA12 VSS33 _EMI EA5 EA2 EADV# V EINT0 EINT3 VSS33 _EMI EA22 EA20 VSS33 _EMI EA13 VDDK EA6 VSS33 _EMI W EINT2 EA25 EA24 VDD33 _EMI EA21 EA17 VDD33 _EMI EA9 VDD33 _EMI 1 2 3 4 5 6 7 8 9 19 GPIO9 GPIO8 GPIO5 A GPIO7 GPIO6 DAISY NC B DAIRS T DAIPC MIN C DAICL K DAIPC MOUT KROW 0 D KROW 3 KROW 2 VDD33 E Re le a se fo r 18 KCOL2 KCOL1 KCOL 0 KROW 5 F IRDA_ TXD IRDA_ PDN KCOL6 KCOL 5 KCOL4 G CMVR EF URXD3 UTXD3 IRDA_ RXD VSS33 VDDK H NLD10 CMRS T NC UCTS1 URT S1 URXD2 UTXD2 J NLD12 CMPD N SIMVC C SIMSE L SIMDA TA URXD1 UTXD1 K NLD14 NLD15 CMDA T0 GPIO2 GPIO3 SIMCL K SIMRS T VDD33 L CMDA T3 CMDA T2 CMDA T1 VDD33 _MC MCWP MCINS MCCK GPIO1 M MCDA 0 MCDA 1 MCDA 2 MCDA 3 MCPW RON N VDD33 _USB USB_D P USB_D M VSS33 _MC MCCM 0 P ELB# ED1 ED0 MFIQ WATC HDOG VSS33 _EMI R ECS1# EUB# ED13 ED11 ED3 VDD33 _EMI ED2 T ECS6# ECS2# ERD# ED14 VSS33 _EMI ED8 ED5 ED4 U ECLK VSS33 _EMI ECS3# VSS33 _EMI ED15 VDDK ED9 ED6 VSS33 _EMI V EA3 VDD33 _EMI ECS7# VDD33 _EMI EWR# VDD33 _EMI ED12 ED10 VDD33 _EMI ED7 W 10 11 12 13 14 15 16 17 18 19 Co nf id en tia l KCOL3 MT6226 TFBGA Top-View MT K Figure 3 Top View of MT6226 TFBGA 13mm* 13mm, 296-ball, 0.65 mm pitch Pac kage 15/33 MediaTek Inc. Confidential $ % & # fo r #( #) #* # #$ #% #& # ## #' ( ) * Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief Re le a se 26 " T6226 ! , / . ! - # Co nf id en tia l + Figure 4 Outlines and Dimension of TFBGA 13mm*13mm, 296-ball, 0.65 mm pitch Pac kage Body Size Ball Count Ball Pitch Ball Dia. Package Thk. Stand Off Substrate Thk. D E N e b A (Max.) A1 C 13 13 296 0.65 0.3 1.2 0.21 0.36 MT K Table 1 Defin ition of TFBGA 13mm* 13mm , 296-ball, 0.65 mm pitch Pac kage (Unit: mm) 16/33 MediaTek Inc. Confidential Top Marking Definition fo r 2.2 Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief M T6 2 26 A D DD D -# # # LL L L L MT K Co nf id en tia l S Re le a se MT6226A: Part No. DDDD: Date Code ###: Subcontractor Code LLLLL: Lot No. S: Special Code 17/33 MediaTek Inc. Confidential 2.3 2.3.1 DC Characteristics Absolute Maximum Ratings Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief fo r Prolonged exposure to absolute maximu m ratings may reduce device reliab ility. Functional operation at these maximu m ratings is not imp lied. Symbol Min Max Unit IO power supply VDD33 -0.3 VDD33+0.3 V I/O input voltage VDD33I -0.3 VDD33+0.3 V Operating temperature Topr -20 80 Celsius Storage temperature Tstg -55 125 Celsius MT K Co nf id en tia l Re le a se Item 18/33 MediaTek Inc. Confidential 2.4 Pin Description Ball Name 13X13 Dir Description Mode0 Mode1 Mode2 KI Mode3 fo r JTAG Port JTRST# JTCK JTDI JTMS JTDO I I I I O JTAG JTAG JTAG JTAG JTAG F4 JRTCK O F3 F2 G5 G4 G3 G2 G1 H5 H4 H3 BPI_BUS0 BPI_BUS1 BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 O O O O IO IO IO IO IO IO JTAG test port returned clock output RF Parallel Control Unit RF hard-wire control bus 0 RF hard-wire control bus 1 RF hard-wire control bus 2 RF hard-wire control bus 3 RF hard-wire control bus 4 RF hard-wire control bus 5 RF hard-wire control bus 6 RF hard-wire control bus 7 RF hard-wire control bus 4 RF hard-wire control bus 5 Re le a se E4 E3 E2 E1 F5 test port reset input test port clock input test port data input test port mode switch test port data output Revision 1.01 MI MT6226 GSM/GP RS Baseband Processor Technical Brief GPIO10 GPIO11 GPIO12 GPIO13 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 BSI_CS0 BSI_DATA BSI_CLK O O O R3 R2 T4 PWM1 PWM2 ALERTER IO IO IO Pulse width modulated signal 1 GPIO21 PWM1 Pulse width modulated signal 2 GPIO22 PWM2 Pulse width modulated signal for buzzer GPIO23 ALERTER Co nf id en tia l H1 J5 J4 RF Serial Control Unit RF 3-wire interface chip select 0 RF 3-wire interface data output RF 3-wire interface clock output PWM Interface 65MHz 13MHz BSI_CS1 PU/ Rese PD t PD PU PU PU Input Input Input Input 0 0 26MHz 32KHz PD PD PD PD 0 0 0 0 0 0 Input Input Input Input 0 0 0 DSP_GPO0 TBTXFS DSP_GPO1 TBRXEN DSP_GPO2 BTRXFS PD PD PD Input Input Input TDMA_CK TDMA_D1 TDMA_D0 TDMA_FS TBTXEN TDTIRQ TCTIRQ2 TCTIRQ1 PU PU PU PU Input Input Input Input LPCE2# TEVTVAL PU Input NCE1# MCU_TID PU 0 Input Serial LCD/PM IC Interface J3 J2 J1 K4 LSCK LSA0 LSDA LSCE0# IO IO IO IO K3 LSCE1# K2 LPCE1# L5 LPCE0# O L4 L3 L2 L1 LRST# LRD# LPA0 LWR# O O O O IO MT K IO Serial display interface data output Serial display interface address output Serial display interface clock output Serial display interface chip select 0 output Serial display interface chip select 1 output Parallel LCD/Nand-Flash Interface GPIO16 GPIO17 GPIO18 GPIO19 LSCK LSA0 LSDA LSCE0# GPIO20 LSCE1# Parallel display interface chip select 1 GPIO24 LPCE1# output Parallel display interface chip select 0 output Parallel display interface Reset Signal Parallel display interface Read Strobe Parallel display interface address output Parallel display interface Write Strobe 19/33 1 1 1 1 1 MediaTek Inc. Confidential GPIO56 NLD17 GPIO55 NLD16 NLD17 NLD16 NLD15 NLD14 NLD13 NLD12 NLD11 NLD10 NLD9 NLD8 NLD7 NLD6 NLD5 NLD4 NLD3 NLD2 NLD1 NLD0 NRNB IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Parallel LCD/Nand-Flash Data 17 Parallel LCD/Nand-Flash Data 16 Parallel LCD/Nand-Flash Data 15 Parallel LCD/Nand-Flash Data 14 Parallel LCD/Nand-Flash Data 13 Parallel LCD/Nand-Flash Data 12 Parallel LCD/Nand-Flash Data 11 Parallel LCD/Nand-Flash Data 10 Parallel LCD/Nand-Flash Data 9 Parallel LCD/Nand-Flash Data 8 Parallel LCD/Nand-Flash Data 7 Parallel LCD/Nand-Flash Data 6 Parallel LCD/Nand-Flash Data 5 Parallel LCD/Nand-Flash Data 4 Parallel LCD/Nand-Flash Data 3 Parallel LCD/Nand-Flash Data 2 Parallel LCD/Nand-Flash Data 1 Parallel LCD/Nand-Flash Data 0 Nand-Flash Read/Busy Flag P4 NCLE IO Nand-Flash Command Latch Signal P3 NALE IO Nand-Flash Address Latch Signal P2 P1 NWE# NRE# IO IO R4 NCE# IO MCDA7 MCDA6 DSP_TID0 PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD MCU_TID PU 1 MCU_TID PD 2 MCU_TID PD 3 MCU_DID PU MCU_DF PU S MCU_DC PU K Re le a se fo r F6 G6 L11 L10 L9 K11 K9 J11 J10 J9 M5 M4 M3 N5 N4 N3 N2 N1 P5 Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief DSP_TID1 GPIO26 NCLE DSP_TID2 GPIO27 NALE DSP_TID3 Nand-Flash Write Strobe Nand-Flash Read Strobe GPIO28 NWE# GPIO29 NRE# DSP_TID4 DSP_TID5 Nand-Flash Chip select output GPIO30 NCE# DSP_TID6 Co nf id en tia l GPIO25 NRNB Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input SIM Card Interface L18 L17 K15 K16 K17 SIMRST SIMCLK SIMVCC SIMSEL SIMDATA U2 M19 L15 L16 C17 A19 B18 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 B17 A18 A17 U1 SIM card reset output SIM card clock output SIM card supply power control SIM card supply power select SIM card data input/output IO IO IO IO IO IO IO Dedicated GPIO Interface General purpose input/output 0 General purpose input/output 1 General purpose input/output 2 General purpose input/output 3 General purpose input/output 4 General purpose input/output 5 General purpose input/output 6 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 DICK BSI_RFIN DID DIMS DSP_CLK AHB_CLK ARM_CLK GPIO7 GPIO8 GPIO9 IO IO IO General purpose input/output 7 General purpose input/output 19 General purpose input/output 21 GPIO7 GPIO8 GPIO9 SLOW_CK DSPLD1 SCL DSPLD0 SDA DSPLSYN C SYSRST# I MT K O O O O IO GPIO32 SIMSEL PD DSP_GPO3 DSPLCK DSPLD3 DSPLD2 EDICK EDIWS CMFLAS H EDIDAT 0 0 0 Input 0 PD PD PD PD PD PD PD Input Input Input Input Input Input Input PD PD PD Input Input Input Miscellaneous System reset input active low Input 20/33 MediaTek Inc. Confidential T1 WATCHDOG O # SRCLKEN A O N SRCLKEN A O T2 SRCLKENAI IO External TCXO enable output active low External TCXO enable output active high External TCXO enable input E5 IBOOT I Boot Device Configuration Input Keypad Interface Keypad column 6 Keypad column 5 Keypad column 4 Keypad column 3 Keypad column 2 Keypad column 1 Keypad column 0 KCOL6 KCOL5 KCOL4 KCOL3 KCOL2 KCOL1 KCOL0 I I I I I I I F19 E16 E17 E18 D16 D19 KROW5 KROW4 KROW3 KROW2 KROW1 KROW0 O O O O O O Keypad row 5 Keypad row 4 Keypad row 3 Keypad row 2 Keypad row 1 Keypad row 0 External Interrupt Interface V1 U3 W1 V2 R5 R17 EINT0 EINT1 EINT2 EINT3 MIRQ MFIQ I I I I I I External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 Interrupt to MCU Interrupt to MCU External Memory Interface R16 R15 T19 T17 U19 U18 V18 W19 U17 V17 W17 T16 W16 T15 U15 V15 U14 W14 ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ERD# EWR# IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O External memory data bus 0 External memory data bus 1 External memory data bus 2 External memory data bus 3 External memory data bus 4 External memory data bus 5 External memory data bus 6 External memory data bus 7 External memory data bus 8 External memory data bus 9 External memory data bus 10 External memory data bus 11 External memory data bus 12 External memory data bus 13 External memory data bus 14 External memory data bus 15 External memory read strobe External memory write strobe MT K MI SRCLKEN AN GPO0 SRCLKEN A GPIO31 SRCLKEN AI GPO1 Co nf id en tia l G17 G18 G19 F15 F16 F17 F18 1 0 1 fo r T3 Watchdog reset output Re le a se R18 Revision 1.01 KI MT6226 GSM/GP RS Baseband Processor Technical Brief GPIO41 MIRQ GPIO42 MFIQ 21/33 13MHz PD Input PD Input PU PU PU PU PU PU PU Input Input Input Input Input Input Input 0 0 0 0 0 0 32KHz PU PU PU PU PU PU Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input 1 1 MediaTek Inc. Confidential U11 EADV# O R11 V11 R10 T10 U10 W10 T9 U9 V9 R8 T8 W8 R7 T7 U7 V7 R6 T6 U6 W6 T5 U5 V5 W5 V4 U4 W3 W2 EWAIT ECLK EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 EA17 EA18 EA19 EA20 EA21 EA22 EA23 EA24 EA25 O O O O O O O O O O O O O O O O O O O O O O O O O O O O P16 USB_DP IO P17 USB_DM IO P19 N15 N16 MCCM0 MCDA0 MCDA1 IO IO IO External memory chip select 0 External memory chip select 1 External memory chip select 2 External memory chip select 3 External memory chip select 4 External memory chip select 5 External memory chip select 6 External memory chip select 7 External memory lower byte strobe External memory upper byte strobe Power Down Control Signal for PSRAM Address valid for burst mode flash memory External device wait signal Clock for flash memory External memory address bus 0 External memory address bus 1 External memory address bus 2 External memory address bus 3 External memory address bus 4 External memory address bus 5 External memory address bus 6 External memory address bus 7 External memory address bus 8 External memory address bus 9 External memory address bus 10 External memory address bus 11 External memory address bus 12 External memory address bus 13 External memory address bus 14 External memory address bus 15 External memory address bus 16 External memory address bus 17 External memory address bus 18 External memory address bus 19 External memory address bus 20 External memory address bus 21 External memory address bus 22 External memory address bus 23 External memory address bus 24 External memory address bus 25 USB Interface USB D+ Input/Output GPIO54 GPIO53 GPIO52 GPIO40 ECS4# ECS5# ECS6# ECS7# GPO2 EPDN# MT K MI KI O O O O O O O O O O O 6.5MHz 26MHz Re le a se ECS0# ECS1# ECS2# ECS3# ECS4# ECS5# ECS6# ECS7# ELB# EUB# EPDN# Co nf id en tia l R13 T13 U13 V13 R12 T12 U12 W12 R14 T14 T11 Revision 1.01 fo r MT6226 GSM/GP RS Baseband Processor Technical Brief GPO3 GPO4 EA24 EA25 13MHz PU PU PU PU 1 1 1 1 1 1 1 1 1 1 0 1 32KHz Input 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB D- Input/Output Memory Card Interface SD Command/MS Bus State Output SD Serial Data IO 0/MS Serial Data IO SD Serial Data IO 1 22/33 MediaTek Inc. Confidential IO IO O M16 M17 M18 MCPWRON MCWP MCINS O I I SD Serial Data IO 2 SD Serial Data IO 3 SD Serial Clock/MS Serial Clock Output SD Power On Control Output SD Write Protect Input SD Card Detect Input K18 K19 J16 J17 J18 J19 H15 H16 H17 URXD1 UTXD1 UCTS1 URTS1 URXD2 UTXD2 URXD3 UTXD3 IRDA_RXD I O I O IO IO IO IO IO UART Interface UART 1 receive data UART 1 transmit data UART 1 clear to send UART 1 request to send UART 2 receive data UART 2 transmit data UART 3 receive data UART 3 transmit data IrDA receive data G15 IRDA_TXD IO IrDA transmit data G16 IRDA_PDN IO IrDA Power Down Control Digital Audio Interface GPIO35 GPIO36 GPIO33 GPIO34 GPIO37 PU PU PU PU PU Input 1 Input 1 Input Input Input Input Input PU Input PU Input DSPLD7 DSPLD6 PU PD Input Input DSPLD5 PU Input DSPLD4 BFEPRBO PU PU Input Input PD PD Input Input Input Input Input Outp ut Input Input Input Input Input Input Input Input Input Input URXD2 UTXD2 URXD3 UTXD3 IRDA_RX D GPIO38 IRDA_TX D GPIO39 IRDA_PD N UCTS3 URTS3 EINT7 EINT5 UCTS2 GPIO43 DAICLK GPIO44 DAIPCMO UT GPIO45 DAIPCMI N GPIO47 DAIRST GPIO46 DAISYNC D17 D18 DAICLK IO DAIPCMOUT IO C19 DAIPCMIN IO DAI pcm data input C18 B19 DAIRST DAISYNC IO IO DAI reset signal input DAI frame synchronization signal output Image Sensor Interface J12 K12 H12 H11 H9 H10 CMRST CMPDN CMVREF CMHREF CMPCLK CMMCLK IO IO I I I O Image sensor reset signal output GPIO48 CMRST Image sensor power down control GPIO49 CMPDN Sensor vertical reference signal input Sensor horizontal reference signal input Image sensor pixel clock input Image sensor master clock output H8 J8 K8 L8 M8 M9 M10 M11 M12 L12 CMDAT9 CMDAT8 CMDAT7 CMDAT6 CMDAT5 CMDAT4 CMDAT3 CMDAT2 CMDAT1 CMDAT0 I I I I I I I I IO IO Image sensor data input 9 Image sensor data input 8 Image sensor data input 7 Image sensor data input 6 Image sensor data input 5 Image sensor data input 4 Image sensor data input 3 Image sensor data input 2 Image sensor data input 1 Image sensor data input 0 MT K PU PU PU PU Co nf id en tia l DAI clock output DAI pcm data out GPIO15 MCWP GPIO14 MCINS MI KI MCDA2 MCDA3 MCCK Re le a se N17 N18 N19 Revision 1.01 fo r MT6226 GSM/GP RS Baseband Processor Technical Brief GPIO50 CMDAT1 GPIO51 CMDAT0 URTS2 MCDA5 MCDA4 EINT6 EINT4 PD PD Analog Interface 23/33 MediaTek Inc. Confidential Audio analog output left channel Audio analog output right channel Audio DAC bypass pin FM radio analog input left channel FM radio analog input right channel Audio DAC bias resistor pin Audio DAC bypass pin Earphone 0 amplifier output (-) Earphone 0 amplifier output (+) C12 Microphone bias supply (+) B11 D10 C10 B10 A10 D9 AU_VREF_P AU_VIN0_P AU_VIN0_N AU_VIN1_N AU_VIN1_P BDLAQP C9 BDLAQN A9 BDLAIN B9 BDLAIP B8 BUPAIP A8 BUPAIN C8 BUPAQN D8 BUPAQP B7 D6 C6 B6 A6 C5 B5 A5 C4 B4 APC AUXADIN0 AUXADIN1 AUXADIN2 AUXADIN3 AUXADIN4 AUXADIN5 AUXADIN6 AUX_REF AFC MT K D12 A4 AFC_BYP A2 D5 SYSCLK PLL_OUT Microphone bias supply (-) Audio reference voltage (-) Audio reference voltage (+) Microphone 0 amplifier input (+) Microphone 0 amplifier input (-) Microphone 1 amplifier input (-) Microphone 1 amplifier input (+) Quadrature input (Q+) baseband codec downlink Quadrature input (Q-) baseband codec downlink In-phase input (I+) baseband codec downlink In-phase input (I-) baseband codec downlink In-phase output (I+) baseband codec uplink In-phase output (I-) baseband codec uplink Quadrature output (Q+) baseband codec uplink Quadrature output (Q-) baseband codec uplink Automatic power control DAC output Auxiliary ADC input 0 Auxiliary ADC input 1 Auxiliary ADC input 2 Auxiliary ADC input 3 Auxiliary ADC input 4 Auxiliary ADC input 5 Auxiliary ADC input 6 Auxiliary ADC reference voltage input Automatic frequency control DAC output Automatic frequency control DAC bypass capacitance Co nf id en tia l C11 AU_MICBIA S_P AU_MICBIA S_N AU_VREF_N MI KI AU_MOUL AU_MOUR AU_M_BYPL AU_FMINL AU_FMINR AU_R_BIAS AU_M_BYPR AU_OUT0_N AU_OUT0_P Re le a se B15 A15 C14 B14 A14 D13 C13 B12 A12 Revision 1.01 fo r MT6226 GSM/GP RS Baseband Processor Technical Brief VCXO Interface 13MHz or 26MHz system clock input PLL test pin 24/33 MediaTek Inc. Confidential RTC Interface VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDD33_EMI W7 VDD33_EMI W9 VDD33_EMI W11 VDD33_EMI W13 VDD33_EMI W15 VDD33_EMI W18 VDD33_EMI T18 VDD33_EMI V3 V6 U8 V10 V12 V14 U16 V19 VSS33_EMI VSS33_EMI VSS33_EMI VSS33_EMI VSS33_EMI VSS33_EMI VSS33_EMI VSS33_EMI R19 P15 M15 VSS33_EMI VDD33_USB VDD33_MC P18 E15 VSS33_USB/ MC VDD33_IS A16 E14 F1 K1 R1 L19 VSS33_IS VSS33_IS VDD33 VDD33 VDD33 VDD33 PD Supply voltage of internal logic Supply voltage of internal logic Supply voltage of internal logic Supply voltage of internal logic Supply voltage of internal logic Supply voltage of internal logic Supply voltage of internal logic Supply voltage of memory interface driver Supply voltage of memory interface driver Supply voltage of memory interface driver Supply voltage of memory interface driver Supply voltage of memory interface driver Supply voltage of memory interface driver Supply voltage of memory interface driver Supply voltage of memory interface driver Ground of memory interface driver Ground of memory interface driver Ground of memory interface driver Ground of memory interface driver Ground of memory interface driver Ground of memory interface driver Ground of memory interface driver Ground of memory interface driver 1 Input fo r D1 M1 V8 E11 V16 H19 C16 W4 O I 32.768 KHz crystal input 32.768 KHz crystal output Baseband power on/off control TESTMODE enable input Supply Voltages Re le a se XIN XOUT BBWAKEUP TESTMODE MT K Co nf id en tia l C2 B1 C1 D3 Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief Ground of memory interface driver Supply voltage of USB transceiver Supply voltage of memory card interface drivers Ground of USB/memory card interface Supply voltage of image sensor interface drivers Ground of image sensor interface Ground of image sensor interface Supply voltage for pad Supply voltage for pad Supply voltage for pad Supply voltage for pad 25/33 MediaTek Inc. Confidential Supply voltage for pad Ground Ground Ground Ground Ground Ground Supply voltage for Real Time Clock Analog Supplies B3 C3 C15 Supply voltage for PLL Ground for PLL supply Supply Voltage for Audio band section D14 B13 AVDD_PLL AVSS_PLL AVDD_MBU F AVSS_MBUF AVDD_BUF A13 D11 AVSS_BUF AVDD_AFE A11 AGND_AFE E10 E9 AVSS_AFE AGND_RFE E8 C7 AVSS_GSMR FTX AVDD_GSM RFTX AVSS_RFE A7 AVDD_RFE GND for Audio band section Supply voltage for voice band transmit section GND for voice band transmit section Supply voltage for voice band receive section GND reference voltage for voice band section GND for voice band receive section GND reference voltage for baseband section, APC, AFC and AUXADC GND for baseband transmit section Co nf id en tia l D7 MI KI VDD33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 AVDD_RTC Re le a se E19 D2 H2 M2 H18 B16 E12 B2 Revision 1.01 fo r MT6226 GSM/GP RS Baseband Processor Technical Brief Supply voltage for baseband transmit section GND for baseband receive section, APC, AFC and AUXADC Supply voltage for baseband receive section, APC, AFC and AUXADC MT K Table 2 Pin Descriptions (Bolded types are functions at reset) 26/33 MediaTek Inc. Confidential 2.5 Power Description Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief Ball 13X13 A19 A18 B17 A18 A17 B16 C16 A16 J12 K12 H12 H11 H9 H10 H8 E15 J8 K8 L8 M8 M9 M10 M11 Name IO Supply IO GND Core Supply Core GND GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 VSS33 VDDK VSS33_IS CMRST CMPDN CMVREF CMHREF CMPCLK CMMCLK CMDAT9 VDD33_IS CMDAT8 CMDAT7 CMDAT6 CMDAT5 CMDAT4 CMDAT3 CMDAT2 VDD33 VSS33 VDDK VSSK M12 L12 E12 E11 E14 C15 B15 A15 CMDAT1 CMDAT0 VSS33 VDDK VSS33_IS AVDD_MBUF AU_MOUTL AU_MOUTR D14 C14 C13 D13 B14 A14 B12 B13 AVSS_MBUF AU_M_BYPL AU_M_BYPR AU_R_BIAS AU_FMINL AU_FMINR AU_OUT0_N AVDD_BUF Typ. 2.8V A12 A13 C12 D12 D11 AU_OUT0_P AVSS_BUF AU_MICBIAS_P AU_MICBIAS_N AVDD_AFE Typ. 2.8V Re le a se fo r Remark VSS33_IS VDDK VSSK VDD33_IS VSS33_IS VDDK VSSK MT K Co nf id en tia l VDD33_IS 27/33 Typ. 1.8V Typ. 1.8~2.8V Typ. 1.8V Typ. 2.8V MediaTek Inc. Confidential VDDK IBOOT JTRST# JTCK JTDI JTMS JTDO MT K MI KI D1 E5 E4 E3 E2 E1 F5 Re le a se AU_VREF_N AU_VREF_P AGND_AFE AU_VIN0_P AU_VIN0_N AU_VIN1_N AU_VIN1_P AVSS_AFE BDLAQP BDLAQN AGND_RFE BDLAIN BDLAIP AVSS_GSMRFTX BUPAIP BUPAIN AVDD_GSMRFTX BUPAQN BUPAQP AVSS_RFE APC AVDD_RFE AUXADIN0 AUXADIN1 AUXADIN2 AUXADIN3 AUXADIN4 AUXADIN5 AUXADIN6 AUX_REF AFC AFC_BYP AVDD_PLL PLL_OUT SYSCLK AVSS_PLL AVDD_RTC XOUT XIN BBWAKEUP TESTMODE VSS33 Co nf id en tia l C11 B11 A11 D10 C10 B10 A10 E10 D9 C9 E9 A9 B9 E8 B8 A8 D7 C8 D8 C7 B7 A7 D6 C6 B6 A6 C5 B5 A5 C4 B4 A4 B3 D5 A2 C3 B2 B1 C2 C1 D3 D2 Revision 1.01 fo r MT6226 GSM/GP RS Baseband Processor Technical Brief Typ. 2.8V Typ. 2.8V AVDD_PLL AVSS_PLL AVDD_PLL AVSS_PLL AVDD_RTC VSS33 AVDD_RTC VSS33 VDD33 VSS33 VDDK VSSK 28/33 Typ. 2.8V Typ. 1.8V Typ. 1.8V MediaTek Inc. Confidential NLD5 NLD4 NLD3 NLD2 NLD1 NLD0 NRNB VSS33 VDD33 VSS33 VDDK VSSK fo r M3 N5 N4 N3 N2 N1 P5 Typ. 2.8V VDD33 Re le a se JRTCK BPI_BUS0 BPI_BUS1 NLD17 VDD33 NLD16 BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 BSI_CS0 VSS33 BSI_DATA BSI_CLK LSCK LSA0 LSDA LSCE0# LSCE1# LPCE1# NLD15 NLD14 NLD13 VDD33 LPCE0# LRST# LRD# LPA0 LWR# NLD12 NLD11 NLD10 NLD9 NLD8 NLD7 VSS33 VDDK NLD6 VDDK Co nf id en tia l F4 F3 F2 F6 F1 G6 G5 G4 G3 G2 G1 H5 H4 H3 H1 H2 J5 J4 J3 J2 J1 K4 K3 K2 L11 L10 L9 K1 L5 L4 L3 L2 L1 K11 K9 J11 J10 J9 M5 M2 M1 M4 Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief VSSK Typ. 2.8V VDD33 VSS33 VDDK VSSK VDD33 VSS33 VDDK VSSK MT K Typ. 1.8V 29/33 MediaTek Inc. Confidential P4 P3 R1 P2 P1 R4 R3 NCLE NALE VDD33 NWE# NRE# NCE# PWM1 R2 T4 PWM2 ALERTER T1 SRCLKENA T3 T2 SRCLKENAN SRCLKENAI U1 SYSRST# U2 GPIO0 V1 U3 EINT0 EINT1 W1 EINT2 V2 EINT3 V3 VSS33_EMI W2 W3 EA25 EA24 U4 V4 W4 R5 W5 V5 U5 T5 V6 W6 U6 T6 R6 W7 V7 U7 T7 R7 V8 U8 W8 T8 R8 V9 W9 U9 T9 EA23 EA22 VDD33_EMI MIRQ EA21 EA20 EA19 EA18 VSS33_EMI EA17 EA16 EA15 EA14 VDD33_EMI EA13 EA12 EA11 EA10 VDDK VSS33_EMI EA9 EA8 EA7 EA6 VDD33_EMI EA5 EA4 Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief Typ. 2.8V VSS33 VDDK VDD33_EMI VSS33_EMI Re le a se VDDK Co nf id en tia l MT K VSSK fo r VDD33 VSSK Typ. 1.8~2.8V VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK Typ. 1.8~2.8V Typ. 1.8V VSSK Typ. 1.8~2.8V VDD33_EMI VSS33_EMI 30/33 VDDK VSSK MediaTek Inc. Confidential W10 V10 U10 T10 R10 W11 R11 U11 V11 T11 V12 W12 U12 T12 R12 W13 V13 U13 T13 R13 V14 W14 U14 T14 R14 W15 V15 U15 T15 W16 V16 EA3 VSS33_EMI EA2 EA1 EA0 VDD33_EMI EWAIT EADV# ECLK EPDN# VSS33_EMI ECS7# ECS6# ECS5# ECS4# VDD33_EMI ECS3# ECS2# ECS1# ECS0# VSS33_EMI EWR# ERD# EUB# ELB# VDD33_EMI ED15 ED14 ED13 ED12 VDDK U16 VSS33_EMI T16 W17 V17 W18 ED11 ED10 ED9 VDD33_EMI VDD33_EMI VSS33_EMI VDDK VSSK U17 W19 V18 V19 U18 U19 T17 T18 T19 R15 R16 R17 R18 ED8 ED7 ED6 VSS33_EMI ED5 ED4 ED3 VDD33_EMI ED2 ED1 ED0 MFIQ WATCHDOG VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI VSS33_EMI VDDK VSSK VDD33_EMI Re le a se fo r Typ. 1.8~2.8V Co nf id en tia l MT K Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief VSS33_EMI VDDK Typ. 1.8~2.8V Typ. 1.8~2.8V VSSK 1.8V Typ. 1.8~2.8V Typ. 1.8~2.8V 31/33 MediaTek Inc. Confidential KCOL1 KCOL0 KROW5 VDD33 KROW4 KROW3 KROW2 VDD33_USB VSS33_USB /M VDDK C VSSK VDD33_MC VSS33_USB/M VDDK C VSSK VDD33 VSS33 MT K fo r F17 F18 F19 E19 E16 E17 E18 Typ. 3.3V Re le a se VSS33_EMI VDD33_USB USB_DP USB_DM VSS33_USB/MC MCCM0 MCDA0 MCDA1 MCDA2 MCDA3 MCCK MCPWRON MCWP MCINS VDD33_MC VDD33 GPIO1 GPIO2 GPIO3 SIMRST SIMCLK SIMVCC SIMSEL SIMDATA URXD1 UTXD1 UCTS1 URTS1 URXD2 UTXD2 VDDK VSS33 URXD3 UTXD3 IRDA_PDN IRDA_TXD IRDA_RXD KCOL6 KCOL5 KCOL4 KCOL3 KCOL2 VDDK Co nf id en tia l R19 P15 P16 P17 P18 P19 N15 N16 N17 N18 N19 M16 M17 M18 M15 L19 M19 L15 L16 L18 L17 K15 K16 K17 K18 K19 J16 J17 J18 J19 H19 H18 H15 H16 H17 G15 G16 G17 G18 G19 F15 F16 Revision 1.01 MI KI MT6226 GSM/GP RS Baseband Processor Technical Brief Typ. 2.8V Typ. 2.8V VSSK Typ. 1.8V VDD33 VSS33 VDDK VSSK VDD33 VSS33 VDDK VSSK Typ. 2.8V 32/33 MediaTek Inc. Confidential KROW1 KROW0 DAICLK DAIPCMOUT DAIPCMIN DAIRST DAISYNC GPIO4 MT K Co nf id en tia l Re le a se Table 3 Power Descriptions MI KI D16 D19 D17 D18 C19 C18 B19 C17 Revision 1.01 fo r MT6226 GSM/GP RS Baseband Processor Technical Brief 33/33 MediaTek Inc. Confidential