PHILIPS SAA4993H

INTEGRATED CIRCUITS
DATA SHEET
SAA4993H
Field and line rate converter
with noise reduction
Product specification
File under Integrated Circuits, IC02
2001 Nov 23
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
CONTENTS
12
PACKAGE OUTLINE
13
SOLDERING
13.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
1
FEATURES
2
GENERAL DESCRIPTION
2.1
Patent notice
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
BLOCK DIAGRAMS
6
PINNING
14
DATA SHEET STATUS
7
FUNCTIONAL DESCRIPTION
15
DEFINITIONS
8
CONTROL REGISTER DESCRIPTION
16
DISCLAIMERS
9
LIMITING VALUES
10
THERMAL CHARACTERISTICS
11
CHARACTERISTICS
2001 Nov 23
13.2
13.3
13.4
13.5
2
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
1
SAA4993H
2
FEATURES
• Upconversion of all 1fH film and video standards up to
292 active input lines per field
GENERAL DESCRIPTION
The SAA4993H is a completely digital monolithic
integrated circuit which can be used for field and line rate
conversion of all global TV standards.
• 100/120 Hz 2 : 1, 50/60 Hz 1 : 1 and 100/120 Hz 1 : 1
output formats
It features improved Natural Motion(1) performance.
• 4 : 1 : 1, 4 : 2 : 2 and 4 : 2 : 2 Differential Pulse Code
Modulation (DPCM) input colour formats; 4 : 1 : 1 and
4 : 2 : 2 output colour formats
It can be configured to emulate the SAA4990H as well as
the SAA4991WP. For demonstration purposes a split
screen mode to show the Dynamic Noise Reduction
(DNR) function and natural motion is available, and a
colour vector overlay mode exists.
• Full 8-bit accuracy
• Scalable performance by applying 2 or 3 external field
memories
• Improved recursive de-interlacing
The SAA4993H supports a Boundary Scan Test (BST)
circuit in accordance with IEEE 1149.
• Film (25 and 30 Hz) upconversion to 100/120
movement phases per second
2.1
• Variable vertical sharpness enhancement
Patent notice
Notice is herewith given that the subject integrated circuit
uses one or more of the following US patents and that
each of these patents may have corresponding patents in
other jurisdictions.
• Motion compensated 3D dynamic noise reduction
• High quality vertical zoom
• 2 Mbaud serial interface (SNERT)
US 4740842, US 5929919, US 6034734, US 5534946,
US 5532750, US 5495300, US 5903680, US 5365280,
US 5148269, US 5072293, US 5771074, and
US 5302909.
• Demonstration mode for noise reduction, motion
compensation and colour overlay.
(1) Natural Motion is a trademark of Koninklijke Philips
Electronics N.V.
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDI
core supply voltage
2.3
2.5
2.7
V
VDDE
external supply voltage (output pads)
3.0
3.3
3.6
V
IDD
supply current
−
280
−
mA
fCLK32
operating clock frequency
−
32
33.3
MHz
Tamb
ambient temperature
0
−
70
°C
4
ORDERING INFORMATION
TYPE
NUMBER
SAA4993H
2001 Nov 23
PACKAGE
NAME
QFP160
DESCRIPTION
plastic quad flat package; 160 leads (lead length 1.6 mm);
body 28 × 28 × 3.4 mm; high stand-off height
3
VERSION
SOT322-2
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SNDA
SNRST
DYNAMIC
NOISE
REDUCTION
27
26
25
YC0 to YC7
YD7 to YD0
YE0 to YE7
151, 152,
154 to 159
2 to 9
111, 112,
114 to 119
122 to 129
COMPRESS
SEQUENCER
MUX
MUX
SNERT
INTERFACE
SAA4993H
4
DE-INTERLACER
vectors
CONTROL
TCK
TDO
TDI
TMS
TRST
TE
CLK32
DECOMPRESS
Field and line rate converter
with noise reduction
SNCL
45 to 52
BLOCK DIAGRAMS
YA0 to YA7
YB7 to YB0
Philips Semiconductors
5
handbook, full pagewidth
2001 Nov 23
FIELD MEMORY 3
FIELD MEMORY 2
MPR
LEFT
35
34
TPM
ESM
VERTICAL
PEAKING
VERTICAL
ZOOM
82 to 89
YF7 to YF0
YG7 to YG0
MOTION ESTIMATOR
33
32
SPM
61 to 68
MPR
RIGHT
BST/TEST
vectors
31
UPCONVERSION
30
79
MHC054
Product specification
Fig.1 Block diagram of the luminance part.
SAA4993H
The solid lines represent pixel data; the broken lines represent controls.
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UVB3 to UVB0
UVC0 to UVC3
UVD3 to UVD0
UVE0 to UVE3
10 to 13
107 to 110
130 to 133
37 to 44
5
DECOMPRESS/
REFORMAT
Philips Semiconductors
UVA0 to UVA7
FIELD MEMORY 3
147 to 150
COMPRESS/
FORMAT
Field and line rate converter
with noise reduction
handbook, full pagewidth
2001 Nov 23
FIELD MEMORY 2
DECOMPRESS/
REFORMAT
DNR
SAA4993H
vectors
MPR
LEFT
MPR
RIGHT
UPCONVERSION
FORMAT
VERTICAL
ZOOM
70 to 77
91 to 98
UVF7 to YVF0
UVG7 to YVG0
MHC055
Product specification
Fig.2 Block diagram of the chrominance part.
SAA4993H
The solid lines represent pixel data; the broken lines represent the data flow, if the (optional) field memory 3 is also used.
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
6
SAA4993H
PINNING
SYMBOL
PIN
DESCRIPTION(1)(2)
TYPE
VSSE
1
ground ground of output pads
YC0
2
input
bus C luminance input from field memory 2 bit 0 (LSB)
YC1
3
input
bus C luminance input from field memory 2 bit 1
YC2
4
input
bus C luminance input from field memory 2 bit 2
YC3
5
input
bus C luminance input from field memory 2 bit 3
YC4
6
input
bus C luminance input from field memory 2 bit 4
YC5
7
input
bus C luminance input from field memory 2 bit 5
YC6
8
input
bus C luminance input from field memory 2 bit 6
YC7
9
input
bus C luminance input from field memory 2 bit 7 (MSB)
UVC0
10
input
bus C chrominance input from field memory 2 bit 0 (LSB)
UVC1
11
input
bus C chrominance input from field memory 2 bit 1
UVC2
12
input
bus C chrominance input from field memory 2 bit 2
UVC3
13
input
bus C chrominance input from field memory 2 bit 3 (MSB)
REC
14
output
read enable output for bus C
VSSE
15
ground ground of output pads
VDDE
16
supply external supply voltage (output pads)
VSSI
17
ground core ground
VDDI
18
supply core supply voltage
JUMP0
19
input
configuration pin 0; will be stored in register 0B3 e.g. to indicate presence of 3rd field
memory; should be connected to ground or to VDDE via a pull-up resistor of 47 kΩ
JUMP1
20
input
configuration pin 1; will be stored in register 0B5 e.g. to indicate presence of 16-bit
1st field memory for full 4 : 2 : 2; should be connected to ground or to VDDE via a pull-up
resistor of 47 kΩ
VDDE
21
supply external supply voltage (output pads)
VDDI
22
supply core supply voltage
VSSI
23
ground core ground
RAMTST1
24
input
test pin 1 input for internal RAM testing with internal pull-down; connect to ground for
normal operation
SNRST
25
input
SNERT bus reset input
SNDA
26
I/O
SNERT bus data input and output
SNCL
27
input
SNERT bus clock input
VSSE
28
ground ground of output pads
RAMTST2
29
input
test pin 2 input for internal RAM testing with internal pull-down; connect to ground for
normal operation
TE
30
input
test mode input with internal pull-down; if not used it has to be connected to ground
TRST
31
input
boundary scan test reset input (active LOW); if not used it has to be connected to VDDE
via a pull-up resistor of 47 kΩ
TMS
32
input
boundary scan test mode select input; if not used it has to be connected to VDDE via a
pull-up resistor of 47 kΩ
TDI
33
input
boundary scan test data input; if not used it has to be connected to VDDE via a pull-up
resistor of 47 kΩ
2001 Nov 23
6
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
DESCRIPTION(1)(2)
SYMBOL
PIN
TYPE
TDO
34
3-state boundary scan test data output
TCK
35
input
VSSE
36
ground ground of output pads
UVA0
37
input
bus A chrominance input from field memory 1 bit 0 (LSB)
UVA1
38
input
bus A chrominance input from field memory 1 bit 1
UVA2
39
input
bus A chrominance input from field memory 1 bit 2
UVA3
40
input
bus A chrominance input from field memory 1 bit 3
UVA4
41
input
bus A chrominance input from field memory 1 bit 4
UVA5
42
input
bus A chrominance input from field memory 1 bit 5
UVA6
43
input
bus A chrominance input from field memory 1 bit 6
UVA7
44
input
bus A chrominance input from field memory 1 bit 7 (MSB)
YA0
45
input
bus A luminance input from field memory 1 bit 0 (LSB)
YA1
46
input
bus A luminance input from field memory 1 bit 1
YA2
47
input
bus A luminance input from field memory 1 bit 2
YA3
48
input
bus A luminance input from field memory 1 bit 3
YA4
49
input
bus A luminance input from field memory 1 bit 4
YA5
50
input
bus A luminance input from field memory 1 bit 5
YA6
51
input
bus A luminance input from field memory 1 bit 6
YA7
52
input
bus A luminance input from field memory 1 bit 7 (MSB)
REA
53
output
read enable output for bus A
VSSE
54
ground ground of output pads
VSSI
55
ground core ground
VDDI
56
supply core supply voltage
VDDI
57
supply core supply voltage
VSSI
58
ground core ground
VSSE
59
ground ground of output pads
REF
60
input
read enable input for bus F and G
YF7
61
output
bus F luminance output bit 7 (MSB)
YF6
62
output
bus F luminance output bit 6
YF5
63
output
bus F luminance output bit 5
YF4
64
output
bus F luminance output bit 4
YF3
65
output
bus F luminance output bit 3
YF2
66
output
bus F luminance output bit 2
YF1
67
output
bus F luminance output bit 1
YF0
68
output
bus F luminance output bit 0 (LSB)
VDDE
69
supply external supply voltage (output pads)
UVF7
70
output
bus F chrominance output bit 7 (MSB)
UVF6
71
output
bus F chrominance output bit 6
UVF5
72
output
bus F chrominance output bit 5
UVF4
73
output
bus F chrominance output bit 4
2001 Nov 23
boundary scan test clock input; if not used it has to be connected to VDDE via a pull-up
resistor of 47 kΩ
7
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
DESCRIPTION(1)(2)
SYMBOL
PIN
TYPE
UVF3
74
output
bus F chrominance output bit 3
UVF2
75
output
bus F chrominance output bit 2
UVF1
76
output
bus F chrominance output bit 1
UVF0
77
output
bus F chrominance output bit 0 (LSB)
VSSE
78
ground ground of output pads
CLK32
79
input
VSSI
80
ground core ground
VSSE
81
ground ground of output pads
YG7
82
3-state bus G luminance output bit 7 (MSB)
YG6
83
3-state bus G luminance output bit 6
YG5
84
3-state bus G luminance output bit 5
YG4
85
3-state bus G luminance output bit 4
YG3
86
3-state bus G luminance output bit 3
YG2
87
3-state bus G luminance output bit 2
YG1
88
3-state bus G luminance output bit 1
YG0
89
3-state bus G luminance output bit 0 (LSB)
VDDE
90
supply external supply voltage (output pads)
UVG7
91
3-state bus G chrominance output bit 7 (MSB) or vector output bit 7
UVG6
92
3-state bus G chrominance output bit 6 or vector output bit 6
UVG5
93
3-state bus G chrominance output bit 5 or vector output bit 5
UVG4
94
3-state bus G chrominance output bit 4 or vector output bit 4
UVG3
95
3-state bus G chrominance output bit 3 or vector output bit 3
UVG2
96
3-state bus G chrominance output bit 2 or vector output bit 2
UVG1
97
3-state bus G chrominance output bit 1 or vector output bit 1
system clock input
UVG0
98
3-state bus G chrominance output bit 0 (LSB) or vector output bit 0
VSSE
99
ground ground of output pads
VSSI
100
ground core ground
VDDI
101
supply core supply voltage
VDDE
102
supply external supply voltage (output pads)
VDDI
103
supply core supply voltage
VSSI
104
ground core ground
VSSE
105
ground ground of output pads
WED
106
3-state write enable output for bus D
UVD3
107
3-state bus D chrominance output to field memory 3 bit 3 (MSB)
UVD2
108
3-state bus D chrominance output to field memory 3 bit 2
UVD1
109
3-state bus D chrominance output to field memory 3 bit 1
UVD0
110
3-state bus D chrominance output to field memory 3 bit 0 (LSB)
YD7
111
3-state bus D luminance output to field memory 3 bit 7 (MSB)
YD6
112
3-state bus D luminance output to field memory 3 bit 6
VDDE
113
supply external supply voltage (output pads)
YD5
114
3-state bus D luminance output to field memory 3 bit 5
2001 Nov 23
8
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
DESCRIPTION(1)(2)
SYMBOL
PIN
TYPE
YD4
115
3-state bus D luminance output to field memory 3 bit 4
YD3
116
3-state bus D luminance output to field memory 3 bit 3
YD2
117
3-state bus D luminance output to field memory 3 bit 2
YD1
118
3-state bus D luminance output to field memory 3 bit 1
YD0
119
3-state bus D luminance output to field memory 3 bit 0 (LSB)
VSSE
120
ground ground of output pads
VSSE
121
ground ground of output pads
YE0
122
input
bus E luminance input from field memory 3 bit 0 (LSB)
YE1
123
input
bus E luminance input from field memory 3 bit 1
YE2
124
input
bus E luminance input from field memory 3 bit 2
YE3
125
input
bus E luminance input from field memory 3 bit 3
YE4
126
input
bus E luminance input from field memory 3 bit 4
YE5
127
input
bus E luminance input from field memory 3 bit 5
YE6
128
input
bus E luminance input from field memory 3 bit 6
YE7
129
input
bus E luminance input from field memory 3 bit 7 (MSB)
UVE0
130
input
bus E chrominance input from field memory 3 bit 0 (LSB)
UVE1
131
input
bus E chrominance input from field memory 3 bit 1
UVE2
132
input
bus E chrominance input from field memory 3 bit 2
UVE3
133
input
bus E chrominance input from field memory 3 bit 3 (MSB)
REE
134
output
read enable output for bus E
VSSE
135
ground ground of output pads
HREF
136
input
VSSI
137
ground core ground
VDDI
138
supply core supply voltage
OSCI
139
input
test pin input with internal pull-down; connect to ground for normal operation
RESFM
140
output
reset field memory output for pin OSCI = LOW or test output OSCOUT for
pin OSCI = HIGH
VDDE
141
supply external supply voltage (output pads)
VDDI
142
supply core supply voltage
VSSI
143
ground core ground
ACV
144
output
VSSE
145
ground ground of output pads
WEB
146
output
write enable output for bus B
UVB3
147
output
bus B chrominance output to field memory 2 bit 3 (MSB)
UVB2
148
output
bus B chrominance output to field memory 2 bit 2
UVB1
149
output
bus B chrominance output to field memory 2 bit 1
UVB0
150
output
bus B chrominance output to field memory 2 bit 0 (LSB)
YB7
151
output
bus B luminance output to field memory 2 bit 7 (MSB)
YB6
152
output
bus B luminance output to field memory 2 bit 6
VDDE
153
supply external supply voltage (output pads)
YB5
154
output
2001 Nov 23
horizontal reference synchronization input
active video output
bus B luminance output to field memory 2 bit 5
9
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
DESCRIPTION(1)(2)
SYMBOL
PIN
TYPE
YB4
155
output
bus B luminance output to field memory 2 bit 4
YB3
156
output
bus B luminance output to field memory 2 bit 3
YB2
157
output
bus B luminance output to field memory 2 bit 2
YB1
158
output
bus B luminance output to field memory 2 bit 1
bus B luminance output to field memory 2 bit 0 (LSB)
YB0
159
output
VSSE
160
ground ground of output pads
Notes
1. Not used input pins (e.g. bus E) should be connected to ground.
2. Because of the noisy characteristic of the output pad supply, it is recommended not to connect the core supply and
the output pad supply directly at the device. The output pad supply should be buffered as close as possible to the
device.
2001 Nov 23
10
Philips Semiconductors
Product specification
122 YE0
121 VSSE
123 YE1
124 YE2
125 YE3
126 YE4
127 YE5
128 YE6
129 YE7
130 UVE0
131 UVE1
132 UVE2
133 UVE3
134 REE
137 VSSI
136 HREF
135 VSSE
139 OSCI
138 VDDI
142 VDDI
141 VDDE
140 RESFM
144 ACV
143 VSSI
146 WEB
145 VSSE
SAA4993H
147 UVB3
148 UVB2
149 UVB1
150 UVB0
151 YB7
152 YB6
154 YB5
153 VDDE
155 YB4
156 YB3
157 YB2
158 YB1
handbook, full pagewidth
160 VSSE
159 YB0
Field and line rate converter
with noise reduction
VSSE
1
YC0
2
120 VSSE
119 YD0
YC1
3
118 YD1
YC2
4
117 YD2
YC3
5
116 YD3
YC4
6
115 YD4
YC5
7
YC6
8
114 YD5
113 VDDE
YC7
9
112 YD6
UVC0 10
111 YD7
UVC1 11
110 UVD0
UVC2 12
109 UVD1
UVC3 13
108 UVD2
REC 14
VSSE 15
VDDE 16
107 UVD3
VSSI 17
VDDI 18
JUMP0 19
104 VSSI
103 VDDI
102 VDDE
JUMP1
VDDE
106 WED
105 VSSE
20
101 VDDI
100 VSSI
SAA4993H
21
VDDI 22
VSSI 23
98
VSSE
UVG0
RAMTST1
24
97
UVG1
SNRST
25
96
UVG2
SNDA
26
95
UVG3
SNCL
VSSE
27
94
UVG4
28
93
UVG5
RAMTST2
29
92
UVG6
TE
30
91
TRST
31
90
UVG7
VDDE
TMS
32
89
YG0
TDI
33
88
YG1
TDO
34
87
YG2
TCK
35
86
YG3
VSSE
UVA0
36
85
YG4
37
84
YG5
UVA1
38
83
YG6
UVA2
39
82
UVA3
40
81
YG7
VSSE
2001 Nov 23
65
66
67
68
69
70
71
72
73
74
75
76
77
YF3
YF2
YF1
YF0
VDDE
UVF7
UVF6
UVF5
UVF4
UVF3
UVF2
UVF1
UVF0
VSSE
80
64
YF4
79
63
YF5
11
CLK32
VSSI
62
YF6
Fig.3 Pin configuration.
78
61
YF7
49
YA4
60
48
YA3
REF
47
YA2
VSSI 58
VSSE 59
46
YA1
VDDI 56
VDDI 57
45
YA0
REA 53
VSSE 54
VSSI 55
44
UVA7
YA7 52
43
UVA6
YA6 51
42
UVA5
YA5 50
41
UVA4
99
MHC056
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
7
SAA4993H
FUNCTIONAL DESCRIPTION
Table 1
The fal_top module builds the functional top level of the
SAA4993H. It connects the luminance data path, the
chrominance data path and the luminance
(de)compression with SAA4993H inputs and outputs as
well as controlling logic. Outside of the fal_top module,
there are only the pad cells, boundary scan test cells, the
boundary scan test controller, the clock tree, the test
enable tree and the input port registers.
Clock cycle references
SIGNAL
LATENCY
RE_F
0
RE_C and
RE_E
62 cycles + REceShift
YC, YE, UVC
and UVE
63 cycles
RE_A
93 cycles + REaShift
Figure 4 shows a simplified block diagram of the fal_top
module. It displays the flow of pixel data (solid lines) and
controls (broken lines) between the modules inside.
YA and UVA
94 cycles
YF, YG, UVF
and UVG
147 cycles + 3 input lines
Basic functionality of the modules in the fal_top module is
as follows:
WE_B and
WE_D
159 cycles + 4 input lines + WEbdShift
• KER (kernel): Y (luminance) data path
YB, YD, UVB
and UVD
159 cycles + 4 input lines
• COL (colour): UV (chrominance) data path
• YDP (Y-DPCM): compression (and decompression) of
luminance output (and input) data by Differential Pulse
Code Modulation (DPCM)
There is an algorithmic delay of 3 lines between input and
output data. Therefore, the main data output on the
F and G bus begins while the fourth input line is read.
Writing to the B and D bus starts one input line later. The
read and write enable signals RE_A, WE_B, RE_C, WE_D
and RE_E can be shifted by control registers REaShift,
WEbdShift and REceShift, which are implemented in the
line sequencer.
• LSE (line sequencer): generate line frequent control
signals
• SNE (interface): Synchronous No parity Eight bit
Reception and Transmission (SNERT) interface to a
microcontroller.
The SNERT interface operates in a slave receive and
transmit mode for communication with a microcontroller,
which resides on peripheral circuits (e.g. SAA4978H)
together with a SNERT master. The SNERT interface
transforms serial data from the microcontroller (via the
SNERT bus) into parallel data to be written into the
SAA4993Hs write registers and parallel data from
SAA4993Hs read registers into serial data to be sent to the
microcontroller. The SNERT bus consists of 3 signals:
The fal_top module itself reads the following control
register bits (addresses):
• NrofFMs (017H)
• MatrixOn (026H) and BusGControl (028H)
• MemComp and MemDecom (026H).
NrofFMs, MatrixOn and BusGControl are used to enable
the D and G output bus, respectively. MemComp and
MemDecom are connected to YDP to control luminance
data compression and decompression. These control
register signals are not displayed in Fig.4. Further
information on the control registers is given in Chapter 8.
1. SNCL: used as serial clock signal, generated by the
master
2. SNDA: used as bidirectional data line
3. SNRST: used as a reset signal, generated by the
microcontroller to indicate the start of a transmission.
The processing of a video field begins on the rising edge
of the RE_F input signal. As indicated in Fig.4, the
SAA4993H receives its inputs and generates its outputs at
the following clock cycles after RE_F (see Table 1).
2001 Nov 23
12
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
external field memories
handbook, full pagewidth
fal_top
WE_B,
WE_D
RE_C,
RE_E
UVB,
UVD
UVC,
UVE
YB,
YD
YC,
YE
159
cycles
62
cycles
159
cycles
63
cycles
159
cycles
63
cycles
UVA
94 cycles
YDP
COL
UVF, UVG
147 cycles
SNDA
SNE
LSE
RE_A
93 cycles
RE_F
0 cycles
YF, YG
147 cycles
KER
YA
94 cycles
MHC057
The solid lines represent pixel data; the broken lines represent controls.
Fig.4 Block diagram of fal_top.
2001 Nov 23
13
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NAME
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
DESCRIPTION(2)
DNR/peaking/colour
Kstep10
010
write; S
X X X X set LUT value: k = 1⁄16 if difference below (0 to 15)
Kstep0
Kstep1
Kstep32
X X X X
011
write; S
X X X X set LUT value: k = 2⁄8 if difference below (0 to 30 in multiples of 2)
Kstep2
Kstep3
Kstep54
X X X X
012
X X X X set LUT value: k = 4⁄8 if difference below (0 to 60 in multiples of 4)
Kstep5
X X X X
013
X X X X set LUT value: k = 6⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,
64, 72, 80, 88, 96, 104, 112 or 120)
14
Kstep7
X X X X
014
X X X X set fixed Y value; used when FixY = 1 or in left part of split screen
(0, 1⁄16 to 14⁄16 or 16⁄16)
GainY
X X X
FixY
X
015
write; S
X X X X set fixed UV value; used when FixUV = 1 or in left part of split screen
(0, 1⁄16 to 14⁄16 or 16⁄16)
GainUV
X X X
X
select fixed UV (adaptive or fixed) (full screen)
write; S
VecComp
X X X set degree of horizontal vector compensation in Y DNR:
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8) of the vector
X X X X
set vertical peaking level: (0, +2, +3.5, +5, +6, x, x, x, x, x, x, x, x,
−12, −6 or −2.5) dB
SAA4993H
016
set gain in difference signal for adaptive DNR UV (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)
Product specification
FixUV
PeakCoef
set gain in difference signal for adaptive DNR Y (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)
select fixed Y (adaptive or fixed) (full screen)
FixvalUV
Peak_Vcomp
set LUT value: k = 7⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,
64, 72, 80, 88, 96, 104, 112 or 120)
write; S
FixvalY
Gain_fix_uv
set LUT value: k = 5⁄8 if difference below (0 to 60 in multiples of 4)
write; S
Kstep6
Gain_fix_y
set LUT value: k = 3⁄8 if difference below (0 to 30 in multiples of 2)
write; S
Kstep4
Kstep76
set LUT value: k = 1⁄8 if difference below (0 to 15)
Philips Semiconductors
CONTROL REGISTER DESCRIPTION
Field and line rate converter
with noise reduction
2001 Nov 23
8
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017
DESCRIPTION(2)
write; S
ColourIn
X X select colour input format: (4 : 1 : 1, 4 : 2 : 2, 4 : 2 : 2 DPCM or
4 : 2 : 2)
ColourOut
X
NrofFMs
X
ColOvl
X
SlaveUVtoY
X
DnrSplit
X
DnrHpon
select colour output format: (4 : 1 : 1 or 4 : 2 : 2)
set number of field memories connected: (1 or 2 plus 3)
select vector overlay on colour output: (vector overlay or colour
from video path)
slave UV noise reduction to K factor of Y: (separate or slaved)
select split screen mode for DNR: (normal or split screen)
X
switch DNR high-pass on (DNR only active on low frequent spectrum:
(all through DNR or high bypassed)
Philips Semiconductors
DNR_Colour_mode
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
Vertical zoom
Zoom1
018
write; F
ZoomSt98
15
X X zoom line step bits 9 and 8; line step = vertical distance between
successive output lines; usable range = 0 to 2 frame lines;
resolution 1⁄256 frame line
ZoomPo98
Zoom2
X X
019
write; F
ZoomSt70
Zoom3
X X X X X X X X zoom line step bits 7 to 0 (see above)
01A
write; F
ZoomPo70
Zoom4
X X X X X X X X zoom start position bits 7 to 0 (see above)
01B
write; F
ZoomEnVal
X X X X zoom run in value = number of lines without zoom active
(0 to 15 lines)
zoom run out value = number of lines without zoom active
(−8 to +7 lines)
Product specification
X X X X
SAA4993H
ZoomDiVal
zoom start position bits 9 and 8; start position = vertical position of the
top display line; usable range = 1 to 3 frame lines; resolution 1⁄256
frame line
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DESCRIPTION(2)
De-interlacer
Proscan1
01C
write; S
KlfLim
X X X X limitation of recursion factor in calculation of original line positions:
(1 to 16); 1 limits to almost full recursion, 16 limits to no recursion
KlfOfs
Proscan2
X X X X
01D
write; S
PlfLim
X X X X limitation of recursion factor in calculation of interpolated line
positions: (1 to 16); 1 limits to almost full recursion, 16 limits to no
recursion
16
PlfOfs
Proscan3
X X X X
01E
see KlfOfs; this offset applies to interpolated lines
write; S
PeakLim
DeiOfs
The transfer curve of the de-interlacing filter coefficient is determined
by the difference (Diff) between a line in the input field and the
counterpart in the previous field shifted over the estimated motion
vector. KlfOfs determines the bias of the transfer curve for the original
input line, such that coefficient = KlfOfs + F(Diff), where the function F
is calculated in the SAA4993H. The bias can take a value in the range
(0 to 15), representing decreasing filter strength.
Philips Semiconductors
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
X X X X Maximum that the peaked pixel is allowed to deviate from original pixel
value: deviation (0 to 30 in steps of 2). Above this deviation, the
peaked pixel is clipped to (original pixel + or − PeakLim).
X X X X
offset to bias between average and median in the initial de-interlacing,
if the KplFad = MIX option is chosen
Product specification
SAA4993H
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01F
write; F
PlfThr
X X X Multiplier threshold at which to switch the lower limit of the filter
coefficient for interpolated lines. Above this threshold, the differences
corresponding to the two neighbouring lines are used as clipping
parameters, below this threshold, the interpolated line difference is
used as clipping level. This parameter can be used to optimize the
de-interlacing quality in slowly moving edges; it is not likely to have
effect if PlfLim is high.
AdRecOut
X
ProDiv
X X
17
KplOff
Proscan5
X
0CB
select adaptive recursive or order statistic output (order statistic or
adaptive)
Scaling factor to control the strength of the filtering for the interpolated
lines. A value 0 means no scaling (normal filtering), while 3 means
scaling by factor 8 (very strong filtering). This parameter can be used
to adjust the de-interlacing to varying level of noise in the input picture;
use higher scaling for higher noise.
disable all recursion in calculating pixels for frame memory (recursive
or non recursive); to be true SAA4991WP and digital scan emulation
modes
write; S
VecRbf
X X X X Roll back factor on vectors used for motion-compensated
de-interlacing. Values 0 to 14 (on a scale of 16) indicate attenuation.
A value of 15 indicates no attenuation.
FadDiv
KplFad
DESCRIPTION(2)
Philips Semiconductors
Proscan4
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
X X X
X
sensitivity scaling factor in transition from average to median in initial
de-interlacing
chooses between majority selection and median/average mix for initial
de-interlacing (majority or mix); when KplFad = 0, FadDiv and
DeiOfs are don’t cares
Product specification
SAA4993H
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DESCRIPTION(2)
General
NrBlks
020
write; S
NrBlks
X X X X X X number of blocks in active video (6 to 53, corresponds to
96 to 848 pixels), to be set as 1⁄16 (number of active pixels per
line + 15); take remarks on TotalPxDiv8 into consideration
TotalLnsAct98
X X
total number of output lines (bits 9 and 8)
18
TotalLnsAct70
021
write; S
X X X X X X X X total number of output lines (bits 7 to 0)
TotalPxDiv8
022
write; S
X X X X X X X X Total number of pixels per line divided-by-8 (80 to 128, corresponds to
640 to 1024 pixels). The horizontal blanking interval is calculated as
TotalPxDiv8 − 2 × NrBlks and has to be in the range from 12 to 124
(corresponds to 96 to 992 pixels). Conclusion: TotalPxDiv8 has to be
set to 12 + 2 × NrBlks < TotalPxDiv8 < 124 + 2 × NrBlks and NrBlks
TotalPxDiv8 – 124
TotalPxDiv8 – 12
has to be set to ------------------------------------------------ < NrBlks < --------------------------------------------2
2
REaShift
023
write; S
WEbdREceShift
024
write; S
Philips Semiconductors
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
X X X shift of RE_A signal in number of pixels
(0, +1, +2, +3, −4, −3, −2 or −1)
WEbdShift
X X X shift of WE_B and WE_D signal in number of pixels
(0, +1, +2, +3, −4, −3, −2 or −1)
REceShift
X X X
POR
025
write; S
ScalingFactor
0D6
write; S
shift of RE_C and RE_E signal in number of pixels
(0, +1, +2, +3, −4, −3, −2 or −1)
X power-on reset command, to be set high temporarily during start-up
(normal or reset); note 3
X X X X X X X X 8-bit scaling factor for EggSliceMix, EggSliceRgt and global activity
(the same factor for all registers).
ScalingFactor
output value (n+1) = ------------------------------------ × output value (n)
128
Product specification
SAA4993H
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DESCRIPTION(2)
Mode control
Control1
026
write; F
EstMode
X Set estimator mode; 0 = line alternating use of left and right estimator:
use in progressive scan except with vertical compress. 1 = field
alternating use of left and right estimator: use in field doubling and
progressive scan with vertical compress.
FilmMode
X
UpcMode
X X
MatrixOn
X
EmbraceOn
X
19
MemComp
MemDecom
X
X
set film mode; 0 = video camera mode; 1 = film mode
select upconversion quality; 00 = full, 01 = economy (DPCM),
10 = SAA4991WP, 11 = SAA4990H
set matrix output mode; 1 = double output, disabling vertical peaking;
0 = normal single output mode; this bit setting is the AND function of
BusGControl bits
Philips Semiconductors
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
Master enable for embrace mode (off or on); SwapMpr in control2
should be at ‘swap’ position to really cross-switch FM1 and FM3 field
outputs. Should be set to logic 0 except in film mode and FM3 is
present, or in SAA4991WP film mode and MemComp bit is active.
set memory compression (luminance DPCM) (off or on)
set memory decompression (luminance DPCM) (off or on)
Product specification
SAA4993H
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027
write; F
QQcurr
X Quincunx phase of current field (in TPM) (phase0 or phase1); this
needs to toggle each time a new field comes from FM1. In phase0 the
estimator operates on a checker-board pattern that starts with the left
upper block; in phase1 the other blocks are estimated.
QQprev
X
FldStat
X
FieldWeYUV
X
20
OddFM1
X
SwapMpr
VecOffs
DESCRIPTION(2)
X
X X
quincunx phase of previous field (in TPM) (phase0 or phase1); this is
the value of QQcur during the last estimate written into the temporal
prediction memory
Field status (same input field or new input field); reflects whether
the output of FM1 is a new or a repeated field. This bit will toggle field
by field in field doubling mode and is continuously HIGH in progressive
output mode.
Philips Semiconductors
Control2
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
enable writing FM2 and FM3 for both luminance and chrominance
(recirculation of data for luminance alone can be controlled with
OrigFmEnY and IntpFmEnY in Control3) (off or on)
odd input field (even or odd), this is to be set equal to the detected
field interlace for the field that comes out of FM1
Swap multi port RAMs (normal or swap); this bit needs to be set to
get real frame data at the temporal position from FM1. If swapped, the
current field (FM1) will be stored in the right line memory tree, while
the original lines from the stored frame (FM2/3) are stored in the left
memory tree. Should be set only in film mode if FM3 is present;
EmbraceOn must be set as well.
Product specification
SAA4993H
Set vertical vector offset (0, +1, − or −1) frame lines; vertical offset of
the right line memory tree with respect to the left line memory tree.
A higher offset value means: on the right memory tree access to less
delayed video lines is taken; in interlaced video operation, the vertical
offset will be −1 with an odd field on the left side and +1 with an even
field on the left. With non-interlaced input, vertical offset should be
constantly 0. In film mode, vertical offset is dynamically switched
between +1, 0 and −1.
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028
OddLeft
write
F
X interlace (even or odd) phase of the field which is written to the left
line memory tree (left MPRAM)
OrigFmEnY
X
IntpFmEnY
X
FillTPM
X
VertOffsDNR
X X
21
BusGControl
DESCRIPTION(2)
S
X X
enables writing luminance from de-interlacer in original field memory
(FM2), otherwise recirculation of luminance that is just read from FM2
(recirculate or update)
enables writing luminance from de-interlacer in interpolated field
memory (FM3), otherwise recirculation of luminance that is just read
from FM3 (recirculate or update)
Enables writing in temporal prediction memory (keep or update);
FillTPM should be set to ‘keep’ in SAA4991WP/film mode, in those
output fields where FM1 and FM2 contain the same motion phase.
FillTPM should be set to ‘update’ in all other situations.
Philips Semiconductors
Control3
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
Set vertical vector offset of DNR (0, +1, − or −1) frame lines; vertical
offset of the right line memory tree with respect to the left line memory
tree, before the swap action. A higher offset value means: on the right
memory tree access to less delayed video lines is taken; in interlaced
video operation, the vertical offset will be −1 with an odd field on the
left side and +1 with an even field on the left. With non-interlaced
input, vertical offset should be constantly logic 0; in film mode, vertical
offset is dynamically switched between +1, 0 and −1. It should be
noted that the signal OddFM1 is used to determine this offset.
Select output mode of bus G; 00 = normal single output mode (bus G
in 3-state), 01 = output of motion vectors to UVG (motion_x on U and
motion_y on V), 10 = copy bus F to G, 11 = double output, disabling
vertical peaking. Only when double output is selected, the MatrixOn
bit in register Control1 should be set, otherwise it needs to be cleared.
Upconversion
write; F
X X X X X X temporal interpolation factor used in luminance upconverter; value
ranges from 0 (for current field position) to 32 (for previous field
position)
SAA4993H
UpcShFac
029
Product specification
Upconv1
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02A
write
YVecClip
S
RollBack
F
Upconv3
02B
X X X value used for coring the vertical vector component before application
in the upconverter; range: 0 to 3.5 in steps of 0.5 line; should remain
at logic 0 in normal operation
X X X X X
roll back factor ranging from 0 (use 0% of estimated vectors) to 16
(use 100% of estimated vectors)
write; S
MelzLfbm
X SAA4991WP type local fallback method instead of more robust local
fallback (complex or SAA4991WP type fallback)
Melzmemc
X
MelDeint
X
22
MixCtrl
X X X X X
UpcColShiFac
0C4
write; F
Upconv4
0C5
write; S
use (as in SAA4991WP) horizontal motion compensated median for
upconverter de-interlacing (normal or SAA4991WP type
de-interlacing)
Bits 3 and 4 are used to control sensitivity to local vector smoothness
(0 = sensitive to unsmoothness, 3 = hardly sensitive to
unsmoothness). Bits 5 to 7 define the maximum contribution of
non-motion compensated pixels to the output
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8).
X X X Number of consecutive lines to have bad egg-slice values before
upconverter goes into protection mode (0, 1, 2, 4, 8, 16, 32 or 64).
A value of 0 switches off the possibility to go into protection.
MCDemo
X
write; S
X X X X X X X X Reference line number at which the egg slice measurement should
start. SAA4993H defines a window internally as number of lines
between EggStartLine and (MaxRefLine − EggStartLine).
Product specification
0C6
mode switch on left side of the screen; 0 (natural motion); 1 (digital
scan-like processing)
SAA4993H
EggStartLine
SAA4991WP film mode memory control (normal or SAA4991WP
type); should be set in SAA4991WP film mode to ensure that only
original lines are selected as output when UpcShFac is 0 or 32
X X X X X X temporal interpolation factor used in chrominance upconverter; value
ranges from 0 (for current field position) to 32 (for previous field
position)
LfIndex
EggSlice1
DESCRIPTION(2)
Philips Semiconductors
Upconv2
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
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0C7
write; S
EggSlcThr
X X X X X X Minimum line egg slice right value to activate reliability measurement.
The parameter is multiplied internally by 4.
EggRelInd
SafeShiFac
DESCRIPTION(2)
X X
0C8
write; F
02C
write; S
the egg slice reliability is computed internally as
EggSliceRgt (ESR) > RelFactor × EggSliceMix (ESM). RelFactor is
determined by EggRelInd (2⁄8, 3⁄8, 4⁄8, or 6⁄8).
X X X X X X upconverter shift factor to be used in protection mode; 0 (for current
field position) to 32 (for previous field position)
Motion estimator
Motest1
PenOdd
X X X additional penalty on vector candidates with odd vertical component
(0, 8, 16, 32, 64, 128, 256 or 511)
SpcThr
X X X
Active when EstMode = 0; replace the spatial prediction of one
estimator (left or right) by that of the other if the match error of the
former exceeds that of the latter by more than (0, 8, 16, 32, 64, 128,
256 or 511). A higher threshold means the two estimators are very
independent.
23
BmsThr
Motest2
X X
02D
Active when EstMode = 0; select as estimated vector the output of the
right estimator unless its match error exceeds that of the left estimator
by more than (0, 8, 16 or 32). This parameter should normally be set
to logic 0.
write; S
TavLow
X If the difference between the current vector and the previous one in
the same spatial location is within a small window, then the two
vectors are averaged to improve temporal consistency. TavLow is the
lower threshold of this window (1 or 2).
TavUpp
X X
X X
scaling factor to reduce all sizes of update vectors in the ensemble
with large sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)
SAA4993H
X X
see above; TavUpp is the upper threshold (0, 4, 8 or 16)
scaling factor to reduce all sizes of update vectors in the ensemble
with medium sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)
Product specification
MedEns
LarEns
Philips Semiconductors
EggSlice2
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
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02E
write; F
MotShiFac
Motest4
X X X X X X Motion estimator shift factor, being the temporal position used in the
estimator at which the matching is done; value 32 for matching at
previous field position down to 0 for matching at current field position.
Keeping MotShiFac equal to UpShiFac in the next upconverted output
field estimates for minimum matching errors (minimum Halo’s).
MotShiFac at value 16 gives the largest natural vector range (twice as
large as with value 0 or 32). Going above the range with
MotShiFac ≠ 16 is dealt with in SAA4993H by shifting towards 16, but
for the horizontal and vertical component separately (consequence is
that vector candidates tend to rotate towards the diagonal directions).
02F
write; S
PenRng
24
X Penalty for vectors estimated on the first row and the first column (if
left estimator is used) or the right column (if right estimator is used),
whenever the spatial prediction candidate is selected (64 or 511).
For noisy pictures, this register could be set to logic 1 to improve
border processing in the estimator.
CndSet
X
ErrThr
X X X
ErrHbl
X X
TstMod
Motest5
DESCRIPTION(2)
Philips Semiconductors
Motest3
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
X
0CC
choice of candidate set (left or right) for which data (Candidate1 to
Candidate8) is written in this field (becomes active in next field);
note 3
threshold on block match error for considering a block to be bad
(16, 32, 64, 128, 256, 512, 1024 or 2032)
number of horizontally adjacent blocks that have to be all bad before
considering an occurrence of a burst error (1, 2, 4 or 8) (counting of
burst errors is read out with BlockErrCnt, address 0A8H)
to be kept to logic 1 for normal operation
write; S
ActOption
X
write zeros in the temporal prediction memory
(no writing or writing zeros)
LoActThr
0CD
write; S
X X X X X X X X blocks having an activity value below or equal to this threshold are
counted as having LOW activity
HiActThr
0CE
write; S
X X X X X X X X blocks having an activity value above this threshold are counted as
having HIGH activity
SAA4993H
ClearTPM
Product specification
X X selection of the vector component to take in the activity count
(x + y, x, y or −)
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0CF
DESCRIPTION(2)
write; S
LeftBorder
X X X X X X X estimator left border (in 8-pixel blocks)
WinNullWrite
X
enable writing of null vectors outside estimators’ active window
(off or on)
RightBorder
0D0
write; S
X X X X X X X estimator right border (in 8-pixel blocks)
TopBorder
0D1
write; S
X X X X X X X estimator top border (in 4-line blocks)
BottomBorder
0D2
write; S
X X X X X X X estimator bottom border (in 4-line blocks)
Candidate1
090
write; S
Candidat1
X X X selection Candidate1 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update1
X X
Penalty1
Candidate2
X X X
091
write; S
25
X X X selection Candidate2 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update2
X X
Penalty2
X X X
092
penalty for Candidate2 (0, 8, 16, 32, 64, 128, 256 or 511)
X X X selection Candidate3 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update3
X X
Penalty3
X X X
093
update for Candidate3 (zero update, medium update, large update
or zero update)
penalty for Candidate3 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
Update4
X X
X X X
update for Candidate4 (zero update, medium update, large update
or zero update)
penalty for Candidate4 (0, 8, 16, 32, 64, 128, 256 or 511)
Product specification
X X X selection Candidate4 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
SAA4993H
Candidat4
Penalty4
update for Candidate2 (zero update, medium update, large update
or zero update)
write; S
Candidat3
Candidate4
update for Candidate1 (zero update, medium update, large update
or zero update)
penalty for Candidate1 (0, 8, 16, 32, 64, 128, 256 or 511)
Candidat2
Candidate3
Philips Semiconductors
LeftBorder
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
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094
write; S
Candidat5
X X X selection Candidate5 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update5
X X
Penalty5
Candidate6
X X X
095
write; S
X X X selection Candidate6 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update6
X X
Penalty6
X X X
096
update for Candidate6 (zero update, medium update, large update
or zero update)
penalty for Candidate6 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
Candidat7
26
X X X selection Candidate7 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update7
X X
Penalty7
Candidate8
update for Candidate5 (zero update, medium update, large update
or zero update)
penalty for Candidate5 (0, 8, 16, 32, 64, 128, 256 or 511)
Candidat6
Candidate7
DESCRIPTION(2)
Philips Semiconductors
Candidate5
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
X X X
097
update for Candidate7 (zero update, medium update, large update
or zero update)
penalty for Candidate7 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
Candidat8
X X X selection Candidate8 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update8
X X
Penalty8
X X X
update for Candidate8 (zero update, medium update, large update
or zero update)
penalty for Candidate8 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
X X X X X X X position of LeftUpp measurement point for pan-zoom calculations
(resolution: 16 pixels)
PZpositionLeftUppY
099
write; S
X X X X X X X Y position of LeftUpp measurement point for pan-zoom calculations
(resolution: 4 lines)
PZpositionRightLowX 09A
write; S
X X X X X X X position of RightLow measurement point for pan-zoom calculations
(resolution: 16 pixels)
PZpositionRightLowY 09B
write; S
X X X X X X X Y position of RightLow measurement point for pan-zoom calculations
(resolution: 4 lines)
PZvectorStartX
write; F
09C
X X X X X X X X X start value of pan-zoom vectors
Product specification
098
SAA4993H
PZpositionLeftUppX
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DESCRIPTION(2)
PZvectorDeltaX
09D
write; F
X X X X X X X X X delta value of pan-zoom vectors
PZvectorStartY
09E
write; F
X X X X X X X X Y start value of pan-zoom vectors
PZvectorDeltaY
09F
write; F
X X X X X X X X Y delta value of pan-zoom vectors
GlobalMSEmsb
0A0
read; F
GlobalMSElsb
0A1
read; F
X X X X X X X X Global Mean Square Error (MSE) = summation within a field period of
X X X X X X X X squared differences in comparing vector shifted video from frame
memory (FM2/3) with new field input (FM1) in those lines coinciding
with new field lines. The window for the measurement is kept at
40 pixels horizontal and 20 field lines vertical from the border of the
video. Measurements is only done in fields where the de-interlacer is
active, otherwise reading is zero. In field doubling mode, MSE is zero
at the end of every new input field.
GlobalMTImsb
0A2
read; F
GlobalMTIlsb
0A3
read; F
GlobalACTmsb
0A4
read; F
GlobalACTlsb
0A5
read; F
VectTempCons
0A6
read; F
X X X X X X X X Vector temporal consistency = summation over a field period of
absolute differences of horizontal plus vertical components of vectors
newly estimated for each block compared with those vectors
estimated in the previous run at the same spatial block position.
It should be noted that a lower figure implies better consistency.
VectSpatCons
0A7
read; F
X X X X X X X X Vector spatial consistency = summation over a field period of absolute
differences of horizontal and vertical components of vectors compared
with those of the neighbour blocks (L, R, U and D); in the comparison,
all vector data is used from the previous estimator run. It should be
noted that a lower figure implies better consistency.
BlockErrCnt
0A8
read; F
X X X X X X X X burst error count (number of burst errors)
Read data; note 3
Philips Semiconductors
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
27
X X X X X X X X Global Motion Trajectory Inconsistency (MTI) = summation within a
X X X X X X X X field period of squared differences comparing shifted video from frame
memory (FM2/3 output) with filtered data that is rewritten to the frame
memory (FM2/3 input) in those lines coinciding with new field lines.
The window for the measurement is kept at 40 pixels horizontal and
20 field lines vertical from the border of the video. Measurement is
done only in fields where de-interlacer is active, otherwise reading is
zero; in field doubling mode, MTI is zero at the end of every new input
field.
X X X X X X X X global activity (ACT) = summation over a field period of the horizontal
X X X X X X X X plus the vertical components of the vectors of all blocks
Product specification
SAA4993H
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DESCRIPTION(2)
read; F
X X X X X X X X least error sum (summation over a field period of the smallest match
error that the estimator has found for each block: indicates reliability of
the estimation process)
YvecRangeErrCntmsb 0AA
read; F
X X X X X X X X Y vector range error count (number of vectors that have a vertical
component that is out of range for upconversion at the chosen
temporal position) (15 to 8)
YvecRangeErrCntlsb
0AB
read; F
X X X X X X X X Y vector range error count (7 to 0)
RefLineCountPrev
0AC
read; F
X X X X X X X X read out of (number of input (run-) lines − 40) used in previous field
RefLineCountNew
0AD
write; F
X X X X X X X X Write of [number of input (run-) lines − 40] to be used in new field
(actual maximum number of input lines in normal operation: 292;
register value 252). Nominally this is to be set as an exact copy of the
value read from RefLineCountPrev before a new field starts. In case
the effective number of input (run-) lines has increased,
RefLineCountNew should, for one field, be set to 255. This will occur
e.g. with decreasing vertical zoom magnification or changing from
525 lines video standard to 625 lines standard. If this is not done, a
deadlock will occur with too few lines processed correctly by the
motion estimator.
PanZoomVec0-X
0B0
read; F
X X X X X X X X pan-zoom vector 0 (8-bit X value)
PanZoomVec0-Y
0B1
read
28
0A9
FalconIdent
S
PanZoomVec0-Y
0
F
PanZoomVec1-X
0B2
read; F
PanZoomVec1-Y
0B3
read
StatusJump0
S
PanZoomVec1-Y
F
read; F
PanZoomVec2-Y
0B5
read
StatusJump1
S
PanZoomVec2-Y
F
X X X X X X X pan-zoom vector 0 (7-bit Y value)
X X X X X X X X pan-zoom vector 1 (8-bit X value)
X
read out of configuration pin JUMP0
X X X X X X X pan-zoom vector 1 (7-bit Y value)
X X X X X X X X pan-zoom vector 2 (8-bit X value)
X
read out of configuration pin JUMP1
X X X X X X X pan-zoom vector 2 (7-bit Y value)
PanZoomVec3-X
0B6
read; F
X X X X X X X X pan-zoom vector 2 (8-bit X value)
PanZoomVec3-Y
0B7
read; F
X X X X X X X pan-zoom vector 3 (7-bit Y value)
Product specification
0B4
SAA4993H identification: fixed bit, reading this bit as zero means
SAA4993H is present
SAA4993H
PanZoomVec2-X
Philips Semiconductors
LeastErrSum
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
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DESCRIPTION(2)
29
PanZoomVec4-X
0B8
read; F
X X X X X X X X pan-zoom vector 4 (8-bit X value)
PanZoomVec4-Y
0B9
read; F
X X X X X X X pan-zoom vector 4 (7-bit Y value)
PanZoomVec5-X
0BA
read; F
X X X X X X X X pan-zoom vector 5 (8-bit X value)
PanZoomVec5-Y
0BB
read; F
X X X X X X X pan-zoom vector 5 (7-bit Y value)
PanZoomVec6-X
0BC
read; F
X X X X X X X X pan-zoom vector 6 (8-bit X value)
PanZoomVec6-Y
0BD
read; F
X X X X X X X pan-zoom vector 6 (7-bit Y value)
PanZoomVec7-X
0BE
read; F
X X X X X X X X pan-zoom vector 7 (8-bit X value)
PanZoomVec7-Y
0BF
read; F
X X X X X X X pan-zoom vector 7 (7-bit Y value)
PanZoomVec8-X
0AE
read; F
X X X X X X X X pan-zoom vector 8 (8-bit X value)
PanZoomVec8-Y
0AF
read; F
X X X X X X X pan-zoom vector 8 (7-bit Y value)
EggSliceRgtMSB
0C0
read; F
X X X X X X X X result of right pixels egg-slice detector (15 to 8)
EggSliceRgtLSB
0C1
read; F
X X X X X X X X result of right pixels egg-slice detector (7 to 0)
EggSliceMixMSB
0C2
read; F
X X X X X X X X result of mixed pixels egg-slice detector (15 to 8)
EggSliceMixLSB
0C3
read; F
X X X X X X X X result of mixed pixels egg-slice detector (7 to 0)
SafeFbLine
0C9
read; F
X X X X X X X X reference line number (divided by two) at which the upconverter goes
into protection mode
EggBinGoodness
0CA
read; F
X X X X X X X X Goodness of the four egg-slice sections, from top to bottom, 2 bits per
section. Each section is represented with 2 bits in this register, where
bits 0 and 1 represent the top section and bits 6 and 7 represent the
lowest of the 4 sections. Each pair of bits indicate
00 = (ESR > 3⁄4ESM), 01 = (1⁄2ESM < ESR ≤ 3⁄4ESM),
10 = (1⁄4ESM < ESR ≤ 1⁄2ESM), 11 = (ESR ≤ 1⁄4ESM).
LoActCnt
0D3
read; F
X X X X X X X X number of blocks having low activity
HiActCnt
0D4
read; F
X X X X X X X X number of blocks having high activity
NullErrSum
0D5
read; F
X X X X X X X X sum of errors for the null candidate over the complete field; when no
null candidate is selected a value of 0xFF will be read
Philips Semiconductors
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter
with noise reduction
2001 Nov 23
NAME
Product specification
SAA4993H
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2. Selectable items are marked bold.
3. Almost all of the R(ead) and W(rite) registers of SAA4993H are double buffered. The Write registers are latched by a signal called New_field.
New_field gets set, when RE_F rises after RSTR (New_field is effectively at the start of active video). The Read registers are latched by a signal
called Reg_upd. Reg_upd gets set, when half the number of active pixels of the fourth line of vertical blanking have entered the SAA4993H
(Reg_upd will effectively be active 31⁄2 lines after the RE_A, RE_C and RE_E have ended). The only exception are the registers which are not
double buffered, these are as follows:
a) Write register 025H: power_on_reset
b) Write register 02FH, bit 1: CndSet
c) Read register 0B0H to 0BFH, 0AEH and 0AFH: pan_zoom_vectors, including FalconIdent (= 0), StatusJump0 and StatusJump1.
Philips Semiconductors
1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each display field.
Field and line rate converter
with noise reduction
2001 Nov 23
Notes
30
Product specification
SAA4993H
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDDI
core supply voltage
−0.5
+2.7
V
VDDE
external supply voltage (output pads)
−0.5
+3.6
V
IDD
supply current
−
600
mA
Io
output current
−
4
mA
Vi
input voltage for all I/O pins
−0.5
+3.6
V
Tstg
storage temperature
−40
+125
°C
Tj
junction temperature
0
125
°C
10 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
27
K/W
Rth(j-c)
thermal resistance from junction to case
2.9
K/W
11 CHARACTERISTICS
VDDE = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDI
core supply voltage
2.3
2.5
2.7
V
VDDE
external supply voltage (output pads)
3.0
3.3
3.6
V
IDD
supply current
−
280
−
mA
VOH
HIGH-level output voltage
2.4
−
−
V
VOL
LOW-level output voltage
−
−
0.4
V
VIH
HIGH-level input voltage
2
−
−
V
VIL
LOW-level input voltage
−
−
0.8
V
IOH
HIGH-level output current
10 ns slew rate
output;
VOH = 2.4 V
−4
−
−
mA
IOL
LOW-level output current
10 ns slew rate
output;
VOL = 0.4 V
4
−
−
mA
CL
load capacitance
−
−
50
pF
Ci
input capacitance
−
−
8
pF
ILI
input leakage current
−
−
1
µA
General
2001 Nov 23
31
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SYMBOL
SAA4993H
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Outputs; see Fig.5; note 1
IOZ
output current in 3-state mode
−
−
1
µA
td(o)
output delay time (except pin RESFM)
−0.5 < Vo < 3.6
−
−
21
ns
th(o)
output hold time (except pin RESFM)
4
−
−
ns
SR
slew rate
300
−
700
mV/ns
Inputs; see Fig.5; note 2
tsu(i)
input set-up time
6
−
−
ns
th(i)
input hold time
2
−
−
ns
Input CLK32; see Fig.5
tr
rise time
−
−
4
ns
tf
fall time
−
−
4
ns
δ
duty factor
40
−
60
%
Tcy
cycle time
30
−
39
ns
BST interface; see Fig.6
Tcy(BST)
BST cycle time
−
1
−
µs
tsu(i)(BST)
input set-up time
3
−
−
ns
th(i)(BST)
input hold time
6
−
−
ns
th(o)(BST)
output hold time
4
−
−
ns
td(o)(BST)
output delay
−
−
30
ns
SNERT interface; see Fig.7
tSNRST(H)
SNRST pulse HIGH time
500
−
−
ns
td(SNRST-SNCL)
delay SNRST pulse to SNCL LOW time
200
−
−
ns
Tcy(SNCL)
SNCL cycle time
0.5
−
1
µs
tsu(i)(SNCL)
input set-up time to SNCL
53
−
−
ns
th(i)(SNCL)
input hold time to SNCL
10
−
−
ns
th(o)
output hold time
30
−
−
ns
td(o)
output delay
−
−
330
ns
to(en)
output enable time
210
−
−
ns
Notes
1. Timing characteristics are measured with CL = 15 pF; IOL = 2 mA; RL = 2 kΩ.
2. All inputs except SNERT interface inputs, CLK32 input and BST/TEST inputs.
2001 Nov 23
32
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
tf
handbook, full pagewidth
90%
tr
90%
CLOCK
1.5 V
10%
10%
INPUT
DATA
MHB175
tsu(i)
OUTPUT
DATA
th(i)
data
valid
data transition
period
th(o)
td(o)
Fig.5 Data input/output timing diagram.
Tcy(BST)
handbook, full pagewidth
TCK
TDI, TMS
t su(i)(BST)
t h(i)(BST)
TDO
t h(o)(BST)
t d(o)(BST)
Fig.6 Boundary scan test interface timing diagram.
2001 Nov 23
33
MHB649
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
handbook, full pagewidth
SNCL
write sequence:
SNDA
a0
a1
a2
a3
a4
a5
a6
a7
a0
a1
a2
a3
a4
a5
a6
a7
w0
w1
w2
w3
w4
w5
w6
w7
r0
r1
r2
r3
r4
r5
r6
r7
read sequence:
SNDA
driven by
master
SNDA
driven by
SAA4993H
SNCL
50%
t su(i)(SNCL)
50%
50%
t h(i)(SNCL)
write sequence:
SNDA
read sequence:
SNDA
driven by
master
a6
a7
a6
a7
w0
w1
t o(en)
SNDA
driven by
SAA4993H
r0
t d(o)
Fig.7 SNERT interface timing diagram.
2001 Nov 23
t h(o)
34
r1
t d(o)
MHC058
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
Table 2
SAA4993H
YUV formats
FORMAT(2)
I/O PIN(1)
4:1:1
4:2:2
4 : 2 : 2 DPCM
YX7
Y07
Y17
Y27
Y37
Y07
Y17
Y07
Y17
YX6
Y06
Y16
Y26
Y36
Y06
Y16
Y06
Y16
YX5
Y05
Y15
Y25
Y35
Y05
Y15
Y05
Y15
YX4
Y04
Y14
Y24
Y34
Y04
Y14
Y04
Y14
YX3
Y03
Y13
Y23
Y33
Y03
Y13
Y03
Y13
YX2
Y02
Y12
Y22
Y32
Y02
Y12
Y02
Y12
YX1
Y01
Y11
Y21
Y31
Y01
Y11
Y01
Y11
YX0
Y00
Y10
Y20
Y30
Y00
Y10
Y00
Y10
UVX7
U07
U05
U03
U01
U07
V07
UC03
VC03
UVX6
U06
U04
U02
U00
U06
V06
UC02
VC02
UVX5
V07
V05
V03
V01
U05
V05
UC01
VC01
UVX4
V06
V04
V02
V00
U04
V04
UC00
VC00
UVX3
−
−
−
−
U03
V03
−
−
UVX2
−
−
−
−
U02
V02
−
−
UVX1
−
−
−
−
U01
V01
−
−
UVX0
−
−
−
−
U00
V00
−
−
Notes
1. Digit X refers to different I/O buses:
a) A = input from 1st field memory
b) B = output to 2nd field memory
c) C = input from 2nd field memory
d) D = output to 3rd field memory
e) E = input from 3rd field memory
f) F = main output
g) G = 2nd output for matrix purposes.
2. The first index digit defines the sample number and the second defines the bit number.
2001 Nov 23
35
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
12 PACKAGE OUTLINE
QFP160: plastic quad flat package;
160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height
SOT322-2
c
y
X
A
120
121
81
80
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
Lp
bp
L
pin 1 index
detail X
41
160
1
40
ZD
wM
bp
e
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
4.07
0.50
0.25
3.60
3.20
0.25
0.38
0.22
0.23
0.13
28.1
27.9
28.1
27.9
0.65
HD
HE
31.45 31.45
30.95 30.95
L
Lp
v
w
y
1.6
1.03
0.73
0.3
0.13
0.1
Z D(1) Z E (1)
1.5
1.1
1.5
1.1
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT322-2
135E12
MS-022
2001 Nov 23
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-11-03
00-01-19
36
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
If wave soldering is used the following conditions must be
observed for optimal results:
13 SOLDERING
13.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
13.2
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
13.3
13.4
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2001 Nov 23
Manual soldering
37
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
13.5
SAA4993H
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2001 Nov 23
38
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
14 DATA SHEET STATUS
DATA SHEET STATUS(1)
PRODUCT
STATUS(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
15 DEFINITIONS
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
ICs with field conversion functionality  Purchase of a
Philips IC with field conversion functionality does not
convey any implied license under any Intellectual Property
Right to use this IC in any field conversion application,
such as but not limited to a TV set having a display with a
100 Hz field refresh rate. A license can be obtained via the
Philips Corporate Intellectual Property department. For
more information, please contact Philips Corporate
Intellectual Property, Attn. Patent Licensing Manager, P.O.
Box 220, 5600 AE Eindhoven, The Netherlands, email:
[email protected].
16 DISCLAIMERS
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
2001 Nov 23
39
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA73
© Koninklijke Philips Electronics N.V. 2001
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp40
Date of release: 2001
Nov 23
Document order number:
9397 750 08704