PHILIPS SAA8117HL

INTEGRATED CIRCUITS
DATA SHEET
SAA8117HL
Digital camera USB interface IC
Product specification
File under Integrated Circuits, IC22
1999 Apr 02
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
CONTENTS
15
PACKAGE OUTLINE
16
SOLDERING
16.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
QUICK REFERENCE DATA
6
BLOCK DIAGRAM
7
PINNING
17
DEFINITIONS
8
FUNCTIONAL DESCRIPTION
18
LIFE SUPPORT APPLICATIONS
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
19
PURCHASE OF PHILIPS I2C COMPONENTS
8.10
8.11
8.12
Video synchronization
CIF formatter
Compression engine
Transfer buffer
SNERT interface
Sensor pulse generator
Pulse diagrams
USB video FIFO
PSIE-MMU, I2C-bus interface and USB RAM
space
ATX and external ATX interface
Audio
Power management
9
CONTROL REGISTER DESCRIPTION
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
SNERT (UART)
I2C-bus interface
Commands
End-points
Control top registers
Video FIFO registers
ADIF top registers
10
LIMITING VALUES
11
THERMAL CHARACTERISTICS
12
CHARACTERISTICS
13
TIMING
14
APPLICATION INFORMATION
1999 Apr 02
16.2
16.3
16.4
16.5
2
Philips Semiconductors
Product specification
Digital camera USB interface IC
1
SAA8117HL
2
FEATURES
APPLICATIONS
• Low-cost desktop video applications with USB interface.
• Medium resolution CCD sensors (PAL non-interlaced
mode) or VGA CCD sensors (progressive mode)
• D1 digital video input (8 bits YUV 4 : 2 : 2,
time multiplexed)
3
• Internal Pulse Pattern Generator (PPG) dedicated for
medium resolution Sharp or compatible sensors and
VGA sensors and for frame rate selection
The SAA8117HL is a monolithic integrated circuit which
can be used in PC video cameras to convert D1 video
signals and analog audio signals to properly formatted
USB packets.
• Video formatter (programmable CIF formatter and
compression engine) controlled via SNERT (UART)
interface
GENERAL DESCRIPTION
It is designed as a back-end for the SAA8110G or
SAA8112HL (general camera digital processing ICs) and
is optimized for use with the TDA8784/87 (camera
pre-processing IC) and the 83C51RC (microcontroller).
• Selectable output frame rate (1 fps in VGA, up to 15 fps
in CIF format)
• Video packetizer FIFO
• I2C-bus interface for communication between the USB
protocol hardware and the external microcontroller
• Integrated analog bus driver (ATX)
• Microphone/audio input to USB (FGA, ADC, PLL and
decimator filter)
• Integrated analog bus driver (ATX)
• Integrated main oscillator
• Miscellaneous functions e.g. power management,
PLL backup oscillator.
4
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
SAA8117HL
LQFP100
plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm
SOT407-1
1999 Apr 02
3
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
5 QUICK REFERENCE DATA
Measured over full voltage and operating temperature range.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
3.0
3.3
3.6
V
VDDA
analog supply voltage
3.0
3.3
3.6
V
IDD(tot)
total supply current
−
91
−
mA
I2C-bus
VDD = 3.3 V
Vi(bus)
input voltage on
Vo(bus)
output voltage on I2C-bus interface pin SDA
Vi(n)
input signal voltage on other pins
3.0 V < VDD < 3.6 V
low voltage TTL compatible V
Vo(n)
output signal voltage on other pins
3.0 V < VDD < 3.6 V
low voltage TTL compatible V
fclk
clock frequency
−
48
−
MHz
Ptot
total power dissipation
Tamb = 25 °C
−
300
−
mW
Tstg
storage temperature
−55
−
+150
°C
Tamb
operating ambient temperature
Tj
junction temperature
1999 Apr 02
interface pins
5 V tolerant TTL compatible V
5 V tolerant TTL compatible V
Tamb = 70 °C
4
0
25
70
°C
−40
−
+125
°C
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58
SNCL
SNDA
SNRES
RESERVED2
RESERVED1
YUV0
to
YUV7
GENPOR
RESET
76
51
SCL SDA
94
CLOCK UCPOR
95
93
64
77
TRC
96
DCDCON
100
97
99 98
56
63
I2C-BUS
INTERFACE
55
57
POWER
MANAGEMENT
65
66
SNERT
INTERFACE
AND HATCH
SAA8117HL
53
EXTERNAL
ATX
INTERFACE
USB
RAM SPACE
52
67
68
71
72
35, 36,
37, 38,
42, 43
44, 45
73
CIF
FORMATTER
COMPRESSION
ENGINE
TRANSFER
BUFFER
USB
VIDEO
FIFO
PSIE
MMU
74
SPEED
SUSPEND
VM
VP
RCV
VMO
VPO
Digital camera USB interface IC
BLOCK DIAGRAM
SMP
Philips Semiconductors
6
ndbook, full pagewidth
1999 Apr 02
SNAPSHOT
UCINT CLOCKON
SUSREADYNOT
OEBAR
ATXCTRL
5
60
HREF
VSYNC
LLC
49
50
47
ATX
61
AUDIO
ADC
VIDEO
SYNCHRONISATION
32, 25, 15
85, 84, 62, 7
MAIN
OSCILLATOR
PATTERN PULSE GENERATOR
(PPG)
19, 18 13, 12
17, 16 11, 10
23, 22,
21
24 20
B1 to B4
RG
A1 to A4
C1 to C3
28 29
SHP
27 33
CLK1
SHUTTER SHD
8
CLPDM
CLK2
31 30
9
HD
CLPOB
5
6
XIN1
VD
AUDIO
PLL
86
AUDIO
AMP
87
XIN2
XOUT1
MIC
89
90
WS
91
BCK
DA
ATXDM
VDD1 to VDD3
VDDA1 to VDDA4
70, 48, 41, 39
VDDD1 to VDDD4
54, 34, 26, 14
GND1 to GND4
88, 80, 78, 59, 4
AGND1 to AGND5
92, 75, 69, 46, 40
DGND1 to DGND5
3, 2, 1
81, 82, 83
FCE130
REF1 to REF3
M0 to M2
Product specification
SAA8117HL
Fig.1 Block diagram.
XOUT2
79
I2S-BUS
INTERFACE
ATXDP
Philips Semiconductors
Product specification
Digital camera USB interface IC
7
SAA8117HL
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
M2
1
I
test mode control signal bit 2
M1
2
I
test mode control signal bit 1
M0
3
I
test mode control signal bit 0
AGND1
4
P
analog ground 1 for main oscillator (48 MHz, 3rd overtone)
XIN1
5
I
oscillator input
XOUT1
6
O
oscillator output
VDDA1
7
P
analog supply voltage 1 for main oscillator (48 MHz, 3rd overtone)
CLPDM
8
O
dummy clamp pulse output to TDA8784/87
CLPOB
9
O
optical black clamp pulse output to TDA8784/87
B4
10
O
vertical CCD load pulse output (VH1X)
B3
11
O
vertical CCD load pulse output (VH3X)
B2
12
O
vertical CCD load pulse output
B1
13
O
vertical CCD load pulse output
GND1
14
P
ground 1 for output buffers
VDD1
15
P
supply voltage 1 for output buffers
A4
16
O
vertical CCD transfer pulse output (V4X)
A3
17
O
vertical CCD transfer pulse output (V3X)
A2
18
O
vertical CCD transfer pulse output (V2X)
A1
19
O
vertical CCD transfer pulse output (V1X)
SHUTTER
20
O
shutter control output for CCD charge reset
C3
21
O
horizontal CCD transfer pulse output
C2
22
O
horizontal CCD transfer pulse output (FH1)
C1
23
O
horizontal CCD transfer pulse output (FH2)
RG
24
O
reset output for CCD output amplifier gate
VDD2
25
P
supply voltage 2 for output buffers
GND2
26
P
ground 2 for output buffers
CLK1
27
O
pixel clock output to TDA8784/87and SAA8110G
SHP
28
O
preset sample-and-hold pulse output to TDA8784/87 (FCDS)
SHD
29
O
data sample-and-hold pulse output to TDA8784/87 (FS)
VD
30
O
vertical definition pulse output to SAA8110G
HD
31
O
horizontal definition pulse output to SAA8110G
VDD3
32
P
supply voltage 3 for output buffers
CLK2
33
O
double pixel clock output to SAA8110G
GND3
34
P
ground 3 for output buffers
YUV0
35
I
multiplexed input YUV-bit 0 (LSB)
YUV1
36
I
multiplexed input YUV-bit 1 input
YUV2
37
I
multiplexed input YUV-bit 2 input
YUV3
38
I
multiplexed input YUV-bit 3 input
VDDD1
39
P
digital supply voltage 1 for input buffers and predrivers and one part of the digital
core
1999 Apr 02
6
Philips Semiconductors
Product specification
Digital camera USB interface IC
SYMBOL
SAA8117HL
PIN
TYPE
DESCRIPTION
DGND1
40
P
digital ground 1 for input buffers and predrivers and for the digital core
VDDD2
41
P
digital supply voltage 2 for digital core
YUV4
42
I
multiplexed input YUV-bit 4
YUV5
43
I
multiplexed input YUV-bit 5
YUV6
44
I
multiplexed input YUV-bit 6
YUV7
45
I
multiplexed input YUV-bit 7
DGND2
46
P
digital ground 2 for input buffers and predrivers and for the digital core
LLC
47
I
line-locked clock input (delayed CLK2) for YUV-port from SAA8110G
VDDD3
48
P
digital supply voltage 3 for digital core
HREF
49
I
horizontal reference input for YUV-port from SAA8110G
VSYNC
50
I
vertical synchronization input for YUV-port from SAA8110G
RESET
51
I
Power-on reset input (for video processing and PPG)
RESERVED1
52
−
test pin (should not be used)
RESERVED2
53
−
test pin (should not be used)
GND4
54
P
ground 4 for output buffer
SNDA
55
I/O
SNCL
56
I
input clock for SNERT-interface (communication between SAA8117HL and
SAA8110G)
SNRES
57
O
output reset for SNERT-interface (communication between SAA8117HL and
SAA8110G)
SMP
58
O
output switch mode pulse for DC-to-DC power supply
AGND2
59
P
analog ground 2 for ATX (transceiver)
ATXDP
60
I/O
positive driver of the differential data pair input/output (ATX)
ATXDM
61
I/O
negative driver of the differently data pair input/output (ATX)
VDDA2
62
P
analog supply voltage 2 for ATX
SPEED
63
O
required output for ATX-backup solution
UCINT
64
O
interrupt output from USB protocol hardware to microcontroller
SUSPEND
65
O
control output from USB protocol hardware to microcontroller
VM
66
O
required output for ATX-backup solution (txdn)
VP
67
O
required output for ATX-backup solution (txdp)
RCV
68
I
required output for ATX-backup solution
DGND3
69
P
digital ground 3 for input buffers and predrivers and for the digital core
VDDD4
70
P
digital supply voltage 4 for one part of input buffers and predrivers and for the
digital core
VMO
71
I
required input or ATX-backup solution (rxdn)
VPO
72
I
required input for ATX-backup solution (rxdp)
OEBAR
73
O
required output for ATX-backup solution
ATXCTRL
74
I
required input for ATX-backup solution
DGND4
75
P
digital ground 4 for input buffers and predrivers and for the digital core
GENPOR
76
I
Power-on reset input (for USB protocol hardware)
1999 Apr 02
data I/O for SNERT-interface (communication between SAA8117HL and
SAA8110G)
7
Philips Semiconductors
Product specification
Digital camera USB interface IC
SYMBOL
SAA8117HL
PIN
TYPE
77
O
AGND3
78
P
analog ground 3 for FGA
MIC
79
I
microphone input
AGND4
80
P
analog ground 4 for FGA/ADC
REF1
81
I
reference input voltage 1 for FGA/ADC (double-bonding)
REF2
82
I
reference input voltage 2 for DACn (used in the ADC)
REF3
83
I
reference input voltage 3 for DACp (used in the ADC)
VDDA3
84
P
analog supply voltage 3 for FGA/ADC
VDDA4
85
P
analog supply voltage 4 for PLL
XIN2
86
I
oscillator input required for PLL backup solution
XOUT2
87
O
oscillator output required for PLL backup solution
AGND5
88
P
analog ground 5 for PLL
WS
89
I
I2S-bus word select (required for FGA/ADC backup solution)
DA
90
I
I2S-bus data (required for FGA/ADC backup solution)
BCK
91
I
I2S-bus clock (required for FGA/ADC backup solution)
DGND5
92
P
digital ground 5 for input buffers and predrivers and for the digital core
CLOCK
93
O
clock output from USB protocol hardware to microcontroller
SCL
94
I
slave I2C-bus clock input
SDA
95
I/O
slave I2C-bus data input/output
CLOCKON
96
O
control output for main oscillator switched on
SNAPSHOT
97
I
input for remote wake-up (snapshot)
DCDCON
98
O
control output from USB protocol hardware to power supply module
SUSREADYNOT
99
I
input from microcontroller for SUSPEND mode
TRC
100
I
threshold control input for enabling the clock (switching for power management)
UCPOR
1999 Apr 02
DESCRIPTION
output control from USB protocol hardware to microcontroller
8
Philips Semiconductors
Product specification
76 GENPOR
77 UCPOR
78 AGND3
79 MIC
80 AGND4
81 REF1
82 REF2
84 VDDA3
83 REF3
85 VDDD4
86 XIN2
87 XOUT2
88 AGND5
89 WS
SAA8117HL
90 DA
91 BCK
92 DGND5
93 CLOCK
94 SCL
95 SDA
96 CLOCKON
97 SNAPSHOT
98 DCDCON
100 TRC
handbook, full pagewidth
99 SUSREADYNOT
Digital camera USB interface IC
M2
1
75 DGND4
M1
2
74 ATXCTRL
M0
3
73 OEBAR
AGND1
4
72 VPO
XIN1
5
71 VMO
XOUT1
6
70 VDDD4
VDDA1
7
69 DGND3
CLPDM
8
68 RCV
CLPOB
9
67 VP
B4 10
66 VM
B3 11
65 SUSPEND
B2 12
64 UCINT
SAA8117HL
B1 13
63 SPEED
GND1 14
62 VDDA2
VDD1 15
61 ATXDM
A4 16
60 ATXDP
A3 17
59 AGND2
A2 18
58 SMP
A1 19
57 SNRES
SHUTTER 20
56 SNCL
C3 21
55 SNDA
C2 22
54 GND4
C1 23
53 RESERVED2
RG 24
52 RESERVED1
VDD2 25
Fig.2 Pin configuration.
1999 Apr 02
9
VSYNC 50
HREF 49
VDDD3 48
LLC 47
DGND2 46
YUV7 45
YUV6 44
YUV5 43
YUV4 42
VDDD2 41
DGND1 40
YUV3 38
VDDD1 39
YUV2 37
YUV1 36
YUV0 35
GND3 34
CLK2 33
VDD3 32
HD 31
VD 30
SHD 29
SHP 28
CLK1 27
GND2 26
51 RESET
FCE131
Philips Semiconductors
Product specification
Digital camera USB interface IC
8
8.1
SAA8117HL
This prefilter must be chosen by selecting prefilter B and
setting SN_Prefilter_B_Comb. Prefilter B-comb can be
used independently from prefilter A.
FUNCTIONAL DESCRIPTION
Video synchronization
The video synchronization module (see Fig.1) is capable
of locking onto the video signal thereby implementing a
horizontal gate signal HREF (HREF = HIGH when data is
valid) and a VS signal indicating the start of a new video
frame. This module expects, in the PAL mode, 288 active
lines from a total of 292 lines and in the VGA mode,
480 active lines from a total of 486 lines. The module
generates control signals for the CIF formatter.
8.2
The incoming 4 : 2 : 2 data is vertically filtered to 4 : 2 : 0
by throwing away colour samples. In the even lines the
V-samples are discarded, in the odd lines the U-samples.
The vertical scaling in PAL mode is from CIF (352 × 288)
to QCIF (176 × 144) only. This is done via a vertical
prefilter A (3 taps). In VGA mode a VPD-4 vertical filter is
applied to scale from 640 × 480 to CIF and QCIF.
From the QCIF image a sub-QCIF cut (128 × 96) can be
made. Due to the granularity of the cropping origin, a
UV interchange can occur. This interchange can be
corrected with SN_EIRRAH.
CIF formatter
The video data must be progressive (or non-interlaced)
and in 4 : 2 : 2 (UYVY) format. The CIF formatter module
(see Figs 1 and 3) is programmable to perform down
scaling from 512 × 288 (PAL mode) or 640 × 480 (VGA
mode) to 352 × 288 or 176 × 144 without affecting the
aspect ratio.
In VGA mode the CIF formatter can be bypassed to create
a full resolution snapshot. The snapshot can be in 4 : 2 : 0
and in 4 : 2 : 2 format, selectable with SN_4 : 2 : 2.
8.3
The horizontal scaling is achieved with a Variable Phase
Delay filter (VPD-4). To avoid aliasing, this module also
contains a prefilter which has three modes:
Compression engine
The compression engine module (see Figs 1 and 3) works
on CIF format only. The CIF data is compressed to a fixed
number of bytes per frame. This number can be selected
leading a compression factor of either 3 or 4. As a result
the data stream of CIF 4 : 2 : 0 equals the data stream of
QCIF 4 : 2 : 2 (3 times compression) or QCIF 4 : 2 : 0
(4 times compression). The algorithm is Philips
proprietary. Real-time decoding can be done in software
on any Pentium platform.
• Prefilter A (3 taps)
• Prefilter B (7 taps)
• Prefilter B-comb (13 taps).
Prefilter B-comb is similar to prefilter B, but inserts extra
taps with amplification 0.
handbook, full pagewidth
SN_4:2:2
SN_EIRRAH
SN_PAL_VGA
SN_Prefilter A_On/Off
YUV0 to YUV7
PREFILTER
A
SN_Output_Format_Select
DOWN
SCALER
PREFILTER
B
COMPRESSION
ENGINE
to
transfer
buffer
SN_Prefilter B_On/Off
SN_Compress
SN_Prefilter B_Comb
SN_Compression_Ratio
SN_Clk_Compress_On
FCE132
Fig.3 The CIF formatter and compression engine.
1999 Apr 02
10
Philips Semiconductors
Product specification
Digital camera USB interface IC
8.4
SAA8117HL
It should be noted that in case of medium resolution Sharp
or compatible sensors an external inverter driver is
required to convert the 3 V pulses into a voltage suitable
for the used CCD sensor. For the medium resolution Sharp
CCD sensor driver, the name of the pins to which the PPG
pulses must be connected are indicated between brackets
in the SAA8117HL pinning list (pins C3, B1 and B2 are not
used).
Transfer buffer
The transfer buffer module (see Fig.1) ensures a smooth
transfer of the data to the FIFO of the USB. Moreover the
transfer buffer can insert in band synchronization words in
the video data stream.
This function can be switched on and off with
SN_In band_Control in register CONTROL17_0.
The synchronization words can only be used with
non-compressed data streams and are formatted like
0x00 0xFF 0x<framecounter>7<linecounter>9.
The subscript denotes the number of bits and the frame
counter is circular incrementing.
For both type of sensors the PPG generates 8 different
frame rates (see Table 6). The active video size is
512 × 288 for PAL and 640 × 480 for VGA. The total H × V
size is 685 × 292 for PAL and 823 × 486 for VGA.
It should be noted that additional HD pulses are added
during the vertical blanking interval to reach a total of
312 lines in PAL mode and 525 lines in VGA mode as
required by the SAA8110G.
The non-compressed data is formatted like:
4 : 2 : 0: <optional sync word><Y0><Y1><Y2><Y3>
<C0><C2><Y4><Y5><Y6><Y7><C4><C6>....,
4 : 2 : 2: <optional sync word><Y0><Y1><Y2><Y3>
<U0><V0><U2><V2><Y4>....,
The following registers are associated with the PPG:
• CONTROL17_0
where C denotes U-data in the even lines (0, 2, 4, etc.)
and V-data in the odd lines (1, 3, 5, etc.).
• CONTROL17_2
8.5
• PPG_SHUTTERSPEED_1
• PPG_SHUTTERSPEED_0
SNERT interface
• PPG_CLPOB_START_LSB
In a USB camera the SAA8110G will operate on a clock
frequency which depends on the actual frame rate. For the
slowest frame rates, this frequency can be so low that the
SNERT communication is no longer functional over the
specified entire frequency range of the microcontroller.
The microcontroller must adapt its SNERT bus frequency
to a frequency appropriate for the current mode in which
the SAA8110G is operating.
• PPG_CLPOB_STOP_LSB
• PPG_CLPDM_START_LSB
• PPG_CLPDM_STOP_LSB
• CLPMSB.
8.7
The SAA8117HL itself is also partly controlled via SNERT.
The CIF formatter, compression engine and the PPG
function are controlled via SNERT. This SNERT interface
works independently from the frame rate and can always
be operated in the full frequency range.
8.6
For medium resolution CCD sensors (PAL):
• High-speed pulses, see Figs 4 and 5
• Horizontal pulses, see Fig.6
• Vertical pulses, see Figs 7 to 11.
For VGA-sensors:
Sensor pulse generator
• High-speed pulses, see Figs 12 to 14
The SAA8117HL incorporates a Pulse Pattern Generator
(PPG) function. The PPG can be used for PAL medium
resolution Sharp sensors (LZ2423) or compatible CCD
sensors. The SAA8117HL can also handle VGA type CCD
sensors, so a set of pulses is provided to simplify the use
of such sensors. Depending on the type of sensor, it will be
necessary to reformat these pulses externally according to
the sensor specification.
1999 Apr 02
Pulse diagrams
• Horizontal pulses, see Fig.15
• Vertical pulses, see Figs 16 to 21.
11
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0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0
9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
CLOCK ENABLE
C1 (FH1)
C2 (FH2)
Philips Semiconductors
Digital camera USB interface IC
handbook, full pagewidth
1999 Apr 02
CCD OUTPUT
12
RG (FR)
SHD (FS)
SHP(FCDS)
CLK1
CLK2
Product specification
Fig.4 High-speed pulses for PAL medium resolution (1).
SAA8117HL
FCE133
mode 0: 1/(4.8 MHz)
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1
2
3
0
1
2
3
0
3
0
1
2
3
0
1
2
3
CLOCK ENABLE
C1 (FH1)
C2 (FH2)
Philips Semiconductors
0
Digital camera USB interface IC
handbook, full pagewidth
1999 Apr 02
CCD OUTPUT
13
RG (FR)
SHD (FS)
SHP (FCDS)
CLK1
CLK2
Product specification
Fig.5 High-speed pulses for PAL medium resolution (2).
FCE134
SAA8117HL
mode 1: 1/(4 MHz)
mode 2: 1/(3 MHz)
mode 3: 1/(2.4 MHz)
mode 4: 1/(2 MHz)
mode 5: 1/(1.5 MHz)
mode 6: 1/(1 MHz)
mode 7: 1/(750 kHz)
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2
685/0
680
641 BLK
619 BLK
636 BLK
642
643
612 A511
613 A512
614 BLK
100 BLK
101 BLK
102 A1
103 A2
99
91
74
22
16
12
683
685/0
4
0
15
91
CLOCK ENABLE
(1)
Philips Semiconductors
4
Digital camera USB interface IC
handbook, full pagewidth
1999 Apr 02
1
HD
(1)
CLPOB
14
(1)
(1)
CLPDM
64
72
SHUTTER (OFDX)
FCE135
29
49
A1 (V1X)
39
59
A2 (V2X)
24
54
A3 (V3X)
34
64
A4 (V4X)
Product specification
Fig.6 Horizontal pulses for PAL medium resolution.
SAA8117HL
(1) CLPOB and CLPDM are programmable.
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A286
A287
A288
Hd
Hd
AL1
AL2
A1
A2
289
290
291
292
1
2
3
4
5
6
HD
VD
CLPOB (DCP)
CLPDM (BCP)
Philips Semiconductors
A285
Digital camera USB interface IC
handbook, full pagewidth
1999 Apr 02
INE#
B4 (VH1X)
15
B3 (VH3X)
SHUTTER (OFDX)
A1 (V1X)
A2 (V2X)
A3 (V3X)
Fig.7 Vertical pulses for PAL medium resolution (1).
Product specification
FCE136
SAA8117HL
A4 (V4X)
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2
1
4
1
4
1
64
72
HD
SHUTTER (OFDX)
Philips Semiconductors
292
Digital camera USB interface IC
handbook, full pagewidth
1999 Apr 02
INE#
B4 (VH1X)
49
29
49
29
59
39
59
39
A1 (V1X)
54
24
54
24
A2 (V2X)
64
34
64
A3 (V3X)
34
16
B3 (VH3X)
A4 (V4X)
FCE137
Product specification
SAA8117HL
Fig.8 Vertical pulses for PAL medium resolution (2).
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647
651
655
659
663
667
671
675
679
683
1
4
1
3
1
4
1
4
2
64
72
545
553
HD
RESET_DATA [9 to 0] + 8
584
RESET_DATA [9 to 0]
599
SHUTTER (OFDX)
Philips Semiconductors
Digital camera USB interface IC
handbook, full pagewidth
1999 Apr 02
INE#
599
17
614
B4 (VH1X)
49
29
684
664
49
29
B3 (VH3X)
59
39
9
674
644
554
59
39
A1 (V1X)
54
24
4
559
54
24
A2 (V2X)
64
34
14
669
64
34
A3 (V3X)
A4 (V4X)
FCE138
Product specification
SAA8117HL
Fig.9 Vertical pulses for PAL medium resolution (3).
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567
571
575
579
583
587
591
595
599
603
607
611
615
619
623
627
631
635
639
643
647
651
655
659
663
667
671
675
679
683
1
4
4
1
4
1
4
3
64
72
HD
SHUTTER (OFDX)
Philips Semiconductors
2
Digital camera USB interface IC
handbook, full pagewidth
1999 Apr 02
INE#
B4 (VH1X)
18
49
29
49
29
684
664
B3 (VH3X)
59
39
59
39
9
674
A1 (V1X)
54
24
54
4
24
A2 (V2X)
64
34
64
34
14
669
A3 (V3X)
A4 (V4X)
FCE139
Product specification
SAA8117HL
Fig.10 Vertical pulses for PAL medium resolution (4).
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5
1
4
1
4
4
64
72
64
72
HD
SHUTTER (OFDX)
Philips Semiconductors
3
Digital camera USB interface IC
handbook, full pagewidth
1999 Apr 02
INE#
B4 (VH1X)
49
29
49
29
59
39
59
39
A1 (V1X)
54
24
54
24
A2 (V2X)
64
34
64
A3 (V3X)
34
19
B3 (VH3X)
A4 (V4X)
FCE140
Product specification
SAA8117HL
Fig.11 Vertical pulses for PAL medium resolution (5).
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0
1
2
3
4
0
1
2
3
4
0
4
0
1
2
3
4
0
1
2
3
4
CLOCK ENABLE
C1
C2
Philips Semiconductors
Digital camera USB interface IC
handbook, full pagewidth
1999 Apr 02
CCD OUTPUT
C3
20
RG
SHD
SHP
CLK1
CLK2
Product specification
Fig.12 High-speed pulses for VGA sensors (1).
SAA8117HL
FCE141
mode 0: 1/(9.6 MHz)
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0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0
5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
CLOCK ENABLE
C1
C2
Philips Semiconductors
Digital camera USB interface IC
ndbook, full pagewidth
1999 Apr 02
CCD OUTPUT
C3
21
RG
SHD
SHP
CLK1
CLK2
mode 1: 1/(8 MHz)
mode 3: 1/(4 MHz)
FCE142
Product specification
SAA8117HL
Fig.13 High-speed pulses for VGA sensors (2).
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0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
CLOCK ENABLE
C1
C2
C3
Philips Semiconductors
Digital camera USB interface IC
ndbook, full pagewidth
1999 Apr 02
CCD OUTPUT
RG
22
SHD
SHP
CLK1
CLK2
FCE143
Product specification
Fig.14 High-speed pulses for VGA sensors (3).
SAA8117HL
mode 2: 1/(6 MHz)
mode 4: 1/(3 MHz)
mode 5: 1/(2 MHz)
mode 6: 1/(1.5 MHz)
mode 7: 1/(1 MHz)
2
823/0
771
818
766 BLK
767
728 A656
79 A7
71 BLK
72 BLK
70 D
73 A1
65 D
64
60
36
12
4
821
823/0
732 BLK
755
15
63
CLOCK ENABLE
(1)
(1)
CLPOB
(1)
(1)
CLPDM
2
22
2
22
2
22
Philips Semiconductors
751
HD
Digital camera USB interface IC
ndbook, full pagewidth
1999 Apr 02
731 A659
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SHUTTER
FCE144
23
A1
A2
A3
A4
25 28
B1
27 30
B2
24
29
31
(1) CLPOB and CLPDM are programmable.
Fig.15 Horizontal pulses for VGA sensors.
Product specification
26
B4
SAA8117HL
B3
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483
485
Hd
486
1
2
Hd
Hd
AL1
AL2
A1
3
4
5
6
7
HD
VD
CLPOB
CLPDM
SHUTTER
Philips Semiconductors
482
Hd
Digital camera USB interface IC
INE#
A480
ndbook, full pagewidth
1999 Apr 02
A476
A1
24
A2
A3
A4
B1
B2
B3
Fig.16 Vertical pulses for VGA sensors (1).
Product specification
FCE145
SAA8117HL
B4
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2
751
755
1
A2
RESET_DATA [9 to 0] + 20
22
22
RESET_DATA [9 to 0]
2
RESET_DATA [9 to 0] + 20
22
RESET_DATA [9 to 0]
2
RESET_DATA [9 to 0] + 20
22
A1
2
RESET_DATA [9 to 0]
22
2
SHUTTER
2
22
2
HD
Philips Semiconductors
486
Digital camera USB interface IC
ndbook, full pagewidth
1999 Apr 02
INE#
25
28
25
28
A4
27
30
27
30
B1
B2
24
29
24
29
26
31
B3
26
31
25
A3
B4
Product specification
Fig.17 Vertical pulses for VGA sensors (2).
SAA8117HL
FCE146
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687
691
695
699
703
707
711
715
719
723
727
731
735
739
743
747
751
755
3
751
755
2
779
799
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20
A2
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20
779
799
RESET_DATA [9 to 0] + 20
22
A1
2
RESET_DATA [9 to 0]
22
2
SHUTTER
779
799
22
2
HD
Philips Semiconductors
1
Digital camera USB interface IC
ndbook, full pagewidth
1999 Apr 02
INE#
26
A3
25
28
780
800
A4
27
30
780
800
B1
24
29
B2
26
31
B3
Fig.18 Vertical pulses for VGA sensors (3).
Product specification
FCE147
SAA8117HL
B4
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631
635
639
643
647
651
655
659
663
667
671
675
679
683
687
691
695
699
703
707
711
715
719
723
727
731
735
739
743
747
751
755
4
751
755
3
22
2
HD
2
22
2
22
SHUTTER
A1
Philips Semiconductors
2
Digital camera USB interface IC
ndbook, full pagewidth
1999 Apr 02
INE#
A2
27
A3
25
28
A4
27
30
B1
24
29
B2
26
31
B3
Fig.19 Vertical pulses for VGA sensors (4).
Product specification
FCE148
SAA8117HL
B4
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623
627
631
635
639
643
647
651
655
659
663
667
671
675
679
683
687
691
695
699
703
707
711
715
719
723
727
731
735
739
743
747
751
755
5
751
755
4
22
2
22
2
HD
22
2
22
2
22
2
2
SHUTTER
22
A1
Philips Semiconductors
3
Digital camera USB interface IC
ndbook, full pagewidth
1999 Apr 02
INE#
A2
28
A3
25
28
25
28
A4
27
30
27
30
B1
24
29
24
29
26
31
26
31
B2
B3
Fig.20 Vertical pulses for VGA sensors (5).
Product specification
FCE149
SAA8117HL
B4
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0
1
2
3
489
490
491
492
493
494
518
519
520
521
522
A1
A2
A3
Philips Semiconductors
INE#
Digital camera USB interface IC
ndbook, full pagewidth
1999 Apr 02
1/(6 MHz) = 0.167 µs
29
A4
B1
B2
B3
B4
FCE150
Product specification
SAA8117HL
Fig.21 Vertical pulses for VGA sensors (6).
Philips Semiconductors
Product specification
Digital camera USB interface IC
8.8
SAA8117HL
Moreover the FIFO is enabled and disabled with
I2C_Active.
USB video FIFO
I2C-bus
The USB video FIFO is programmed via the
(see Fig.22). The FIFO is designed to achieve three
different packets containing video on the isochronous USB
channel. Video data is contained in a chain of equally sized
USB packets, except for the last packet of a video frame
which is always smaller. The video frames can be
separated from each other by one or more 0-length
packets. For low frame rates (below 10 frames/s) there are
always 0-length packets in the stream. The host can
synchronize on the smaller packets for the high frame
rates and on the 0-length packets for the low frame rates.
The write process to the FIFO is controlled by the transfer
buffer and is not programmable.
The read process is executed in the PSIE-MMU and is
driven by the USB frame interval (1 ms). Every frame
interval the PSIE-MMU tries to read I2C_Packet_Size
bytes from the FIFO. This read process will not be started
when a new video frame is stored in the FIFO and there
are less than I2C_FIFO_Offset bytes written. The read
process stops if the next bytes are of another video frame,
or if the read-pointer overtakes the write-pointer.
For every mode the FIFO must be adjusted. There are
three parameters to program the video FIFO:
I2C_Read_Spacing determines the read rate. Its value can
easily be determined with the formula:
2
12000
I C_Read_Spacing < --------------------------------------------2
I C_Packet_Size
• I2C_Packet_Size: this value indicates the length of all
packets with video data except for the last packet of a
video frame
• I2C_FIFO_Offset: this value indicates the number of
data in the FIFO before a new packet is transmitted over
the USB
• I2C_Read_Spacing: this value indicates the number of
12 MHz clock cycles between read actions from the
FIFO.
handbook, full pagewidth
data to PSIE-MMU
data from transfer buffer
read
FIFO
write
I2C_FIFO_Offset
read
enable
I2C_Packet_Size
I2C_Read_Spacing
WRITE
SYNC
I2C_Active
FCE151
Ptr_to_start_Vframe
Fig.22 USB video FIFO.
1999 Apr 02
30
Philips Semiconductors
Product specification
Digital camera USB interface IC
8.9
SAA8117HL
PSIE-MMU, I2C-bus interface and USB RAM
space
8.10
ATX and external ATX interface
The SAA8117HL contains an analog bus driver, called the
ATX. It incorporates a differential and two single-ended
receivers and a differential transmitter. The interface to the
bus consists of a differential data pair (ATXDM and
ATXDP). The SAA8117HL contains also an interface to an
external ATX as backup solution.
The Programmable Serial Interface Engine (PSIE) and
Memory Management Unit (MMU) is the heart of the USB
protocol hardware (see Fig.23). It formats the actual
packets that are transferred to the USB and passes the
incoming packets to the right end-point buffers. These
buffers are allocated as part of the USB RAM space.
The microcontroller communicates via the I2C-bus with the
PSIE-MMU. The I2C-bus protocol distinguishes three
register spaces. These spaces are addressed via different
commands. The command is sent to the command
address. Depending on the command it is sent to the
PSIE-MMU and/or to the command interpreter which
configures the (de-)mux to open the path to the right
register space. Subsequent write/read to/from the data
address store or retrieve data from the register space is
selected by the command.
handbook, full pagewidth
PSIE-MMU
REGISTER
SPACE
PI_Address + 0X
to/from
microcontroller
(DE)MUX
SET MODE
REGISTER
SPACE
I2C-BUS
INTERFACE
PI_Address + 10
COMMAND
INTERPRETER
NON USB
AND
VIDEO FIFO
REGISTERS
to
PSIE-MMU
Fig.23 I2C-bus interface and register map.
1999 Apr 02
31
FCE152
Philips Semiconductors
Product specification
Digital camera USB interface IC
8.11
SAA8117HL
Audio
8.12
The PLL converts the 48 MHz to 256fs (fs = audio sample
frequency). There are three modes for the PLL to achieve
the sample frequencies of 48, 44.1 or 32 kHz
(see Table 1).
The USB requires the device to switch power states.
The SAA8117HL contains a power management module
since the device may not consume more than 500 µA
during the power state called SUSPEND. This requires
that even the crystal oscillator must be switched off.
The SAA8117HL is also not functional except for some
logic that enables the IC to wake-up the camera. After
wake-up of the SAA8117HL first the clock to the
microcontroller is generated and thereafter an interrupt is
generated to wake-up the controller. Therefore the clock of
the microcontroller is generated by the SAA8117HL.
In the Fixed Gain Amplifier (FGA) the microphone input is
amplified by 20 dB.
The bit stream ADC samples the audio signal. It runs at an
oversample rate of 256 times the base sample rate. In the
application, the bit stream can be converted to parallel
16-bit samples. This conversion is programmable with
respect to the effective sample frequency (dropping
sample results in a lower effective sample frequency) and
sample resolution. As a result the effective sample rate
can be determined.
Table 1
The power management module also sets a flag in register
I2C_SET_MODE_AND_READ. After a reset the
microcontroller should check this register via the I2C-bus
and find the cause of the wake-up. Different causes may
require different start-up routines.
ADC clock frequencies and sample frequencies
CLOCK
(MHz)
8.1920
11.2996
12.2880
DIVIDING
NUMBER
The internal video processing core uses another
VDDD domain which can be switched during SUSPEND.
SAMPLE
ADC CLOCK
FREQUENCY
(MHz)
(kHz)
1
32
4.096
2
16
2.048
4
8
1.042
8
note 1
note 1
1
44.1
5.6448
2
22.05
2.8224
4
11.025
1.4112
8
5.5125
0.7056
1
48
6.144
2
24
3.072
4
12
1.536
8
6
0.768
The PPG is switched off by setting SN_Resume and
resetting SN_PAL_VGA. In non CIF modes the power
consumption is reduced by resetting SN_Compress and
SN_CLK_Compress_On.
The SAA8117HL has the feature to independently
wake-up from SUSPEND, but requires a signal from the
microcontroller before going into SUSPEND (via the signal
on pin SUSREADYNOT).
Since the main oscillator of the SAA8117HL is switched off
during SUSPEND precautions are needed to avoid
undefined states when the clock is switched on. This is
ensured via the pins CLOCKON and TRC.
Pin CLOCKON goes HIGH as soon as the main oscillator
is switched on. The oscillator will need some time to make
a stable 48 MHz signal. However, the clock is only passed
through to other parts of the SAA8117HL when the level on
pin TRC reaches a certain threshold. The time needed to
reach the threshold can be trimmed with an RC-circuit.
Note
1. Not supported.
1999 Apr 02
Power management
32
Philips Semiconductors
Product specification
Digital camera USB interface IC
9
SAA8117HL
CONTROL REGISTER DESCRIPTION
This Chapter gives an overview of all registers.
9.1
SNERT (UART)
The following registers are accessible via SNERT (see Table 2).
Table 2
SNERT write registers of the SAA8117HL
ADDRESS
NAME
FUNCTION
FORMAT
C0
−
reserved
−
C1
−
reserved
−
C2
CONTROL17_0
various control bits
see Table 3
C3
CONTROL17_1
various control bits
see Table 5
C4
VP_SQCIF_OFFSET
vertical (MSN) and horizontal (LSN) offset for sub-QCIF
mode
nibble
C5
CONTROL17_2
various control bits
see Table 6
C6
PPG_SHUTTERSPEED_0
bits of shutter speed 0
see Table 8
C7
PPG_SHUTTERSPEED_1
bits of shutter speed 1
see Table 9
C8
PPG_CLPOB_START_LSB
LSB start position control for CLPOB pulse
byte
C9
PPG_CLPOB_STOP_LSB
LSB stop position control for CLPOB pulse
byte
CA
PPG_CLPDM_START_LSB
LSB start position control for CLPDM pulse
byte
CB
PPG_CLPDM_STOP_LSB
LSB stop position control for CLPDM pulse
byte
CC
CLPMSB
MSBs of CLPOB_Start, CLPOB_Stop, CLPDM_Start and
CLPDM_Stop
see Table 10
1999 Apr 02
33
Philips Semiconductors
Product specification
Digital camera USB interface IC
Table 3
7
6
SAA8117HL
Detailed description of SNERT register CONTROL17_0 (address 0xC2)
5
4
3
2
1
0
PARAMETER
EIRRAH
X
exchanges the chrominance irregularities when needed; toggle the bit to ensure
timing of chrominance signal; the value must be determined experimentally (can
be different for different modes)
Snapshot
1
transported in 4 : 2 : 2 format
0
transported in 4 : 2 : 0 format
Inband_Control
1
in band synchronization words are inserted in the video data stream
0
only active video data is transmitted over USB
Compression_Ratio
1
ratio is 4 times
0
ratio is 3 times
Compress
1
compression is active; only to be used in case (for this register) bit 2 = 1 and
bit 1 = 0 since compression functions are for CIF only; CIF format must be
compressed unless the frame rate is 3.75 Hz
0
compression module is switched off and power consumption is minimized for this
module
Output_Format_Select
X
X
see Table 4
PAL_VGA
Table 4
1
PAL sensor
0
VGA sensor
Detailed description of bit 2 and bit 1 of SNERT register CONTROL17_0
OUTPUT_FORMAT_SELECT
PARAMETER
2
1
FRAME RATE WITH RESPECT TO OUTPUT FORMAT
0
0
sub-QCIF
24
20
15
12
10
7.5
5
3.75
−
0
1
QCIF
24
20
15
12
10
7.5
5
3.75
−
1
0
CIF
−
−
15
12
10
7.5
5
3.75
−
1
1
VGA; note 1
−
−
−
−
−
−
−
−
0.9375
Note
1. Only valid when a VGA sensor is applied. The VGA output is not compressed.
1999 Apr 02
34
Philips Semiconductors
Product specification
Digital camera USB interface IC
Table 5
SAA8117HL
Detailed description of SNERT register CONTROL17_1 (address 0xC3)
7
6
5
4
X
X
X
X
3
2
1
0
PARAMETER
reserved
CLK_Compress_On
1
compression clock active
0
compression module is brought to low power state
Prefilter B_Comb
1
horizontal scaling factor exceeds 3 (only functioning if bit 1 is also set to logic 1);
this bit switches prefilter B to 13 taps
0
prefilter B is as described for bit 1
Prefilter B_On/Off
1
horizontal scaling factor exceeds 2; the prefilter with 7 taps is switched on
0
prefilter B is bypassed
Prefilter A_On/Off
Table 6
1
prefilter A with 3 taps is on; must be set to logic 1 when bit 2 is set to logic 1 to
obtain the overall wanted frequency response
0
prefilter A is bypassed
Detailed description of SNERT register CONTROL17_2 (address 0xC5)
7
6
5
X
X
X
4
3
2
1
0
PARAMETER
PIX_nr0 to PIX_nr2
3 LSBs of 10 bits pixel number for autoexposure control (7 LSBs in register 0xC6)
Shutter_Update_Buffer
1
update of the shutter speed is buffered
0
no buffering (immediately destroying of the current video frame)
Resume
1
video processing and PPG are switched of; if a VGA sensor is selected the vertical
transport pulses are not switched off but this must be done by selecting a PAL
sensor (register 0xC2 bit 0)
0
PGG pulses generated
PPG_Mode_Frame_Rate
X
1999 Apr 02
X
X
see Table 7
35
Philips Semiconductors
Product specification
Digital camera USB interface IC
Table 7
SAA8117HL
Detailed description of bit 2 to bit 0 of SNERT register CONTROL17_2
BIT
PARAMETER OF PPG_MODE_FRAME_RATE
2
1
0
VGA
PAL
0
0
0
24
24
0
0
1
20
20
0
1
0
15
15
0
1
1
10
12
1
0
0
7.5
10
1
0
1
5
7.5
1
1
0
3.75
5
1
1
1
0.9375
3.75
Table 8
7
6
Detailed description of SNERT register PPG_SHUTTERSPEED_0 (address 0xC6)
5
4
3
2
1
0
X
PARAMETER
1 LSB of 9-bit line number (8 MSBs in register 0xC7)
X
Table 9
X
X
X
X
X
X
7 MSBs of 10-bit pixel number (3 LSBs in register 0xC5)
Detailed description of SNERT register PPG_SHUTTERSPEED_1 (address 0xC7)
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
PARAMETER
8 MSBs of 9-bit line number (LSB in register 0xC6)
Table 10 Detailed description of SNERT register CLPMSB (address0xCC)
7
6
X
X
5
4
X
X
3
2
1
0
PARAMETER
2 MSBs of CLPOB_Start (LSBs in register 0xC8)
2 MSBs of CLPOB_Stop (LSBs in register 0xC9)
X
X
2 MSBs of CLPDM_Start (LSBs in register 0xCA)
X
1999 Apr 02
X
2 MSBs of CLPDM_Stop (LSBs in register 0xCB)
36
Philips Semiconductors
Product specification
Digital camera USB interface IC
9.2
SAA8117HL
I2C-bus interface
The I2C-bus interface uses two addresses:
• Command address for writing commands to the Memory Manager (MM)
• Data address for writing/reading data to/from the Memory Manager (MM).
The 6 MSBs of the two addresses are equal and are defined by the PI_address = 010111 (see Table 11). The LSBs of
the addresses differentiate between the command address and the data address. When bit 1 is logic 1 the address is
the command address (0x5E) and when bit 1 is logic 0 the address is one of the data addresses (0x5C or 0x5D).
Table 11 I2C-bus addresses
BIT
ADDRESS
7
6
5
4
3
2
1
0
0
1
0
1
1
1
0
0
0x5C: for writing data to the memory manager
0
1
0
1
1
1
0
1
0x5D: for reading data from the memory manager
0
1
0
1
1
1
1
0
0x5E: for writing commands
0
1
0
1
1
1
1
1
0x5F: not in use
9.2.1
COMMANDS
The commands listed in Table 12 must be sent to the I2C-bus address 0x5E.
Table 12 I2C-bus USB command codes
BIT
FUNCTION
7
6
5
0
0
end-point number
select end-point
0
1
end-point number
read/write status
1
0
end-point number
initialize/read status information
1
1
0
1
read/write register bank
1
1
1
0
0
X
X
X
not used
1
1
1
0
1
0
0
0
set non-USB register
1
1
1
1
0
0
0
0
read/write data
1
1
1
1
0
0
0
1
acknowledge setup
1
1
1
1
0
0
1
0
set buffer empty
1
1
1
1
1
0
1
0
set buffer full
1
1
1
1
0
1
0
0
read interrupt register
1
1
1
1
0
1
0
1
read current frame number
1
1
1
1
0
1
1
0
send resume
1
1
1
1
0
1
1
1
set status change bits
1
1
1
1
0
0
1
1
set mode
1999 Apr 02
4
3
2
1
0
address
37
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 13 Set mode and write register overview
BYTE
SET MODE AND WRITE
1
N1 timer; programmable timer for power management; counts 12 MHz cycles; must be bigger than number
of cycles needed for the microcontroller to go in power-down state after pin SUSREADYNOT is made LOW
2
N2 timer; programmable timer for power management; counts 12 MHz cycles; determines the time between
when the microcontroller clock is switched off and the main clock is switched off
3
PSIE-MMU control byte (see Table 14)
Table 14 Detailed description of PSIE-MMU control byte (byte 3)
7
6
5
X
X
X
4
3
2
1
0
PARAMETER
reserved
interrupt after isochronous audio transfer
1
for each isochronous audio transfer an interrupt to the microcontroller will
be generated; default set to logic 1 upon general Power-on reset and/or
bus reset by the SAA8117HL
0
no interrupts are given to the microcontroller
interrupt after isochronous video transfer
1
for each isochronous video transfer an interrupt to the microcontroller will
be generated; default set to logic 1 upon general Power-on reset and/or
bus reset by the SAA8117HL
0
no interrupts are given to the microcontroller
audio end-point
1
audio end-point enabled; default set to logic 1 upon general Power-on reset
and/or bus reset by the SAA8117HL
0
audio end-point disabled; the PSIE-MMU will not react on in-tokens on the
audio end-point
video end-point
1
video end-point enabled; default set to logic 1 upon general Power-on reset
and/or bus reset by the SAA8117HL
0
video end-point disabled; the PSIE-MMU will not react on in-tokens on the
video end-point
error debug mode
1999 Apr 02
1
interrupts are generated only in the event that the transfer is not
successfully completed; the microcontroller can read data from the interrupt
and status registers to see the cause of this error
0
all successful USB transactions are reported to the microcontroller via an
interrupt; default set to logic 0 upon general Power-on reset by the
SAA8117HL
38
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 15 Detailed description of PSI-MMU set mode and status byte
7
6
5
4
X
X
X
X
3
2
1
0
PARAMETER
reserved
remote wake-up status flag
1
remote wake-up when device is in SUSPEND mode
0
no remote wake-up
resume status flag
1
bus resume by the host when device is in SUSPEND mode
0
no bus resume
bus reset status flag
1
bus reset
0
no bus reset
power-up status flag
9.2.2
1
general power up reset
0
no power up reset
END-POINTS
The SAA8117HL has 6 logical end-points which are listed in Table 16.
Table 16 Mapping of logic to physical end-point numbers for used end-points
PHYSICAL END-POINT
LOGIC
END-POINT
BUFFER SIZE
Control end-point
0
Control end-point
1
Interrupt end-point
2
Interrupt end-point
Iso video end-point
Iso video end-point
END-POINT NAME
1999 Apr 02
OUT
IN
8
0
1
8
2
3
8
−
4
3
8
−
5
4
96.0
−
6
5
35.1
−
7
39
Philips Semiconductors
Product specification
Digital camera USB interface IC
9.2.3
SAA8117HL
CONTROL TOP REGISTERS
The following registers can be written on I2C-bus address 1 after the command 0xE8 on I2C-bus address 0.
Table 17 I2C-bus control top registers (base address 0x08)
ADDRESS
NAME
FUNCTION
0x08
CLKSHOP CONTROL
clock control
0x09
RSTGEN AND_PLL CONTROL
reset control
0x0A
I/O MUX CONTROL
mux block control
0x0B
POWER CONTROL ANALOG MODULES
power-on analog modules control
Table 18 Detailed description of I2C-bus control top register CLKSHOP CONTROL (address 0x08)
7
6
5
4
3
2
1
0
PARAMETER
select ADC clock source
1
sel_ad: clock generated from ADC
0
sel_pll: clock generated from PLL
set clock dividers for ADC
0
0
set_divide00: divided by 1
0
1
set_divide01: divided by 2
1
0
set_divide10: divided by 4
1
1
set_divide11: divided by 8
X
reserved
disable 48 MHz clock
1
dis_clk_48: disable 48 MHz clock
0
enable clock
disable receiver clock
1
dis_clk_rec: disable receiver clock
0
enable clock
disable ADC clock
1
dis_clk_ad: disable ADC clock
0
enable clock
X
1999 Apr 02
reserved
40
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 19 Detailed description of I2C-bus control top register RSTGEN AND PLL CONTROL (address 0x09)
7
6
5
4
3
2
1
0
PARAMETER
0
0
fcode00: 256 × 44.1 kHz
0
1
fcode01: 256 × 32 kHz
1
0
fcode10: 256 × 48 kHz
1
1
fcode11: 256 × 44.1 kHz
set PLL frequency
X
X
reserved
reset PSIE-MMU top module
1
upc_rst_mmu: resetting the USB protocol block (called PSIE-MMU) during
tests or in the event of errors
0
no reset
X
reserved
reset ADIF top module
1
upc_rst_adif: resetting the digital audio part during tests or in the event of
errors
0
no reset
reset AGC module
1
upc_rst_AGC: resetting the AGC control during tests or in the event of
errors
0
no reset
Table 20 Detailed description of I2C-bus control top register I/O MUX CONTROL (address 0x0A)
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
1999 Apr 02
PARAMETER
reserved
41
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 21 Detailed description of I2C-bus control top register POWER CONTROL OF ANALOG MODULES
(address 0x0B)
7
6
X
X
5
4
3
2
1
0
PARAMETER
reserved
power control PLL module
1
upc_pll_off: PLL power off
0
power on
X
reserved
power control ADC module left channel
1
upc_adl_off: power off
0
power on
power control ADC module right channel
1
upc_adr_off: power off
0
power on
power control AGC module left channel
1
upc_AGCl_off: power off
0
power on
power control AGC module right channel
1999 Apr 02
1
upc_AGCr_off: power off
0
power on
42
Philips Semiconductors
Product specification
Digital camera USB interface IC
9.2.4
SAA8117HL
VIDEO FIFO REGISTERS
Table 22 Overview of I2C-bus video FIFO registers (base address 0x04)
ADDRESS
NAME
FUNCTION
0x04
FIFO OFFSET
8 LSBs of the offset value
0x05
FIFO ACTIVE AND FIFI OFFSET
FIFO active and 3 MSBs of the offset value
0x06
PACKET SIZE
8 LSBs of packet size value
0x07
READ SPACING AND PACKET SIZE
read spacing and 2 MSBs of packet size value
Table 23 Detailed description of I2C-bus video FIFO register FIFO OFFSET (address0x04)
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
PARAMETER
FIFO offset
mode_fifo_offset: sets the minimum contents of the FIFO that has to be
reached, before a new video frame will be put on the USB bus. This value
can be set between 0 and 2047. Total of 11 bits with 8 LSBs in this register
and 3 MSBs in register 0x05.
Table 24 Detailed description of I2C-bus video FIFO register FIFO ACTIVE AND FIFI OFFSET (address 0x05)
7
6
5
4
3
2
1
0
PARAMETER
FIFO active
1
mode_active: FIFO is active and the contents of the other mode registers
should not be updated by the microcontroller (maledictive)
0
FIFO not active
X
X
X
X
reserved
FIFO offset
X
X
X
3 MSBs of the offset value; see also register 0x04
Table 25 Detailed description of I2C-bus video FIFO register PACKET SIZE (address 0x06)
7
6
5
4
3
2
1
0
PARAMETER
packet size
X
X
X
X
X
X
X
X
mode_packet_size: sets the packet size of the USB video channel. Packets
can vary in size between 0 and 1023. Total of 10 bits with 8 LSBs in this
register and 2 MSBs in register 0x07.
Table 26 Detailed description of I2C-bus video FIFO register READ SPACING AND PACKET SIZE (address 0x07)
7
6
5
4
3
2
1
0
PARAMETER
read spacing
X
X
X
X
X
X
mode_read_spacing: sets the periodicity of the read pulses; the periodicity
can be set from 1 to 63 (from ‘000001’ to ‘111111’)
packet size
X
1999 Apr 02
X
mode_packet_size: 2 MSBs of the value (8 LSBs in register 0x06)
43
Philips Semiconductors
Product specification
Digital camera USB interface IC
9.2.5
SAA8117HL
ADIF TOP REGISTERS
Table 27 Overview of I2C-bus ADIF top registers (base address 0x0C)
ADDRESS
NAME
FUNCTION
0x0C
AGC CONTROL GENERAL
AGC control general
0x0D
AGC CONTROL GAIN LEFT
AGC control gain left
0x0E
AGC CONTROL GAIN RIGHT
AGC control gain right
0x0F
ADIF CONTROL
I2S-bus input and ADIF2MMU
Table 28 Detailed description of I2C-bus ADIF top register ADIF CONTROL (address 0x0F)
7
6
5
4
3
2
1
0
X
PARAMETER
reserved
number of bytes per sample
0
0
0 (reserved)
0
1
1 (8 bits audio samples)
1
0
2 (16 bits audio samples)
1
1
3 (24 bits audio samples)
selection mono/stereo operation
0
mono
1
stereo
selection input for ADC path (ADIF mux)
0
digital input (from I2S-bus)
1
analog input (from Vin_left and Vin_right)
selection high-pass filter (DC filter) for ADC down-sample filter
0
high-pass filter off
1
high-pass filter on
selection UDAI serial input format
1999 Apr 02
0
0
I2S-bus
0
1
LSB justified, 16 bits
1
0
LSB justified, 18 bits
1
1
LSB justified, 20 bits
44
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDA
analog supply voltage
−0.5
+4.0
V
VDDD
digital supply voltage
−0.5
+4.0
V
Vn
voltage on
−0.5
+4.0
V
−0.5
+5.5
V
−0.5
VDD + 0.5
V
pins AGND and DGND
pins SCL and SDA
note 1
all other pins
Tstg
storage temperature
− 55
+150
°C
Tamb
operating ambient temperature
0
70
°C
Tj
junction temperature
−40
+125
°C
Note
1. 5 V tolerant buffers.
11 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1999 Apr 02
PARAMETER
CONDITIONS
thermal resistance from junction to ambient in free air
45
VALUE
UNIT
51
K/W
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
12 CHARACTERISTICS
VDDD = VDDA = 3.3 V ±10%; Tamb = 0 to 70 °C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDD
digital supply voltage
3.0
3.3
3.6
V
VDDA
analog supply voltage
3.0
3.3
3.6
V
VDGND
voltage on pins DGND
0
0
0
V
VAGND
voltage on pins AGND
0
0
0
V
IDDD
digital supply current
Tamb = 25 °C
−
70
−
mA
IDDA
analog supply current
Tamb = 25 °C
−
20
−
mA
Tamb
operating ambient temperature
0
25
70
°C
Inputs
DATA AND CONTROL INPUTS: PINS M0 TO M2, YUV0 TO YUV7, LLC, HREF, VSYNC, RESET, GENPOR, ATXCTRL,
RCV, VM0 AND VP0
VIL
LOW-level input voltage
−
−
0.8
V
VIH
HIGH-level input voltage
2
−
−
V
Outputs
DATA AND CONTROL OUTPUTS: PINS CLK2, SMP, SPEED, SUSPEND, VM, VP AND OEBAR
VOL
LOW-level output voltage
−
−
0.1VDDD
V
VOH
HIGH-level output voltage
0.85VDDD
−
−
V
CONTROL OUTPUTS: PINS RG, SHUTTER, C1 TO C3, CLK1, SHP AND SHD
VOL
LOW-level output voltage
−
−
0.8
V
VOH
HIGH-level output voltage
2.0
−
−
V
CONTROL OUTPUTS: PINS A1 TO A4 AND B1 TO B4
VOL
LOW-level output voltage
−
−
0.8
V
VOH
HIGH-level output voltage
2.6
−
−
V
CONTROL OUTPUTS: PINS CLPDM AND CLPOB
VOL
LOW-level output voltage
−
−
0.6
V
VOH
HIGH-level output voltage
2.2
−
−
V
Interfaces
I2S-BUS: PINS DA, BCK AND WS
VIL
LOW-level input voltage
−
−
0.3VDDD
V
VIH
HIGH-level input voltage
0.7VDDD
−
−
V
I2C-BUS AND
SNERT BUS: PINS SDA, SCL, SNDA, SNCL AND SNRES
VIL
LOW-level input voltage
−
0.7
V
−
VIH
HIGH-level input voltage
0.2VDDD + 0.9 −
VDDD + 0.5
V
VOL
LOW-level output voltage
note 1
−
−
0.4
V
VOH
HIGH-level output voltage
note 1
VDDD − 0.7
−
−
V
1999 Apr 02
46
Philips Semiconductors
Product specification
Digital camera USB interface IC
SYMBOL
PARAMETER
MICROCONTROLLER INTERFACE: PINS
AND
SAA8117HL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SUSREADYNOT, UCPOR, UCINT, CLOCK, CLOCKON, TRC, SNAPSHOT
DCDCON
VIL
LOW-level input voltage
note 2
−
VIH
HIGH-level input voltage
note 2
VOL
LOW-level output voltage
VOH
HIGH-level output voltage
−
0.7
V
0.2VDDD + 0.9 −
VDDD + 0.5
V
note 3
−
−
0.4
V
note 3
VDDD − 0.7
−
−
V
−
48
−
MHz
Audio Phase-Locked Loop (PLL)
fi
clock input frequency
fo
clock output frequency
−
11.2996
−
MHz
B
bandwidth
−
2.3
−
kHz
ζ
damping
−
0.98
−
note 4
∑∆ convertor
INPUTS
fi
input signal frequency
1
−
20
kHz
Vi(rms)
input voltage (RMS value)
−
800
−
mV
TRANSFER FUNCTION
N
order of the ∑∆
−
3
−
Nbit
number of output bits
−
1
−
Neqbit
equivalent output resolution (bit)
−
16
−
DRi
dynamic range at input
−
96.6
−
dB
fclk
clock frequency
−
−
5.6448
MHz
δ
clock frequency duty factor
−
50
−
%
note 5
Fixed Gain Amplifier (FGA)
LOAD
RL
load resistance
5
−
−
kΩ
CL
load capacitance
−
−
15
pF
TRANSFER FUNCTION
Vi(nom)(p-p)
nominal input voltage
(peak-to-peak value)
−
226.3
−
mV
A1
amplification
−
20
−
dB
Vo(nom)(rms)
nominal output voltage (RMS value)
−
800
−
mV
S/N
signal-to-noise ratio
note 6
−
60
−
dB
THD
total harmonic distortion
at HIGH-level;
note 7
−
−65
−
dB
Ri
input impedance
3.35
4.7
6.0
kΩ
Ro
output impedance
fi
input frequency
1999 Apr 02
±3 dB range
47
−
−
100
Ω
100
−
20000
Hz
Philips Semiconductors
Product specification
Digital camera USB interface IC
SYMBOL
PARAMETER
SAA8117HL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BIASING
Iref
reference current
−
25
−
µA
FGA/∑∆ path
TRANSFER FUNCTION
A1
amplification
−
20
−
dB
S/N
signal-to-noise ratio
51
60
70
dB
THD
total harmonic distortion
−70
−66
−61
dB
ATX transceiver
DRIVER CHARACTERISTICS IN FULL SPEED MODE: PINS ATXDP AND ATXDM
fo(sample)
audio sample output frequency
4
−
48
MHz
tt(rise)
rise transition time
CL = 50 pF
4
−
20
ns
tt(fall)
fall transition time
CL = 50 pF
4
−
20
ns
tt(match)
transition time matching
note 8
90
−
110
%
Vo(cr)
output signal crossover voltage
1.3
−
2.0
V
Zo
driver output impedance
30
−
42
Ω
steady state
drive
RECEIVER CHARACTERISTICS IN FULL SPEED MODE: PINS ATXDP AND ATXDM
fs
audio sample input frequency
5
−
55
kHz
fi(D)
data input frequency rate
−
12.00
−
Mbits/s
tframe
frame interval
−
1.000
−
ms
Notes
1. This applies the outputs: pins SDA and SNDA.
2. This applies the inputs: pins SUSREADYNOT, TRC and SNAPSHOT.
3. This applies the outputs: pins CLOCK, UCINT, UCPOR, CLOCKON and DCDCON.
4. Frequencies depend on PLL settings (see Table 1).
Vi
5. Defined here as: 20 × log ------------------ where Vi = input voltage and Vn(i)(eq) = equivalent input noise voltage.
V n(i)(eq)
6. The noise is measured with A-weighting at the nominal input voltage.
7. The distortion is measured at a maximum output voltage of 2.4 V (p-p).
t t(rise)
8. Transition time matching: t t(match) = -----------t t(fall)
1999 Apr 02
48
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
13 TIMING
VDDD = VDDA = 3.3 V ±10%; load capacitance = 10 pF; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data input related to LCC (see Fig.24)
Pins YUV0 toYUV7, HREF and VSYNC
tsu(i)(D)
data input set-up time
1
−
−
ns
th(i)(D)
data input hold time
1
−
−
ns
−2
−1.5
0
ns
PPG high-speed pulses for PAL medium resolution sensors; mode 0 (see Fig.25)
td1
delay between falling edge C2 and rising edge C1
td2
delay between rising edge C2 and falling edge C1
1
1.5
2
ns
td3
delay between falling edge C1 and rising edge SHP
−3
−1.5
−1
ns
td4
delay between rising edge C1 and rising edge SHD
−0.5
0
+0.5
ns
td5
delay between rising edge C1 and falling edge RG
0.5
1
2
ns
td6
delay between falling edge CLK1 and rising edge C1
0
1
2
ns
td7
delay between rising edge CLK1 and falling edge C1
−0.5
0
+0.5
ns
td8
delay between rising edge CLK2 and rising edge C1
−2
0
+2
ns
tWH(C1)
C1 pulse width HIGH
164
165
−
ns
tWL(C2)
C2 pulse width LOW
166
167
−
ns
tWL(SHP)
SHP pulse width LOW
81
82
−
ns
tWL(SHD)
SHD pulse width LOW
81
82
−
ns
tWL(RG)
RG pulse width LOW
83
84
−
ns
tWL(CLK1)
CLK1 pulse width LOW
164
165
−
ns
tWH(CLK2)
CLK2 pulse width HIGH
79
80
−
ns
tr
rise time
pulse C1
−
4.5
−
ns
pulse C2
−
4
−
ns
pulse RG
−
4
−
ns
pulse SHP
−
4
−
ns
−
4
−
ns
pulse C1
−
4
−
ns
pulse C2
−
4
−
ns
pulse RG
−
4
−
ns
pulse SHP
−
4.5
−
ns
pulse SHD
−
4.5
−
ns
note 1
pulse SHD
tf
1999 Apr 02
fall time
note 1
49
Philips Semiconductors
Product specification
Digital camera USB interface IC
SYMBOL
SAA8117HL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PPG high-speed pulses for VGA sensors (see Fig.26)
td1
delay between rising edge C2 and rising edge C1
61
62
63
ns
td2
delay between rising edge C3 and rising edge C2
61
62
63
ns
td3
delay between rising edge SHP and falling edge C3
−1.5
−1
+0.5
ns
td4
delay between falling edge SHD and rising edge C2
8
9
10
ns
td5
delay between rising edge SHD and rising edge C3
−12
−11
−10
ns
td6
delay between rising edge RG and rising edge C1
−0.5
0
+0.5
ns
td7
delay between rising edge C1 and falling edge CLK1
18
19
21
ns
td8
delay between rising edge C1 and rising edge CLK2
20
21
22
ns
tWH(C1)
C1 pulse width HIGH
81
82
−
ns
tWH(C2)
C2 pulse width HIGH
81
82
−
ns
tWH(C3)
C3 pulse width HIGH
82
85
−
ns
tWL(SHP)
SHP pulse width LOW
21
22
−
ns
tWL(SHD)
SHD pulse width LOW
43
44
−
ns
tWL(RG)
RG pulse width LOW
21
22
−
ns
tWH(CLK1)
CLK1 pulse width HIGH
81
82
−
ns
tWH(CLK2)
CLK2 pulse width HIGH
41
43
−
ns
Note
1. Load capacity = 11 pF; VDDD = VDDA = 3.3 V; Tamb = 25 °C.
handbook, full pagewidth
LCC
tsu(i)D
th(i)D
data input
FCE153
Fig.24 Data input timing.
1999 Apr 02
50
Philips Semiconductors
Product specification
Digital camera USB interface IC
tWH(C1)
handbook, full pagewidth
C1
SAA8117HL
50%
50%
50%
td1
C2
td2
50%
50%
tWL(C2)
50%
SHP
50%
td3
tWL(SHP)
SHD
tWL(SHD)
50%
tWL(RG)
td4
50%
td5
RG
50%
50%
td7
td6
CLK1
50%
50%
tWL(CLK1)
td8
CLK2
50%
50%
tWH(CLK2)
FCE154
Fig.25 PPG high-speed pulses for PAL medium resolution sensors (mode 0).
1999 Apr 02
51
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
tWH(C1)
handbook, full pagewidth
C1
50%
50%
50%
td1
tWH(C2)
C2
50%
50%
td2
C3
50%
tWH(C3)
td3
tWL(SHP)
50%
SHP
50%
td4
SHD
td5
50%
50%
td6
tWL(SHD)
50%
RG
td7
CLK1
tWL(RG)
50%
50%
td8
CLK2
50%
tWH(CLK1)
50%
50%
FCE155
tWH(CLK2)
Fig.26 PPG high-speed pulses for VGA sensors (mode 2).
1999 Apr 02
50%
52
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
14 APPLICATION INFORMATION
handbook, full pagewidth
MIC
SYNC
SENSOR
TDA8784/87
SAA8110G
OR
SAA8112HL
USB
YUV
SAA8117HL
48 MHz
CLOCKON
TRC
PPG pulses
SNERT
I2C-BUS
MICROCONTROLLER
power
management
FCE157
Fig.27 Application diagram.
1999 Apr 02
53
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
15 PACKAGE OUTLINE
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
c
y
X
A
51
75
50
76
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
Lp
L
pin 1 index
100
detail X
26
1
25
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.5
1.3
0.25
0.28
0.16
0.18
0.12
14.1
13.9
14.1
13.9
0.5
HD
HE
16.25 16.25
15.75 15.75
L
Lp
v
w
y
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
1.15
0.85
7
0o
1.15
0.85
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-12-19
97-08-04
SOT407-1
1999 Apr 02
EUROPEAN
PROJECTION
54
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
If wave soldering is used the following conditions must be
observed for optimal results:
16 SOLDERING
16.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
16.2
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
16.3
16.4
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
1999 Apr 02
Manual soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
55
Philips Semiconductors
Product specification
Digital camera USB interface IC
16.5
SAA8117HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Apr 02
56
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
17 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Apr 02
57
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
NOTES
1999 Apr 02
58
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
NOTES
1999 Apr 02
59
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545006/750/01/pp60
Date of release: 1999 Apr 02
Document order number:
9397 750 04381