Philips Semiconductors Linear Products Product specification 6-Bit A/D converter (parallel outputs) DESCRIPTION NE5037 PIN CONFIGURATION The NE5037 is a low cost, complete successive-approximation analog-to-digital (A/D) converter, fabricated using Bipolar/I2L technology. With an external reference voltage, the NE5037 will accept input voltages between 0V and VREF. An external START pulse of at least 300ns in duration will provide the 6-bit result of the conversion in parallel format. Full conversion with no missing codes occurs in 9µs. N Package VCC 1 2 15 B4 VIN 3 14 B3 ANALOG GND 4 13 B2 DIGITAL GND 5 12 B1 VREF FEATURES 16 B5 (MSB) CLK 6 • TTL-compatible inputs and outputs • 3-State output buffer • Easy interface to CMOS microprocessors • Fast conversion—9µs • Guaranteed no missing codes over full temp range • Single-supply operation, +5V • Positive true binary outputs • High-impedance analog inputs START 11 7 B0 10 EOC CS 8 9 EO TOP VIEW • µP-based appliances • Light level monitors • Head position sensing • Electronic toys • Joystick interface APPLICATIONS • Temperature control ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 0 to +70°C NE5037N 0406C 16-Pin Plastic Dual In-Line Package (DIP) BLOCK DIAGRAM VCC 1 VREF 2 COM 1/2 LSB IIN 6–BIT DAC V/I IO DB VIN AGND DGND CLK 3 DB5 V/I 4 CONTROL LOGIC 5 SAR 11 DB DBO 6 EOC 7 START August 31, 1994 16 8 CS 10 EOC 9 EOC 582 853-0939 13721 Philips Semiconductors Linear Products Product specification 6-Bit A/D converter (parallel outputs) NE5037 ABSOLUTE MAXIMUM RATINGS RATING UNIT VCC SYMBOL Power supply voltage PARAMETER 7 V VREF Reference voltage 7 V VIN(Analog) Analog input voltage 7 V VIN(Digital) Digital input voltage (CS, OE, START, CLK) 7 V DOUT Data outputs (DB0 to DB5) 3-state mode 7 V Enabled mode (each output) 5 mA EOC End of conversion ∆GND Analog GND to digital GND VCC TA Operating temperature range TSTG Storage temperature range TSOLD Lead soldering temperature (10 seconds) PD Maximum power dissipation, TA=25°C (still-air)1 ±1 V 0 to 70 °C -65 to 150 °C 300 °C 1450 mW N package NOTES: 1. Derate above 25°C at the following rates: N package=11.6mW/°C DC ELECTRICAL CHARACTERISTICS VCC=5.0V; VREF=2.0V; Clock=1MHz; 0°C ≤ TA ≤ 70°C unless otherwise specified. Typical values are specified at 25°C SYMBOL PARAMETER TEST CONDITIONS Resolution LIMITS Min 6 Relative accuracy1,2 +4.75 Typ Max UNIT 6 6 Bits 1/4 1/2 LSB VCC Positive supply voltage εFS Full-scale gain error2,3,4 +5.0 +5.50 V VREF=2.0V, TA=25°C ±1 ±2 LSB εZS Zero-scale offset error2 PSR Power supply rejection, Max change in full-scale2 IIN Analog input bias current IREF Reference bias current RIN Analog input resistance VIH Logic ”1’ input voltage VIL Logic ”0’ input voltage 0.8 V IIH Logic ”1’ input current 10 µA IIL Logic ”0’ input current 10 µA IOH Logic ”1’ output current5 2.4V≤VOH 300 µA IOL Logic ”0’ output current5 VOL≤0.4V 1.6 mA IOZ 3-State leakage current ±0.1 ±40 µA ICC Positive supply current 18 24 mA PD Power dissipation 132 mW VREF=2.0V, TA=25°C ±1/2 -1/2, +2 LSB VREF=2.0V, 4.75V≤VCC≤5.5V ±1/2 ±1 LSB 0≤VIN≤2.5V 1 10 µA 0≤VREF≤2.5V 1 10 3 30 µA MΩ 2.0 V 1 NOTES: 1. Relative accuracy is defined as the deviation of the code transition points from the ideal code transition points on a straight line drawn from zero-scale to full-scale of the device. 2. Specifications given in LSBs refer to the weight of the least significant bit at the 6-bit level which is 1.56% of the full-scale voltage. 3. Full-scale gain error is the deviation of the full-scale code transition point (111110 to 111111) from its ideal value. 4. The analog input voltage (VIN) range is 0V to VREF nominally, with the output remaining at 111111 even though the input may increase from VREF to VCC. (For optimum performance, VREF can be any value from 1.5V to 2.5V.) 5. The data outputs have active pull-ups. The EOC line is open-collector with a nominal 5kΩ internal pull-up resistor. August 31, 1994 583 Philips Semiconductors Linear Products Product specification 6-Bit A/D converter (parallel outputs) NE5037 AC ELECTRICAL CHARACTERISTICS VCC=5.0V; VREF=2.0V; Clock=1MHz; 0°C ≤ TA ≤ 70°C unless otherwise specified. Typical values are specified at 25°C (Refer to AC test figures.) SYMBOL PARAMETER fMAX Maximum clock frequency tW tCONV TO FROM LIMITS TEST CONDITIONS Min Typ UNIT Max 1 MHz Start pulse width 300 ns Minimum positive/negative clock pulse width 300 ns Conversion time delay1 tP (OUT DATA) Propagation tP (OUT EOC) Propagation delay2 tP (3-STATE) Propagation delay, 3-State 9 Clock cycles Data out OE TA=25°C tR=tF≤20ns 500 ns EOC Clock TA=25°C tR=tF≤20ns 800 ns 3-State Data OE TA=25°C tR=tF≤20ns 500 ns NOTES: 1. Propagation delay of data outputs is defined as the delay in the data outputs reading their final value after the low going edge of OE. 2. Propagation delay of EOC is defined as the delay in EOC going low, following the low going edge of the 9th clock pulse after the start pulse. The comparator determines whether the output current of the DAC is greater or less than the input current, which is converted from the unknown analog input voltage through the V/I converter. If the DAC output is greater, that bit of the DAC is set to ”0’ and the corresponding output buffer goes to ”0’ simultaneously. If it is less, it stays at ‘1’ and the output buffer also stays at ‘1’. On successive clock pulses, successive bits of the DAC are tried and the corresponding output buffer represents the bits of the DAC. On the eighth low-going edge of the clock pulse (after the receipt of the start pulse), the EOC pin goes low, thereby indicating that the conversion is complete. The output data is now valid. In order to access the result of the conversion, the OE pin must be set to a low level. EOC is reset to a high state when OE is low. When OE is in a ”1’ state, the output buffers are in a high impedance state. CIRCUIT DESCRIPTION NE5037 is a complete 6-bit, parallel output, microprocessor compatible, A/D converter which incorporates the successive-approximation method. The chip includes the internal control logic, the successive-approximation register (SAR), 6-bit DAC, comparator and output buffers. An externally-generated clock source (max frequency=1MHz) must be provided to Pin 6. An external reference voltage supplied to Pin 2 sets the full-scale range of the A/D converter. The CS pin must be at a low level prior to the start of the conversion process. Upon receipt of a START pulse, the internal control logic resets the SAR. On the first low-going edge of the clock pulse, successive approximation conversion commences. Successive bits beginning with the MSB (D5) are supplied to the input of the internal 6-bit current output DAC by the I2L successive approximation register. CS ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ DON’T CARE START ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ Refer to Figure 1 for the timing diagram. ÉÉ ÉÉ ÉÉ ÉÉ CLK OE EOC DATA OUTPUTS HIGH IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE DATA READY HIGH AVAILABLE Figure 1. Timing Diagram August 31, 1994 584 HIGH AVAILABLE Philips Semiconductors Linear Products Product specification 6-Bit A/D converter (parallel outputs) NE5037 The reference input and the analog voltage input must both remain stable during conversion to insure accuracy and proper operation. This can be done by adequately bypassing these inputs and/or keeping the impedance of these inputs at or below 2kΩ. TRANSFER CHARACTERISTICS The ideal transfer characteristic of the NE5037 is shown in Figure 2. The NE5037 is designed to have a nominal LSB offset so that the code transition points are located LSB on either side of the exact analog inputs for a given code. 111111 1DIGITAL OUTPUT CODE Thus the first transition (000000 to 000001) will occur at an input of LSB (15.63mV with a VREF of 2.0V). Subsequent transitions will occur at nominal increments of 1 LSB. The last transition (to full-scale—111111) will occur at 62.5 LSB (1.953V at VREF of 2.0V). LAYOUT PRECAUTIONS Analog ground (Pin 4) and digital ground (Pin 5) are not connected internally and should be connected together as close to the device as possible for optimum performance. The circuit will operate with as much as ±200mV between the two grounds but some degradation will occur. The leads to the analog inputs should be kept as short as possible to minimize noise pick-up. Input bypass capacitors from the analog inputs to ground will eliminate noise pick-up. Power supplies should be decoupled with at least 1µF located close to the device to minimize the effects of noise spikes. August 31, 1994 111110 111101 111100 LSB V REF 64 FOR 111111 OUTPUT VIN = VREF — LSB — 1/2 LSB 000011 000010 BUILT–IN OFFSET 62.5LSB 000001 62.5 V 64 REF 125/2 LSB 123/2 LSB 121/2 LSB 119/2 LSB 7/2 LSB 5/2 LSB 3/2 LSB 1/2 LSB 000000 ANALOG INPUT Figure 2. Ideal Transfer Characteristics 585 Philips Semiconductors Linear Products Product specification 6-Bit A/D converter (parallel outputs) NE5037 TYPICAL PERFORMANCE CHARACTERISTICS Zero–Scale Offset Error vs Temp Zero–Scale Offset Error vs vcc +1 +31/2 +1/4 25 50 VREF = 2.0V TA = 25oC +3/4 +31/2 +1/4 0 4.75 0 0 75 Full–Scale GAIN Error vs Temp +1/4 5.25 5.5 1.5 Full–Scale Gain Error vs vcc +1 +1/2 0 25 50 VREF = 2.0V TA = 25oC +1 1/2 +1 +1/2 0 4.75 75 TA (oC) Full–Scale Gain Error vs vREF VCC = 5.0V TA = 25oC +1 1/2 +1 +1/2 0 5.0 5.25 5.5 10.0 1 9.0 VCC = 4.75V I OH(mA) I OL(mA) VCC = 4.75V VCC = 5.0V VCC = 5.0V 3 2 2 8.0 IOL @ VOL = 0.4VDC IOL @ VOL = 2.4VDC 0 0 25 50 TA VCC = 4.75V 7.0 1 IOL @ VOL = 0.4VDC 0 75 6.0 0 (oC) 25 50 75 0 TA (oC) IOH vs Temp (EOC) 0.5 0.4 I OH(mA) I CC(mA) VCC = 5.0V VREF = 2.0V VCC = 5.5V 15 VCC = 4.75V VCC = 4.75V 0.3 14 0.2 13 0.1 IOH @ VOH = 2.4VDC 0 25 50 75 0 August 31, 1994 25 50 TA (oC) TA (oC) 586 25 50 TA (oC) ICC vs Temp (EOC) 17 16 2.5 IOH vs Temp (Data Output) 4 VCC = 5.0V 2.0 VREF (VOLTS DC) IOL vs Temp (EOC) IOL vs Temp (Data Output) 3 1.5 VCC (VOLTS DC) 4 2.5 +2 Z–F GAIN ERROR (LSB’s) VCC = 5.0V VREF = 2.0V 2.0 VREF (VOLTS DC) +2 Z–F GAIN ERROR (LSB’s) Z–F GAIN ERROR (LSB’s) +31/2 VCC (VOLTS DC) +2 +1 1/2 VCC = 5.0V TA = 25oC +3/4 0 5.0 TA (oC) I OL(mA) Z–F OFFSET ERROR (LSB’s) VCC = 5.0V VREF = 2.0V +3/4 0 Zero–Scale Offset Error vs vREF +1 Z–F OFFSET ERROR (LSB’s) Z–F OFFSET ERROR (LSB’s) +1 75 75 Philips Semiconductors Linear Products Product specification 6-Bit A/D converter (parallel outputs) NE5037 AC TEST CIRCUITS AND WAVEFORMS VCC = 5V VREF = 2V VIN = 2.1V 1R = tF = 20ns tp (DATA) DATA OUTPUT OE NE5037 10kΩ 15pF 1MHz CLK (TTL) START PULSE (TTL LEVEL) 90% 50% 10% EO (TTL LEVEL) 90% 50% 10% tF tR 10% 50% DB (0 TO 5) tp (3–STATE) tp (DATA) Propagation Delay Time tP (DATA) and TP (3-state) 1R = tF = 20ns VCC = +5V VCC OE VCC = 5V VREF = 2V VIN = 0.1V 90% 50% 10% 50% 10K GND DATA OUTPUT NE5037 tF 15pF 1MHz CLK (TTL) tR VCC VCC START PULSE (TTL LEVEL) EO (TTL LEVEL) DB (0 TO 5) 50% GND tp (DATA) 10% tp (3–STATE) Data Output High 90% VCC VCC = +5V VREF = +2V CLK 1 NE5037 1MHz TTL (CLOCK) START PULSE (TTL LEVEL) 10% 10kΩ 90% 50% 10% 2 tR 9 tF EOC START EO = VCC tW EOC 50% tp (EOC) Propagation Delay Time EOC tP(EOC) August 31, 1994 587 Philips Semiconductors Linear Products Product specification 6-Bit A/D converter (parallel outputs) NE5037 +5V LM334 330 0.1µF 0.1µF 220 1 0.1µF 2 160 7 STRT 8 CS 1000pF RANGE 100 1K BIAS ADJ. 1K 3 5.76K (F) 3.2 K (C) 1/2 NE5512 8 2 – 3 820 10K 6 1/2 NE5512 – CONTROLLER 10 EOC 5 7 + 11–16 5 + 4 0.1µF TP1* 4 9 OE NE5037 A/D 6–BIT DATA BUS 6 910 –3V TP2 TP3 DISPLAY READING VOLTAGE TP1 oF 1.5895 oC 0.8742 CLK a. Temperature Sensor 0.22µF +5V 20 LM334 19 330 0.1µF 0.1µF 220 1 0.1µF 16 14 2 160 1000pF RANGE 100 1K BIAS ADJ. 1K 3 5.76K (F) 3.2 K (C) 8 2 – 3 10K 1/2 NE5512 6 – 4 1/2 NE5512 NE5037 A/D 5 + 5 + 4 6 7 9 14 17 13 N82S147 PROM (DECODER/ DRIVER) 2 5 14 4 5 4 12 3 8 12 6 7 2 7 11 11 10 1 6 10 N74LS174 6–BIT LATCH 9 8 OPEN 12 15 16 15 3 13 13 7 18 10 11 9 DIS 1 10’s 15 Q1 2N3906 820 0.1µF 910 CLK DIS 2 10’s TP1* –3V TP2 TP3 CLK DISPLAY READING U7 PIN 18 VOLTAGE TP1 oF GND 1.5895 oC HIGH 0.8742 Q2 2N3986 b. Digital Thermometer Figure 3. August 31, 1994 588 Philips Semiconductors Linear Products Product specification 6-Bit A/D converter (parallel outputs) NE5037 connected to the latch enable of a 6-bit latch because the data at the converter output is available for only a short time when the converter is in the continuous conversion mode. The (P)ROM) must have the correct code for converting the data from the NE5037 (used as address for the (P)ROMs) to the appropriate segment drive codes. Note that the circuit of Figure 3b shows a circuit which can be used to display either Fahrenheit or Centigrade temperatures. APPLICATION • 0 to 63°C Temperature Sensor CIRCUIT DESCRIPTION The temperature sensor of Figure 3 provides an input to Pin 3 of the NE5037 of 32mV/°C. This 32mV is the value of one LSB for the NE5037. The LM334 is a three-terminal temperature sensor and provides a current of 1µA for each °Kelvin. The first section of the dual op amp is connected as a trans-impedance amplifier to convert the current from the LM334 to a voltage, which is amplified and inverted by the section amplifier. Note that the first amplifier requires different values of feedback resistance for °C and °F. The NE5512 was chosen for its low temperature coefficient of input bias current as excessive IOS tempco would degrade temperature tracking. The displayed output could easily be converted to degrees Fahrenheit (°F) by the controller of Figure 3a or through the (P)ROMs of Figure 3b. When doing this, a third (hundreds) digit (P)ROM and display will be needed for displaying temperatures above 99°F. An inexpensive clock can be made from NAND gates or inverters, as shown in Figure 3c. To read temperature, conversion is started by sending a momentary low signal to Pin 7 of the NE5037. When Pin 10 of the NE5037 goes low, conversion is complete and a low is applied to Pin 9 of the NE5037 to read data on Pins 11 through 16. Note that this temperature data is in straight binary format. CIRCUIT ADJUSTMENT The circuit should be at a known ambient temperature for a few minutes before making adjustments. 14.Adjust bias adjust potentiometer for the voltage indicated in the chart in Figure 3b. The controller can be a microprocessor in a temperature control application, or discrete circuitry in a simple temperature reporting application. A temperature reporting (digital thermometer) circuit is shown in Figure 3b. The NE5037 A/D converter is connected in a continuous conversion mode by connecting together Pins 7, 9, and 10. Should this pin be momentarily shorted to any relatively low impedance point, conversion will stop. Conversion will resume upon interruption and restoration of the power. These pins are also August 31, 1994 15.With the circuit (or sensor U3, if it is remotely located) at a known temperature for 2 to 3 minutes, adjust range control for a correct reading on the displays. This should provide an accuracy of ±3 counts (3° F or C). Higher accuracy may require NE5037 reference voltage regulation. 589