PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) 2.0 Features • 1 to 64 bits • Time Division Multiplexing mode • Requires clock and data for serial bit stream input • Serial data in, parallel result • Standard [CRC-1 (parity bit), CRC-4 (ITU-T G.704), CRC-5-USB, etc.] or custom polynomial • Standard or custom seed value • Enable input provides synchronized operation with other components General Description The default use of the Cyclic Redundancy Check (CRC) component is to compute CRC from a serial bit stream of any length. The input data is sampled on the rising edge of the data clock. The CRC value is reset to 0 before starting or can optionally be seeded with an initial value. On completion of the bitstream, the computed CRC value may be read out. When to use a CRC The default CRC component can be used as a checksum to detect alteration of data during transmission or storage. CRCs are popular because they are simple to implement in binary hardware, are easy to analyze mathematically, and are particularly good at detecting common errors caused by noise in transmission channels. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-62889 Rev. *A Revised November 30, 2010 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet Input/Output Connections This section describes the various input and output connections for the CRC. An asterisk (*) in the list of I/Os indicates that the I/O may be hidden on the symbol under the conditions listed in the description of that I/O. clock – Input The CRC requires a data input that provides the serial bitstream used to calculate the CRC. A data clock input is also required in order to correctly sample the serial data input. The input data is sampled on the rising edge of the data clock. reset – Input The reset input defines the signal to asynchronous reset CRC. enable – Input The CRC component runs after started and as long as the Enable input is held high. This input provides synchronized operation with other components. di – Input Data input that provides the serial bitstream used to calculate the CRC. Page 2 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) Parameters and Settings Drag a CRC component onto your design and double-click it to open the Configure dialog. This dialog has several tabs to guide you through the process of setting up the CRC component. Polynomial Tab Standard Polynomial Allows you to choose one of the standard CRC polynomials provided in the Standard polynomial combo box or generate a custom polynomial. The additional information about each standard polynomial is given in the tool tip. The default is CRC-16. Polynomial Name Polynomial Use Custom User defined General CRC-1 x+1 Parity CRC-4-ITU x +x+1 CRC-5-ITU x + x + x +1 CRC-5-USB x +x +1 CRC-6-ITU x +x+1 CRC-7 x +x +1 CRC-8-ATM x +x +x+1 CRC-8-CCITT x +x +x +x +1 4 5 4 5 2 ITU G.704 2 ITU G.704 USB 6 ITU G.704 7 3 telecom systems, MMC 8 2 ATM HEC 8 7 3 Document Number: 001-62889 Rev. *A 2 1-Wire bus Page 3 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet Polynomial Name CRC-8-Maxim Polynomial 8 5 4 8 7 6 4 8 4 3 2 Use x +x +x +1 1-Wire bus 2 CRC-8 x +x +x +x +x +1 CRC-8-SAE x +x +x +x +1 CRC-10 x 10 +x +x +x +x+1 CRC-12 x 12 +x 11 +x +x +x+1 CRC-15-CAN x 15 +x 14 +x CRC-16-CCITT x 16 +x 12 +x +1 CRC-16 x 16 +x 15 +x +1 CRC-24-Radix64 x +x x+1 24 23 +x 18 +x 17 +x 14 +x 11 +x 10 + x + x + x + x + x + General CRC-32-IEEE802.3 x +x +x 2 +x +x+1 32 26 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x +x +x +x CRC-32C x +x +x +x +x +x +x 13 11 10 9 8 6 x +x +x +x +x +x +1 32 28 27 26 25 23 22 +x 20 +x 19 +x 18 +x 14 + General CRC-32K x +x +x +x +x +x +x 10 7 6 4 2 x +x +x +x +x +x+1 32 30 29 28 26 20 19 +x 17 +x 16 +x 15 +x 11 + General CRC-64-ISO x CRC-64-ECMA x +x +x +x +x +x +x +x +x +x +x + 39 38 37 35 33 32 31 29 27 24 23 x +x +x +x +x +x +x +x +x +x +x + 22 21 19 17 13 12 10 9 7 4 x + x + x + x + x + x + x + x + x + x + x +1 64 64 9 4 5 3 10 General SAE J1850 4 General 2 8 7 telecom systems 4 3 +x +x +x +x +1 CAN 5 XMODEM,X.25, V.41, Bluetooth, PPP, IrDA, CRCCCITT 2 USB 7 6 8 5 4 7 3 5 4 3 +x +x +x+1 62 57 55 Ethernet, MPEG2 ISO 3309 54 53 52 47 46 45 40 ECMA-182 Polynomial Value Represented in the hexadecimal form. It is calculated automatically when one of the standard polynomials is selected. You may also enter it manually (see Custom Polynomials). Seed Value Represented in the hexadecimal form. The maximum possible value is 2N-1. N Defines the degree of polynomial. Possible values include 1- 64 bits. The table with numbers indicates which degrees will be included in the polynomial. Cells with selected numbers are blue; others are white. The number of active cells is equal to N. Numbers are arranged in the reverse order. You may click on the cell to select or deselect a number. Page 4 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) Polynomial Representation Displays the resulting polynomial with the mathematical notation. Custom Polynomials You may enter a custom polynomial in three different ways: Small Changes to Standard Polynomial • Choose one of the standard polynomials. • Select the necessary degrees in the table by clicking on the appropriate cells; the text in Standard Polynomial will change to "Custom." • The polynomial value will be recalculated automatically based on the polynomial representation. Use Polynomial Degrees • Enter a custom polynomial in the N textbox; the text in Standard Polynomial will change to "Custom." • Select the necessary degrees in the table with numbers. • Check the view of the polynomial with the Polynomial Representation. • The polynomial value will be recalculated automatically based on the polynomial representation. Use Hexadecimal Format • Enter a polynomial value in the hexadecimal form in the Polynomial Value text box. • Press [Enter] or switch to another control; the text in Standard Polynomial will change to "Custom." • The N value and degrees of polynomial will be recalculated based on the entered polynomial value. Document Number: 001-62889 Rev. *A Page 5 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet Advanced Tab Implementation This defines implementation of the CRC component: Time Division Multiplex or Single Cycle. The default is Single Cycle. Local Parameters (For API usage) These parameters are used in the API and are not exposed in the GUI: • PolyValueLower (uint32) – Contains the lower half of the polynomial value in hexadecimal. The default is 0xB8h (LFSR= [8,6,5,4]) because the default Resolution is 8. • PolyValueUpper (uint32) – Contains the upper half of the polynomial value in hexadecimal. The default is 0x00h because the default Resolution is 8. • SeedValueLower (uint32) – Contains the lower half of the seed value in hexadecimal. The default is 0xFFh because the default Resolution is 8. • SeedValueUpper (uint32) – Contains the upper half of the seed value in hexadecimal. The default is 0 because the default Resolution is 8. Clock Selection There is no internal clock in this component. You must attach a clock source. Note Generation of the proper CRC sequence for a Resolution of greater than 8 requires a clock signal of 4 times greater than the data rate, if you select Time Division Multiplex for the Implementation parameter. Page 6 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) Placement The CRC is placed throughout the UDB array and all placement information is provided to the API through the cyfitter.h file. Resources Single Cycle Implementation API Memory (Bytes) Resource Type Resources Pins (per External I/O) Datapath Cells PLDs Control/Count7 Cells Flash RAM 1..8-Bits Resolution 1 1 1 256 6 4 9..16-Bits Resolution 2 1 1 317 9 4 17..24-Bits Resolution 3 1 1 436 15 4 25..32-Bits Resolution 4 1 1 447 15 4 Time Division Multiplex Implementation API Memory (Bytes) Resource Type Resources Pins (per External I/O) Datapath Cells PLDs Control/Count7 Cells Flash RAM 9..16-Bits Resolution 1 3 1 483 13 4 17..24-Bits Resolution 2 3 1 873 23 4 25..32-Bits Resolution 2 3 1 1097 23 4 33..40-Bits Resolution 3 3 1 1345 43 4 41..48-Bits Resolution 3 3 1 1509 43 4 49..56-Bits Resolution 4 3 1 1742 43 4 57..64-Bits Resolution 4 3 1 1956 43 4 Document Number: 001-62889 Rev. *A Page 7 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet Application Programming Interface Application Programming Interface (API) routines allow you to configure the component using software. The following table lists and describes the interface to each function. The subsequent sections cover each function in more detail. By default, PSoC Creator assigns the instance name "CRC_1" to the first instance of a component in a given design. You can rename it to any unique value that follows the syntactic rules for identifiers. The instance name becomes the prefix of every global function name, variable, and constant symbol. For readability, the instance name used in the following table is "CRC". Function Description void CRC_Start(void) Initializes seed and polynomial registers with initial values. Computation of CRC starts on rising edge of input clock. void CRC_Stop(void) Stops CRC computation. void CRC_Wakeup(void) Restores CRC configuration and starts CRC computation on rising edge of input clock. void CRC_Sleep(void) Stops CRC computation and saves CRC configuration. void CRC_Init(void) Initializes seed and polynomial registers with initial values. void CRC_Enable(void) Starts CRC computation on rising edge of input clock. void CRC_SaveConfig(void) Saves seed and polynomial registers. void CRC_RestoreConfig(void) Restores seed and polynomial registers. void CRC_WriteSeed(uint8/16/32 seed) Writes seed value. void CRC_riteSeedUpper(uint32 seed) Writes upper half of seed value. Only generated for 33–64 bits CRC. void CRC_WriteSeedLower(uint32 seed) Writes lower half of seed value. Only generated for 33–64 bits CRC. uint8/16/32 CRC_ReadCRC(void) Reads CRC value. uint32 CRC_ReadCRCUpper(void) Reads upper half of CRC value. Only generated for 33–64 bits CRC. uint32 CRC_ReadCRCLower(void) Reads lower half of CRC value. Only generated for 33–64 bits CRC. void CRC_WritePolynomial(uint8/16/32 polynomial) Writes CRC polynomial value. void RC_WritePolynomialUpper(uint32 polynomial) Writes upper half of CRC polynomial value. Only generated for 33–64 bits CRC. void CRC_WritePolynomialLower(uint32 polynomial) Writes lower half of CRC polynomial value. Only generated for 33–64 bits CRC. uint8/16/32 CRC_ReadPolynomial(void) Reads CRC polynomial value. Page 8 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) Function Description uint32 CRC_ReadPolynomialUpper(void) Reads upper half of CRC polynomial value. Only generated for 33–64 bits CRC. uint32 CRC_ReadPolynomialLower(void) Reads lower half of CRC polynomial value. Only generated for 33–64 bits CRC. Global Variables Variable CRC_initVar Description Indicates whether the CRC has been initialized. The variable is initialized to 0 and set to 1 the first time CRC_Start() is called. This allows the component to restart without reinitialization after the first call to the CRC_Start() routine. If reinitialization of the component is required, then the CRC_Init() function can be called before the CRC_Start() or CRC_Enable() function. void CRC_Start(void) Description: Initializes seed and polynomial registers with initial values. Computation of CRC starts on rising edge of input clock. Parameters: None Return Value: None Side Effects: None void CRC_Stop(void) Description: Stops CRC computation. Parameters: None Return Value: None Side Effects: None void CRC_Sleep(void) Description: Stops CRC computation and saves CRC configuration. Parameters: None Return Value: None Side Effects: None Document Number: 001-62889 Rev. *A Page 9 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet void CRC_Wakeup(void) Description: Restores CRC configuration and starts CRC computation on rising edge of input clock. Parameters: None Return Value: None Side Effects: None void CRC_Init(void) Description: Initializes seed and polynomial registers with initial values. Parameters: None Return Value: None Side Effects: None void CRC_Enable(void) Description: Starts CRC computation on rising edge of input clock. Parameters: None Return Value: None Side Effects: None void CRC_SaveConfig(void) Description: Saves initial seed and polynomial registers. Parameters: None Return Value: None Side Effects: None void CRC_RestoreConfig(void) Description: Restores initial seed and polynomial registers. Parameters: None Return Value: None Side Effects: None Page 10 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) void CRC_WriteSeed(uint8/16/32 seed) Description: Writes seed value. Parameters: seed: uint8/16/32 – Seed value. Return Value: None Side Effects: The seed value is cut according to mask = 2 – 1. 14 For example if CRC Resolution is 14 bits the mask value is: mask = 2 – 1 = 0x3FFFu. The seed value = 0xFFFFu is cut: seed & mask = 0xFFFFu & 0x3FFFu = 0x3FFFu. Resolution void CRC_WriteSeedUpper(uint32 seed) Description: Writes upper half of seed value. Only generated for 33–64 bits CRC. Parameters: seed: uint32 – Upper half of seed value. Return Value: None Side Effects: The upper half of seed value is cut according to mask = 2 – 1. For example if CRC Resolution is 35 bits the mask value is: (35 – 32) ^3 – 1 = 2 – 1 = 0x0000 0007u. 2 The upper half of seed value = 0x0000 00FFu is cut: upper half of seed & mask = 0x0000 00FFu & 0x0000 0007u = 0x0000 0007u. Resolution – 32 void CRC_WriteSeedLower(uint32 seed) Description: Writes lower half of seed value. Only generated for 33–64 bits CRC. Parameters: seed: uint32 – Lower half of seed value. Return Value: None Side Effects: None uint8/16/32 CRC_ReadCRC(void) Description: Reads CRC value. Parameters: None Return Value: uint8/16/32: Returns CRC value. Side Effects: None uint32 CRC_ReadCRCUpper(void) Description: Reads upper half of CRC value. Only generated for 33–64 bits CRC. Parameters: None Return Value: uint32: Returns upper half of CRC value. Side Effects: None Document Number: 001-62889 Rev. *A Page 11 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet uint32 CRC_ReadCRCLower(void) Description: Reads lower half of CRC value. Only generated for 33–64 bits CRC. Parameters: None Return Value: uint32: Returns lower half of CRC value. Side Effects: None void CRC_WritePolynomial(uint8/16/32 polynomial) Description: Writes CRC polynomial value. Parameters: polynomial: uint8/16/32 – CRC polynomial. Return Value: None Side Effects: The polynomial value is cut according to mask = 2 – 1. For example if CRC 14 Resolution is 14 bits the mask value is: mask = 2 – 1 = 0x3FFFu. The polynomial value = 0xFFFFu is cut: polynomial & mask = 0xFFFFu & 0x3FFFu = 0x3FFFu. Resolution void RC_WritePolynomialUpper(uint32 polynomial) Description: Writes upper half of CRC polynomial value. Only generated for 33–64 bits CRC. Parameters: polynomial: uint32 – Upper half CRC polynomial value. Return Value: None Side Effects: The upper half polynomial value is cut according to mask = 2 – 1. For example if CRC Resolution is 35 bits the mask value is: (35 – 32) 3 – 1 = 2 – 1 = 0x0000 0007u. 2 The upper half of polynomial value = 0x0000 00FFu is cut: upper half of polynomial & mask = 0x0000 00FFu & 0x0000 0007u = 0x0000 0007u. (Resolution – 32) void CRC_WritePolynomialLower(uint32 polynomial) Description: Writes lower half of CRC polynomial value. Only generated for 33–64 bits CRC. Parameters: polynomial: uint32 – Lower half of CRC polynomial value. Return Value: None Side Effects: None uint8/16/32 CRC_ReadPolynomial(void) Description: Reads CRC polynomial value. Parameters: None Return Value: uint8/16/32: Returns CRC polynomial value. Side Effects: None Page 12 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) uint32 CRC_ReadPolynomialUpper(void) Description: Reads upper half of CRC polynomial value. Only generated for 33–64 bits CRC. Parameters: None Return Value: uint32: Returns upper half of CRC polynomial value. Side Effects: None uint32 CRC_ReadPolynomialLower(void) Description: Reads lower half of CRC polynomial value. Only generated for 33–64 bits CRC. Parameters: None Return Value: uint32: Returns lower half of CRC polynomial value. Side Effects: None Sample Firmware Source Code PSoC Creator provides numerous example projects that include schematics and example code in the Find Example Project dialog. For component-specific examples, open the dialog from the Component Catalog or an instance of the component in a schematic. For general examples, open the dialog from the Start Page or File menu. As needed, use the Filter Options in the dialog to narrow the list of projects available to select. Refer to the "Find Example Project" topic in the PSoC Creator Help for more information. Functional Description The CRC is implemented as a linear feedback shift register (LFSR). The Shift register computes the LFSR function; the Polynomial register holds the polynomial that defines the LFSR polynomial; and the Seed register enables initialization of the starting data. This component requires that the Seed and Polynomial registers are initialized prior to start. Computation of an N–bit LFSR result is specified by a polynomial with N+1 terms, the last of which is the X0 term where X0=1. For example, the widely used CRC–CCITT 16–bits polynomial is X16+X12+X5+1. The CRC algorithm assumes the presence of the X0 term, so that the polynomial for an N–bit result can be expressed by an N bit rather than N+1–bit specification. To specify the polynomial specification, write an N+1 bit binary number corresponding to the full polynomial, with 1's for each term present. The CRC–CCITT polynomial would be 10001000000100001b. Then, drop the right–most bit (the X0 term) to obtain the CRC polynomial value. To implement the CRC–CCITT example, the Polynomial register is loaded with the value of 8810h. Document Number: 001-62889 Rev. *A Page 13 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet A rising edge of the input clock shifts each bit, MSB first, of the input data stream through the Shift register, computing the specified CRC algorithm. Eight clocks are required to compute the CRC for each byte of input data. Note that the initial seed value is lost. This is usually of no consequence since the seed value is only used to initialize the Shift register once, per data set. Block Diagram and Configuration Add information here about the data paths used and how the registers are used inside of those data paths. Also include if writing a register causes something to happen etc. Timing Diagrams Figure 1. Time Division Multiplex Implementation Mode Page 14 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) Figure 2. Single Cycle Implementation Mode DC and AC Electrical Characteristics The following values indicate expected performance and are based on initial characterization data. Document Number: 001-62889 Rev. *A Page 15 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet Timing Characteristics “Maximum with Nominal Routing” Parameter fclock tclockH 1 Description Config. Component Clock Frequency Input Clock High Time 3 3 tclockL Input Clock Low Time tPD Input path delay, pin to sync 4 Input path delay, pin to sync 6 tPD ps ps tPD_si 1 2 Sync output to Input Path Delay (route) Min Typ Max Units Config 1 45 MHz Config 2 30 MHz Config 3 41 MHz Config 4 24 MHz Config 5 35 MHz Config 6 21 MHz N/A 0.5 1/fclock N/A Inputs 1 0.5 1/fclock 2 1,2,3,4 STA 5 8.5 STA ns ns 5 ns Configurations: Config 1: Resolution: 8 bits Implementation: Single Cycle Config 2: Resolution: 16 bits Implementation: Single Cycle Config 3: Resolution: 16 bits Implementation: Time Division Multiplex Config 4: Resolution: 32 bits Implementation: Single Cycle Config 5: Resolution: 32 bits Implementation: Time Division Multiplex Config 6: Resolution: 64 bits Implementation: Time Division Multiplex 2 If Time Division Multiplex Implementation is selected, then Component Clock Frequency must be 4 times greater than the data rate. 3 tCY_clock = 1/fclock - Cycle time of one clock period. 4 tPD_ps will be found in the Static Timing Results as described later. The number listed here is a nominal value based on STA analysis on many input. 5 tPD_ps and tPD_si are route path delays. Because routing is dynamic, these values can change and will directly affect the maximum component clock and sync clock frequencies. The values must be found in the Static Timing Analysis results. 6 tPD_ps in configuration 2 is a fixed value defined per pin of the device. The number listed here is a nominal value of all of the pins available on the device Page 16 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Parameter tI Cyclic Redundancy Check (CRC) 1 Description Config. Alignment of clockX and clock 1,2,3,4 tPD_IE Input Path Delay to Component Clock (Edge Sensitive Input) tPD_IE tIH clk tIL 7 Min Typ Max Units 0 1 1,2 tPD_ps + tsync + tPD_si tPD_ps + tsync + tPD_si + tI clk ns Input Path Delay to Component Clock (Edge Sensitive Input) 3,4 tsync + tPD_si tsync + tPD_si + tI clk ns Input High Time 1,2,3,4 Input Low Time tCY 1,2,3,4 tCY clock clock tCY clock 7 ns 7 ns tCY_clock = 4* [1/fclock] if Time Division Multiplex Implementation is selected. Timing Characteristics “Maximum with All Routing” Parameter fclock 1 Description Component Clock Frequency Config. 3 1 Min Typ Max 2 Units Config 1 23 MHz Config 2 15 MHz Config 3 21 MHz Config 4 12 MHz Configurations: Config 1: Resolution: 8 bits Implementation: Single Cycle Config 2: Resolution: 16 bits Implementation: Single Cycle Config 3: Resolution: 16 bits Implementation: Time Division Multiplex Config 4: Resolution: 32 bits Implementation: Single Cycle Config 5: Resolution: 32 bits Implementation: Time Division Multiplex Config 6: Resolution: 64 bits Implementation: Time Division Multiplex 2 Maximum for “All Routing” is calculated by <nominal>/2 rounded to the nearest integer. This value provides a basis for the user to not have to worry about meeting timing if they are running at or below this component frequency. 3 If Time Division Multiplex Implementation is selected, then Component Clock Frequency must be 4 times greater than the data rate. Document Number: 001-62889 Rev. *A Page 17 of 29 Cyclic Redundancy Check (CRC) Parameter tclockH PSoC® Creator™ Component Data Sheet Description Input Clock High Time Config. 4 4 tclockL Input Clock Low Time tPD Input path delay, pin to sync 5 Input path delay, pin to sync 7 tPD ps ps Max 2 Units MHz Config 6 11 MHz N/A 0.5 1/fclock N/A Inputs 1 0.5 1/fclock STA 2 1,2,3,4 tI Alignment of clockX and clock 1,2,3,4 tPD_IE Input Path Delay to Component Clock (Edge Sensitive Input) tPD_IE tIH 4 Typ 18 Sync output to Input Path Delay (route) tIL Min Config 5 tPD_si clk 1 6 ns 8.5 STA ns 5 ns 0 1 1,2 tPD_ps + tsync + tPD_si tPD_ps + tsync + tPD_si + tI clk ns Input Path Delay to Component Clock (Edge Sensitive Input) 3,4 tsync + tPD_si tsync + tPD_si + tI clk ns Input High Time 1,2,3,4 Input Low Time 1,2,3,4 tCY tCY clock clock tCY clock 8 ns 8 ns tCY_clock = 1/fclock - Cycle time of one clock period. 5 tPD_ps will be found in the Static Timing Results as described later. The number listed here is a nominal value based on STA analysis on many input. 6 tPD_ps and tPD_si are route path delays. Because routing is dynamic, these values can change and will directly affect the maximum component clock and sync clock frequencies. The values must be found in the Static Timing Analysis results. 7 tPD_ps in configuration 2 is a fixed value defined per pin of the device. The number listed here is a nominal value of all of the pins available on the device 8 tCY_clock = 4* [1/fclock] if Time Division Multiplex Implementation is selected. How to Use STA Results for Characteristics Data Nominal route maximums are gathered through multiple test passes with Static Timing Analysis (STA). You can calculate the maximums for your designs using the STA results using the following methods: fclock Maximum Component Clock Frequency appears in Timing results in the clock summary as the named external clock. The graphic below shows an example of the clock limitations from the _timing.html: Page 18 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) Input Path Delay and Pulse Width When characterizing the functionality of inputs, all inputs, no matter how you have configured them, look like one of four possible configurations, as shown in Figure 3. All inputs must be synchronized. The synchronization mechanism depends on the source of the input to the component. To fully interpret how your system will work you must understand which input configuration you have set up for each input and the clock configuration of your system. This section describes how to use the Static Timing Analysis (STA) results to determine the characteristics of your system. Document Number: 001-62889 Rev. *A Page 19 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet Figure 3. Input Configurations for Component Timing Specifications Configuration 1 Component Clock Synchronizer Clock (Frequency) Figures 1 master_clock master_clock Figure 8 1 clock master_clock Figure 6 1 clock clockX = clock 1 clock clockX > clock Figure 5 1 clock clockX < clock Figure 7 2 master_clock master_clock Figure 8 2 clock master_clock Figure 6 3 master_clock master_clock Figure 13 1 Figure 4 Clock frequencies are equal but alignment of rising edges is not guaranteed. Page 20 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Configuration 3 Component Clock clock Cyclic Redundancy Check (CRC) Synchronizer Clock (Frequency) master_clock Figures Figure 11 1 3 clock clockX = clock Figure 9 3 clock clockX > clock Figure 10 3 clock clockX < clock Figure 12 4 master_clock master_clock Figure 13 4 clock clock Figure 9 1. The input is driven by a device pin and synchronized internally with a “sync” component. This component is clocked using a different internal clock than the clock the component uses (all internal clocks are derived from master_clock). When characterizing inputs configured in this way, clockX may be faster, equal to, or slower than the component clock. It may also be equal to master_clock, which produces the characterization parameters shown in Figure 4, Figure 5, Figure 7, and Figure 8. 2. The input is driven by a device pin and synchronized at the pin using master_clock. When characterizing inputs configured in this way, master_clock is faster than or equal to the component clock (it is never slower than). This produces the characterization parameters shown in Figure 5 and Figure 8. Figure 4. Input Configuration 1 and 2; Sync Clock Freq.= Component Clock Freq. (Edge alignment of clock and clockX is not guaranteed) Document Number: 001-62889 Rev. *A Page 21 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet Figure 5. Input Configuration 1 and 2; Sync. Clock Freq. > Component Clock Freq. Figure 6. Input Configuration 1 and 2; [Sync. Clock Freq. == master_clock] > Component Clock Freq. Page 22 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) Figure 7. Input Configuration 1; Sync. Clock Freq. < Component Clock Freq. master_clock clockX tsync clock tPD_ps Input @ pin tPD_si Input @ sync output Input @ component tPD_IE tIH tIL Figure 8. Input Configuration 1 and 2; Sync. Clock = Component Clock = master_clock 3. The input is driven by logic internal to the PSoC, which is synchronous based on a clock other than the clock the component uses (all internal clocks are derived from master_clock). When characterizing inputs configured in this way, the synchronizer clock is faster than, less than, or equal to the component clock, which produces the characterization parameters shown in Figure 9, Figure 10, and Figure 12 4. The input is driven by logic internal to the PSoC, which is synchronous based on the same clock the component uses. Document Number: 001-62889 Rev. *A Page 23 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet When characterizing inputs configured in this way, the synchronizer clock will be equal to the component clock, which will produce the characterization parameters as shown in Figure 13. Figure 9. Input Configuration 3 only; Sync. Clock Freq. = Component Clock Freq. (Edge alignment of clock and clockX is not guaranteed) This figure represents the understanding that Static Timing Analysis holds on the clocks. All clocks in the digital clock domain are synchronous to master_clock. However, it is possible that two clocks with the same frequency are not rising-edge-aligned. Therefore, the static timing analysis tool does not know which edge the clocks are synchronous to and must assume the minimum of 1 master_clock cycle. This means that tPD_si now has a limiting effect on master_clock of the system. Master_clock setup time violations appear if this path delay is too long. You must change the synchronization clocks of your system or run master_clock at a slower frequency. Page 24 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) Figure 10. Input Configuration 3; Sync. Clock Freq. > Component Clock Freq. In much the same way as shown in Figure 9, all clocks are derived from master_clock. STA indicates the tPD_si limitations on master_clock for one master_clock cycle in this configuration. Master_clock setup time violations appear if this path delay is too long. You must change the synchronization clocks of your system or run the master_clock at a slower frequency. Figure 11. Input Configuration 3; Synchronizer Clock Frequency = master_clock > Component Clock Frequency Document Number: 001-62889 Rev. *A Page 25 of 29 Cyclic Redundancy Check (CRC) PSoC® Creator™ Component Data Sheet Figure 12. Input Configuration 3; Synchronizer Clock Frequency < Component Clock Frequency In much the same way as shown in Figure 9, all clocks are derived from master_clock. STA indicates the tPD_si limitations on master_clock for one master_clock cycle in this configuration. master_clock setup time violations appear if this path delay is too long. You must change the synchronization clocks of your system or run master_clock at a slower frequency. Figure 13. Input Configuration 4 only; Synchronizer Clock = Component Clock In all previous figures in this section, the most critical parameters to use when understanding your implementation are fclock and tPD_IE. tPD_IE is defined by tPD_ps and tsync (for configurations 1 and 2 only), tPD_si, and tI_Clk. Of critical importance is the fact that tPD_si defines the maximum component clock frequency. tI_Clk does not come from the STA results but is used to represent when tPD_IE is registered. This is the margin left over after the route between the synchronizer and the component clock. tPD_ps and tPD_si are included in the STA results. To find tPD_ps, look at the input setup times defined in the _timing.html file. The fan-out of this input may be more than 1 so you will need to evaluate the maximum of these paths. Page 26 of 29 Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) tPD_si will be defined in the Register-to-register times. You will need to know the name of the net to use the _timing.html file. The fan-out of this path may be more than 1 so you will need to evaluate the maximum of these paths. Output Path Delays When characterizing the path delays of outputs, you must consider where the output is going in order to know where you can find the data in the STA results. For this component, all outputs are synchronized to the component clock. Outputs fall into one of two categories. The output goes either to another component inside the device, or to a pin to the outside of the device. In the first case, you must look at the Register-to-register times shown for the Logic-to-input descriptions above (the source clock is the component clock). For the second case, you can look at the Clock-to-Output times in the _timing.html STA results. Component Changes This section lists the major changes in the component from the previous version. Version 2.0.a Description of Changes Reason for Changes / Impact Added characterization data to datasheet Minor datasheet edits and updates Document Number: 001-62889 Rev. *A Page 27 of 29 Cyclic Redundancy Check (CRC) Version 2.0 1.20 Description of Changes PSoC® Creator™ Component Data Sheet Reason for Changes / Impact Added support for PSoC 3 ES3 silicon. Changes include: • 4x clock for Time Division Multiplex Implementation added • Single Cycle Implementation on 1x clock now available for 1-32 bits. • Time Division Multiplex Implementation on 4x clock now available for 9-64 bits. • Asynchronous input signal Reset is added. • Synchronous input signal Enable is added. • Added new 'Advanced' page to the Configure dialog for the Implementation (Time Division Multiplex, Single Cycle) parameter New requirements to support the PSoC 3 ES3 device, thus a new 2.0 version of the CRC component was created. Added CRC_Sleep()/CRC_Wakeup() and CRC_Init()/CRC_Enable() APIs. To support low power modes, as well as to provide common interfaces to separate control of initialization and enabling of most components. Updated functions CRC_WriteSeed() and CRC_WriteSeedUpper(). The mask parameter was used to cut the seed value to define CRC resolution while writing. Add validator to Resolution parameter. The resolution of CRC is 1-64 bits. The validator was added to restrict input values. Add reset DFF triggers to polynomial write functions: CRC_WritePolynomial(), CRC_WritePolynomialUpper() and CRC_WritePolynomialLower(). The DFF triggers need to be set in proper state (most significant bit of polynomial, always 1) before starts CRC calculation. To meet this condition any write to Seed or Polynomial register resets the DFF triggers. Updated Configure dialog to allow the Expression View for the following parameters: 'PolyValueLower', 'PolyValueUpper', 'SeedValueLower', 'SeedValueLower' Expression View is used to directly access the symbol parameters. This view allows you to connect component parameters with external parameters, if desired. Updated Configure dialog to add error icons for various parameters. If you enter an incorrect value in a text box, the error icon displays with a tool tip of the problem description. This provides easier use than a separate error message. Changed method of API generation. In version 1.10, This change allows users to view and make changes to the generated API files, and they will APIs were generated by settings from the not be overwritten on subsequent builds. customizer. For 1.20, APIs are provided by the .c and .h files like most other components. Seed and Polynomial parameters were changed to have hexadecimal representation. Page 28 of 29 Change was made to comply with corporate standard. Document Number: 001-62889 Rev. *A PSoC® Creator™ Component Data Sheet Cyclic Redundancy Check (CRC) © Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC® is a registered trademark, and PSoC® Creator™ and Programmable System-on-Chip™ are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A HALFICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-62889 Rev. *A Page 29 of 29