Product Specification PE3291 Product Description The PE3291 is a dual fractional-N FlexiPowerTM phase-lock loop (PLL) IC designed for frequency synthesis. Each PLL includes a FlexiPowerTM prescaler, phase detector, charge pump and onboard fractional spur compensation. The FlexiPower prescalers are supplied power on dedicated pins and can operate at a substantial power savings at voltages as low as 0.8 volts, while allowing a 3 volt charge pump supply. For 3 volt only systems, on-chip voltage regulation may be used to generate the prescaler power supplies. 1200 MHz / 550 MHz Dual Fractional-N FlexiPower™ PLL for Frequency Synthesis Features • Ultra-Low Power via FlexiPower variable supply voltages • Modulo-32 fractional-N main counters • On-board fractional spur compensation: No tuning required, stable over temperature • Improved phase noise compared to integer-N architectures Figure 1 illustrates the implementation of the FlexiPower technology. The prescaler power supply may be provided externally or internally regulated down from VDD. In a typical 950 MHz application the total current consumed by the PLL is 2.1 mA. Operation at reduced current levels provides significant battery life extension. The PE3291 allows the system designer to minimize power consumption by controlling the voltage on the prescaler. For additional operating speeds and current consumptions refer to Figures 5 and 6. PE3291 provides fractional-N division with power-of-two denominator values up to 32. This allows comparison frequencies up to 32 times the channel spacing, providing a lower phase noise floor than integer PLLs. The 32/33 RF prescaler (PLL1) operates up to 1200 MHz and the 16/17 IF prescaler (PLL2) operates up to 550 MHz. The PE3291 Phase Locked-Loop is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Document No. 70-0009-04 │ www.psemi.com Applications • CDMA handsets • CDMA base stations • Analog Cordless phones • One and two way pagers Figure 1: FlexiPower technology enables the prescaler to operate at voltages down to 0.8 volts. This significantly reduces the total power. To Loop Filter Ref. Input 3 Volts Phase Comparator and Charge pump Low Speed Counters 0.8 3 Volts Regulator Prescaler PE3291 ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 15 PE3291 Product Specification Figure 2. Pin Configurations (Top View) Figure 3. Package Type 20-lead TSSOP N/C 1 20 VDD VDD 2 19 VDD CP1 3 18 CP2 GND 4 17 GND fin1 5 16 fin2 Dec1 6 15 Dec2 VDD1 7 14 VDD2 fr 8 13 LE GND 9 12 Data foLD 10 11 Clock Table 1. Pin Descriptions Pin No. Pin Name Type Description 1 N/C No connect. 2 VDD (Note 1) Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. 3 CP1 Output Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external VCO. 4 GND 5 fin1 6 Dec1 Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. 7 VDD1 PLL1 prescaler power supply (FlexiPower 1). 8 fr 9 GND 10 foLD Output Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table). 11 Clock Input CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift register. 12 Data Input Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits. 13 LE Input Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into one of the four appropriate latches (as assigned by the control bits). 14 VDD2 Output PLL2 prescaler power supply (FlexiPower 2). 15 Dec2 Output Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. 16 Fin2 Input Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz. 17 GND 18 CP2 Output Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO. 19 VDD (Note 1) Same as pin 2. 20 VDD (Note 1) Same as pin 2. Ground. Input Input Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.2 GHz. Reference frequency input. Ground. Ground. Note 1: VDD pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 15 Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions PE3291 Product Specification PE3291 Description FlexiPower Operation The PE3291 is intended for such applications as the local oscillator for the RF and first IF of dualconversion transceivers. The RF PLL (PLL1) includes a 32/33 prescaler with a 1200 MHz maximum frequency of operation, where the IF PLL (PLL2) incorporates a 16/17 prescaler with a 550 MHz maximum frequency of operation. Using an advanced fractional-N phase-locked loop technique, the PE3291 can generate a stable, very low phase-noise signal. The dual fractional architecture allows fine resolution in both PLLs, with no degradation in phase noise performance. Each FlexiPower PLL prescaler can be supplied its own dedicated supply voltage as low as 0.8 volts for substantial power savings. The maximum frequency of operation scales with the FlexiPower supply voltage. If voltages less than VDD are not available, the FlexiPower supplies can be internally generated, but the power savings will not be as great as when using external FlexiPower supplies. Data is transferred into the PE3291 via a threewire interface (Data, Clock, LE). Supply voltage can range from 2.7 to 3.3 volts for VDD and from 0.8 to 3.3 volts for the FlexiPower supply. PE3291 features very low power consumption and is available in a 20-lead TSSOP (JEDEC MO-153AC) package. Spurious Response A critical parameter for synthesizer designs is spurious output. Spurs occur at the integer multiples of the step size away from center tone. An important feature of fractional synthesizers is their ability to reduce these spurious sidebands. The PE3291 has a built-in method for reducing these spurs, with no external components or tuning required. In addition, this circuitry works over the full commercial temperature range. Figure 4. PE3291 Block Diagram 32/33 Prescaler fin1 fr Ref. Amp. Fractional Spur Compensation 19-bit Fractional-N Main Divider 9-bit Reference Divider Phase Detector Charge Pump CP1 Clock 21-bit Serial Control Interface Data LE 9-bit Reference Divider fin2 16/17 Prescaler Document No. 70-0009-04 │ www.psemi.com 18-bit Fractional-N Main Divider Multiplexer Phase Detector Charge Pump foLD CP2 Fractional Spur Compensation ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 15 PE3291 Product Specification Table 2. Absolute Maximum Ratings Symbol Table 3. Operating Ratings Parameter/Conditions Min Max Units Symbol Min Max Units Supply voltage -0.3 4.0 V VDD Supply voltage 2.7 3.3 V VI Voltage on any input -0.3 V TA Operating ambient -40 85 °C II DC into any input -10 VDD + 0.3 +10 mA IO DC into any output -10 +10 mA Storage temperature range -65 150 °C VDD Tstg Parameter/Conditions Table 4. ESD Ratings Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC and AC Characteristics table. Exposure to absolute maximum ratings for extended periods may affect device reliability. Symbol Parameter/Conditions Level Units VESD ESD voltage human body model 1000 V Note 1: Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol IDD Parameter 3 V supply current when VDD1 and VDD2 are internally regulated down from VDD (note 1) Conditions P2, P1 = 1X C10, C20 = 01 P2, P1 = 01 C10, C20 = 00 P2, P1 = 10 C10, C20 = 00 P2, P1 = 11 C10, C20 = 00 P2, P1 = 00 RF PLL1 high speed IF PLL2 off RF PLL1 low speed IF PLL2 low speed RF PLL1 high speed IF PLL2 low speed RF PLL1 high speed IF PLL2 high speed 2 PLL’s enabled 1 PLL enabled IDD 3 V supply current when VDD1 and VDD2 are externally supplied (note 1) IDD1 PLL1 FlexiPower Prescaler supply current (see fig. 5) P2, P1 = 00 VDD1 = 1/0 volt VDD1 = 1.8 volts VDD1 = 2.7 volts PLL1 enabled PLL2 FlexiPower Prescaler supply current (see fig. 5) P2, P1 = 00 VDD2 = 1.0 volt VDD2 = 1.8 volts VDD2 = 2.7 volts PLL2 enabled IDD2 Istby Total standby current Digital inputs: Clock, Data, LE VIH High level input voltage VIL Low level input voltage Min (10 MHz Ref. Freq.) P2, P1 = 01 RF RF PLL1 low speed VDD = 2.7 to 3.3 volts VDD = 2.7 to 3.3 volts 0.7 x VDD Typ Max Units 1.4 mA 2.0 mA 2.1 mA 2.7 mA 3.1 mA 1.0 0.7 mA mA 0.5 1.5 4.0 mA mA mA 0.4 1.2 2.0 5 50 mA mA mA mA 0.3 x VDD V V IIH High level input current VIH = VDD = 3.3 volts -1 +1 mA IIL Low level input current VIL = 0, VDD = 3.3 volts -1 +1 mA Note 1: The total current consumed by the device is IDD when internal regulation is employed and IDD + IDD1 + IDD2 when VDD1 and VDD2 are externally supplied. When VDD1 and VDD2 are internally generated, pins 7 and 14 should be left floating. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 15 Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions PE3291 Product Specification Table 5. DC Characteristics (continued): VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units +25 mA Reference Divider input: fr IIHR Input current VIH = VDD = 3.6 volts IILR Input current VIL = 0, VDD = 3.6 volts -25 mA VDD-0.4 V Digital output: foLD VOLD Output voltage LOW Iout = 1 mA VOHD Output voltage HIGH Iout = -1 mA V Charge Pump outputs: CP1, CP2 ICP - Source ICP - Sink ICPL Drive current VCP = VDD / 2 Leakage current 0.5 V < VCP < VDD-0.5 volt Sink vs. Source mismatch VCP = VDD / 2, TA = 25° C -70 mA 70 mA -5 5 nA ICP – Source vs. 10 % ICP vs. TA Output current vs. temperature VCP = VDD / 2 10 % ICP vs. VCP Output current magnitude variation vs. voltage 0.5 V < VCP < VDD – 0.5 volt, TA = 25° C 10 % Figure 5. Prescaler Current vs. FlexiPower Voltage (VDD1 and VDD2 externally supplied) 4.00 PLL1 3.00 Typic al Cur r ent ( mA) PLL2 2.00 1.00 0.00 0.8 1.2 1.6 2 2.4 FlexiPower voltage (V DD1 2.8 ,V DD2 3.2 ) Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Max Units 10 MHz Control Interface and Latches (see figure 8) fClk Serial data clock frequency tClockH Serial clock HIGH time 50 ns tClockL Serial clock LOW time 50 ns tDSU Data set-up time to Clock rising edge 50 ns tDHLD Data hold time after Clock rising edge 10 ns tLEW LE pulse width 50 ns tCLE Clock falling edge to LE rising edge 50 ns tLEC LE falling edge to Clock rising edge 50 ns tData Out Data Out delay after Clock falling edge (foLD pin) Document No. 70-0009-04 │ www.psemi.com CL = 50 pf 90 ns ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 15 PE3291 Product Specification Table 6. AC Characteristics (continued): VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Main Divider (Including Prescaler) fin1 Operating frequency (see figure 6) fin2 Operating frequency (see figure 6) Conditions Min Max Units P2, P1 = 00 VDD1 = 1.0 volts VDD1 = 1.8 volts VDD1 = 2.7 volts 300 300 300 450 900 1200 MHz MHz MHz P2, P1 = 01 VDD1 = internally generated (low speed) 300 800 MHz P2, P1 = 1X = (10 or 11) VDD1 = internally generated (high speed) 300 1100 MHz P2, P1 = 00 VDD1 = 1.0 volts VDD1 = 1.8 volts VDD1 = 2.7 volts 45 45 45 300 550 550 MHz MHz MHz P2, P1 = 01 or 10 VDD2 = internally generated (low speed) 45 300 MHz P2, P1 = 11 VDD1 = internally generated (high speed) 45 550 MHz Pfin1 Input level range External AC coupling -10 5 dBm Pfin2 Input level range External AC coupling -10 5 dBm 10 MHz 50 MHz Comparison frequency fc Reference Divider fr Operating frequency Vfr Input sensitivity Note 1: External AC coupling (note 1) 0.5 VP-P CMOS logic levels may be used if DC coupled Figure 6. PLL Maximum Frequency vs. FlexiPower Voltage Typic al Freque ncy (MHz) 1400 1200 PLL1 1000 800 600 PLL2 400 200 2.4 2.8 3.2 0.8 1.2 1.6 2 FlexiPower voltage (VDD1 ,VDD2 ) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 15 Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions PE3291 Product Specification Functional Description the reference frequency fr by the following equation: The Functional Block Diagram in Figure 7 shows a 21-bit serial control register, a multiplexed output, and PLL sections PLL1 and PLL2. Each PLL contains a fractional-N main counter chain, a reference counter, a phase detector, and an internal charge pump with on-chip fractional spur compensation. Each fractional-N main counter chain includes an internal dual modulus prescaler, supporting counters, and a fractional accumulator. fin1 = [(32 x M1) + A1 + (F1/32)] x (fr/R1) (1) Note that A1 must be less than M1. Also, fin1 must be greater than or equal to 1024 x (fr/R1) to obtain contiguous channels. The PLL2 (IF) VCO frequency fin2 is related to the reference frequency fr by the following equation: Serial input data is clocked on the rising edge of Clock, MSB first. The last two bits are the address bits that determine the register address. Data is transferred into the counters as shown in Table 8, PE3291 Register Set. If the foLD pin is configured as data out, then the contents of shift register bit S20 are clocked on the falling edge of Clock onto the foLD pin. This feature allows the PE3291 and compatible devices to be connected in a daisychain configuration. fin2 = [(16 x M2) + A2 + (F2/32)] x (fr/R2) (2) Note that A2 must be less than M2. Also, fin2 must be greater than or equal to 256 x (fr/R2) to obtain contiguous channels. F1 sets PLL1 fractionality. If F1 is an even number, the PE3291 automatically reduces the fraction. For example, if F1 = 12, then the fraction 12/32 is automatically reduced to 3/8. In this way, fractional denominators of 2, 4, 8, 16 and 32 are available. F2 sets the fractionality for PLL2 in the same manner. The PLL1 (RF) VCO frequency fin1 is related to Figure 7. Functional Block Diagram A1 5 P1 fr Prescaler Control Logic M1 9 F1 5 M1 Counter 3<M1<511 F1 Counter 0<F1<31 P2 32/33 Prescaler fin1 A1 Counter 0<A1<31 Ref. Amp. 9-bit Reference Divider Fractional Spur Compensation Phase Detector R1 9 C11 Charge Pump C12 Clock 21-bit Serial Control Interface Data LE Multiplexer R2 9 C21 9-bit Reference Divider fin2 16/17 Prescaler P1 Phase Detector M2 Counter 3<M2<511 F2 Counter 0<F2<31 M2 9 F2 5 A2 Counter 0<A2<15 Prescaler Control Logic CP1 C22 Charge Pump C22 C22 C22 foLD C22 CP2 Fractional Spur Compensation P2 A2 4 Document No. 70-0009-04 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 15 PE3291 Product Specification Table 7. Register Set S20 S19 S18 S17 Reserved S16 S15 Test 0 S14 S13 S12 S11 S10 C24 C23 C22 C21 M26 M25 M24 FlexiPower voltage regulation Res. P2 Res. P1 M23 M22 C20 R28 C13 C12 M17 M16 M15 M14 M13 M12 S6 R 26 R 25 M21 C11 M10 S4 S3 S2 M20 A23 A22 A21 A20 R 23 R 22 F24 F23 F22 R 21 R 20 F21 F20 PLL1 Reference counter R1 divide ratio C10 R18 R17 R16 R15 R14 A14 A13 A12 A11 R13 R12 F14 F13 MSB (first in) F12 S0 0 0 Address 0 1 Address R11 R10 PLL1 Fractional counter F1 numerator value A10 S1 Address PLL2 Fractional counter F2 numerator value PLL1 Swallow counter A1 divide ratio M11 S5 R 24 PLL2 Swallow counter A2 divide ratio PLL1 Main counter M1 divide ratio M18 R 27 PLL1 Synthesizer control C14 S7 PLL2 Reference counter R2 divide ratio Res. M27 S8 PLL2 Synthesizer control PLL2 Main counter M2 divide ratio M28 S9 F11 F10 1 0 Address 1 1 (last in) LSB Figure 8. Serial Interface Mode Timing Diagram Data tDSU tDHLD tClockL tClockH Clock tCLE tLEW tLEC LE tData Out Data Out (foLD pin) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 15 Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions PE3291 Product Specification Programmable Divide Values Table 8. PE3291 Counter Programming Example (R1, R2, F1, F2, A1, A2, M1, M2) Divide Value Data is clocked into the 21-bit shift register, MSB first. When LE is asserted HIGH, data is latched into the registers addressed by the last two bits shifted into the 21-bit register, according to Table 7. For example, to program the PLL1 (RF) swallow counter, A1, the last two bits shifted into the register (S0, S1) would be (1,1). The 5-bit A1 counter would then be programmed according to Table 8. For normal operation, S16 of address (0,0) (the Test bit) must be programmed to 0 even if PLL2 (IF) is not used. MSB LSB Address S11 S10 S9 S8 S7 S1 S0 A14 A13 A12 A11 A10 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 2 0 0 0 1 0 1 1 - - - - - - 1 1 31 1 1 1 1 1 1 1 Program Modes Several modes of operation can be programmed with bits C10 - C14 and C20 - C24, including the phase detector polarity, charge pump high impedance, output of the foLD pin and power-down modes. The PE3291 modes of operation are shown on Table 9. The truth table for the foLD output is shown in Table 10. Table 9. PE3291 Program Modes S15 S14 S13 S12 S11 C24 C23 C22 C21 (Note 2) C20 (Note 1) See Table 10 See Table 10 0 = PLL2 CP normal 0 = PLL2 Phase Detector inverted 0 = PLL2 on 1 = PLL2 CP High Z 1 = PLL2 Phase Detector normal 1 = PLL2 off C14 C13 C12 C11 (Note 2) C10 (Note 1) See Table 10 See Table 10 0 = PLL1 CP normal 0 = PLL1 Phase Detector inverted 0 = PLL1 on 1 = PLL1 CP High Z 1 = PLL1 Phase Detector normal 1 = PLL1 off S1 S0 0 0 1 0 Note 1: The PLL1 power-down mode disables all of PLL1’s components except the R1 counter and the reference frequency input buffer, with CP1 (pin 3) and fin1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and fin2 (pin 16) becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R1 and R2, the reference frequency input, and the foLD output, causing fr (pin 8) and foLD (pin 10) to become high impedance. The Serial Control Interface remains active at all times. Note 2: The C11 and C21 bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 9. This relationship presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted. Figure 9. VCO Characteristics (1) Positive slope VCO VCO Output Frequency • When VCO1 (RF) slope is positive like (1), C11 should be set HIGH. • When VCO1 (RF) slope is negative like (2), C11 should be set LOW. • When VCO2 (IF) slope is positive like (1), C21 should be set HIGH. • When VCO2 (IF) slope is negative like (2), C21 should be set LOW. (2) Negative slope VCO VCO Input voltage Document No. 70-0009-04 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 15 PE3291 Product Specification Table 10. foLD Programming Truth Table X = don’t care condition C14 C13 C24 C23 (PLL1F0) (PLL1LD) (PLL2F0) (PLL2LD) 0 0 0 0 0 1 0 0 0 0 0 1 PLL1 / PLL2 Lock detect 0 1 0 1 PLL1 Reference divider output (fc1) 1 X 0 0 PLL2 Reference divider output (fc2) 0 X 1 0 PLL1 Programmable divider output (fp1) 1 X 0 1 PLL2 Programmable divider output (fp2) 0 X 1 1 Serial data out 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 1 0 Counter reset3 1 1 1 1 foLD Output State Disabled1 2 PLL 1 Lock detect (LD1) 2 PLL2 Lock detect (LD2) 2 Note: 1. When the foLD is disabled the output is a CMOS LOW. 2. Lock detect indicates when the VCO frequency is in “lock”. When PLL1 is in lock and PLL1 lock detect is selected, the foLD pin will be HIGH with narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the foLD pin will be HIGH with narrow pulses LOW. When PLL1 / PLL2 lock detect is selected the foLD pin will be HIGH with narrow pulses LOW only when both PLL1 and PLL2 are in lock. 3. The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in close alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth acquisition upon powering up. Programming the FlexiPower voltage The PE3291 can be programmed to internally regulate down from the VDD voltage to supply the FlexiPower voltage, as shown in Table 11. This is implemented by programming P2, P1 (S18 & S16 - address 1,0). When programmed with 0,0 external voltage supplies must be provided to the part at pins VDD1 and VDD2. When using internal regulation, the FlexiPower supply pins should be left grounded. Table 11. FlexiPower Voltage Regulation Programming P2 P1 FlexiPower 1 voltage (RF PLL1) FlexiPower 2 voltage (IF PLL2) 0 0 0 1 Low power Low power 1 0 High speed Low power 1 1 High speed High speed No regulation (FlexiPower externally provided) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 15 Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions PE3291 Product Specification Phase Comparator Characteristics PLL1 has the timing relationships shown below for fc1, fp1, LD1, UP1, and DOWN1. When C11 = HIGH, UP1 directs the internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump to sink current. If C11 = LOW, UP1 and DOWN1 are interchanged. PLL2 has the timing relationships shown below for fc2, fp2, LD2, UP2, and DOWN2. When C21 = HIGH, UP2 directs the internal PLL2 charge pump to source current and DOWN2 directs the PLL2 internal charge pump to sink current. If C21 = LOW, UP2 and DOWN2 are interchanged. Figure 10. Phase Comparator Timing Diagram fc1 (2) (Note 1) fp1 (2) (Note 1) LD1 (2) (Note 1) UP1 (2) DOWN1 (2) fc leads fp fc = fp fc lags fp fc lags fp fc lags fp Note 1: fc1(2), fp1(2), and LD1(2) are accessible via the foLD pin per programming in Table 11. Document No. 70-0009-04 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 15 PE3291 Product Specification Loop Filter Digital Control Lines Second/Third Order Loops Control Line Noise Choosing the optimum loop filter for a design encompasses many trade offs. The rule of thumb for choosing the loop filter bandwidth is 10 percent of the step size. A second order loop (C1 C2 R2 and C4 C5 R5 in Figure 11 omitting C3 R3 C6 and R6) will provide the least amount of components and the fastest lock times. If lock time is an issue, one might try opening up the loop filter, although if it is too wide, instability will dominate and worsen lock time. If lock time is not an issue, a narrower second order filter will minimize residual FM without requiring additional components. We have noticed frequency jitter during programming when a low impedance, such as a capacitor to ground, is placed next to any control line pin (clock, data, and load enable). The use of a 51 k ohm resistor in series with the control line will eliminate the problem with no effect to programming time. Third Order loop filters (C1 C2 R2 C3 R3 and C4 C5 R5 C6 R6 in Figure 11) provide a good compromise between lock time and residual FM. We have found using a third order loop with 20 dB of rejection at the step size will halve the Residual FM as measured with a similar second order loop, with minimum effect on lock time. Loop Filter Bandwidth Design Considerations As part of the spur compensation circuitry, the PE329x series PLLs contain capacitors to ground internal to the charge pump. PLL1 contains a 50 pF capacitor and PLL2 contains a 100 pF capacitor. To ensure accurate loop filter calculations, it is critical that the calculated value of the first shunt capacitor (C1 & C4 in Figure 11) be at least 100 pF for PLL1 and 200 pF for PLL2. With this requirement satisfied, the remaining loop components can be calculated. Enable Line Voltage The PE329x series PLLs use a level sensitive load enable. Therefore the digital controller must provide an active low to the part at all times except when the data is to be loaded into the shift register. If the PLL controller does not hold the voltage low, a high impedance resistor to ground should be added to the enable line to ensure stable operation. 5 Volt Operation: The PE329x series PLLs are not capable of accepting control voltages greater than 3.3 volts. Interface to 5 volt controllers requires the addition of resistor dividers to comply with the 3.3 volt maximum operation voltage. For a stable loop, it is also important that the loop bandwidth be less than or equal to one tenth of the step size. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 15 Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions PE3291 Product Specification Figure 11. Application Example Note 1: For optimum fractional spur and lock-time performance C2 and C5 should be polyester (or poly propylene). In addition, the loop filter components must be free from contamination. Contamination will result in poor spur performance. For accurate loop bandwidth, C1 must be greater than or equal to 100 pF, and C4 must be greater than or equal to 200 pF. Document No. 70-0009-04 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 15 PE3291 Product Specification Figure 12. Package Drawing 20-lead TSSOP (JEDEC MO-153-AC) 12o REF 0.20 R 0.90 MIN TOP VIEW 0.65BSC 19 20 18 17 16 15 14 13 12 R 0.90 MIN GAGE PLANE 11 0o 8o 12o REF 0.25 +.15 0.60 -.10 1.0 REF 3.20 2X 4.40±0.10 Ø1.00±0.10 1.00 -B- 1.00 1 2 3 4 5 6 7 8 9 .20 C B A 10 6.40 0.325 SIDE VIEW S Y M B O L -A6.50±0.10 0.90±0.05 1.10 MAX -C0.10 C 0.30 MAX 0.10 0.10±0.05 C B A FRONT VIEW S Y M B O L D E1 E e N O T E AC MIN 6.40 NOM 6.50 MAX 6.60 4.30 4.40 6.4 BSC 4.50 N NOTE ISSUE 3,8 4,8 0.65 BSC 20 1,2 6 A COMMON DIMENSION(MILLIMETERS) 0.65mm LEAD PITCH MIN --- NOM --- MAX A A1 A2 0.05 0.85 --0.90 0.15 0.95 L R 0.50 0.09 R1 b 0.09 0.19 0.60 ----- 0.75 ----- b1 c 0.19 0.09 c1 01 0.09 0° 1.10 --- 0.30 0.22 ----- 0.25 0.20 --- L1 aaa 1.0 REF 0.10 bbb ccc 0.10 0.05 ddd e 0.65 BSC 02 03 12° REF 12° REF 0.16 8° 0.20 Table 12. Ordering Information Order Code Part Marking Description Package Shipping Method 3291-11 PE3291 PE3291-20TSSOP-74A 20-lead TSSOP 74 units / Tube 3291-12 PE3291 PE3291-20TSSOP-2000C 20-lead TSSOP 2000 unit / T&R 3291-00 PE3291EK PE3291-20TSSOP-Eval Kit Evaluation Kit 1 / Box ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 15 Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions PE3291 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corporation Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor, Korea Peregrine Semiconductor Europe #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si, Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 South Asia Pacific Space and Defense Products Peregrine Semiconductor, China Americas: Tel: 505-881-0438 Fax: 505-881-0443 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0009-04 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 15 of 15