HYNIX GDC21D301A

GDC21D301A
(Transport Decoder)
Version 1.5
HDS-GDC21D301A-9908 / 10
GDC21D301A
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by Hyundai for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or
patent rights of Hyundai or others.
These Hyundai products are intended for usage in general electronic equipment (office equipment,
communication equipment, measuring equipment, domestic electrification, etc.).
Please make sure that you consult with us before you use these Hyundai products in equipment which
require high quality and / or reliability, and in equipment which could have major impact to the welfare of
human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of
safety devices, etc.). Hyundai cannot accept liability to any damage which may occur in case these
Hyundai products were used in the mentioned equipment without prior consultation with Hyundai.
Copyright 1999 Hyundai Micro Electronics Co.,Ltd.
All Rights Reserved
3
GDC21D301A
TABLE OF CONTENTS
1. General Description................................................................................................................. 5
2. Features .................................................................................................................................... 5
3. Pin Description......................................................................................................................... 6
4. Block Diagram........................................................................................................................ 12
5. Functional Description .......................................................................................................... 13
5.1 Forward-Error-Correction (FEC) Interface........................................................................ 13
5.2 Sync Detector ................................................................................................................... 13
5.3 TS Header Decoder.......................................................................................................... 13
5.4 Adaptation Field Decoder ................................................................................................. 13
5.5 PES Decoder .................................................................................................................... 13
5.6 Memory Controller ............................................................................................................ 14
5.7 High-Speed Interface........................................................................................................ 14
5.8 External Decoder Interface ............................................................................................... 14
5.9 Host Interface ................................................................................................................... 14
5.10 Clock Controller .............................................................................................................. 14
6. Register Description.............................................................................................................. 15
7. Electrical Specification.......................................................................................................... 30
7.1 Absolute Maximum Rating................................................................................................ 30
7.2 Recommended Operating Range ..................................................................................... 30
7.3 DC Characteristics (VDD = 3.3 V ± 10%, TA = 0 ~ 70 °C ) .............................................. 30
7.4 AC Characteristics (VDD = 3.3 V ± 10%, TA = 0 ~ 70 °C ) .............................................. 31
7.4.1 Transport Stream Interface Requirements.................................................................. 31
7.4.2 Clock Interface Requirements..................................................................................... 31
7.4.3 Reset Signal Requirement .......................................................................................... 32
7.4.4 Audio/Video/Data Decoder Interface Requirements ................................................... 32
7.4.5 Host Processor Interface Requirements ..................................................................... 33
8. Package Mechanical Data ..................................................................................................... 34
8.1 Package Pin out................................................................................................................ 34
8.2 Package Dimensions ........................................................................................................ 36
4
GDC21D301A
GDC21D301A
Transport Decoder
1. General Description
The GDC21D301A Transport Decoder
resides in the center of an MPEG-2 decoding
system. It accepts MPEG-2 transport streams,
parses the transport and packetized
elementary stream (PES) layers into the
separate data streams, and provides rate
buffering for the parsed data streams. Then it
passes those data streams to video and audio
decoders. The GDC21D301A also extracts
Program Clock Reference (PCR) in the data
stream and provides the Pulse Width
Modulation (PWM) signals in order to
recover the clock and to synchronize the
playback of video and audio. The
GDC21D301A manages an external DRAM
that is used for data storage and buffering the
various parsed data streams. This DRAM is
shared with the host processor so that the
system’s memory requirements can be
consolidated into a single, low-cost DRAM.
The GDC21D301A stores data packets
destined for the host directly in shared
DRAM for easy access by the host.
2. Features
The GDC21D301A is fully compliant with MPEG2 ISO/IEC 13818-1 specification.
Decoding Features
• Performs MPEG-2 transportation and PES layer
handling
• Supports maximum 80 Mbps transport streams
• Provides a high-speed data output port
• Identifies and extracts up to 32 transport stream
(TS) packet PIDs
PCR & Time Stamp Control Features
• Provides two PWM signals to recover the system
clock
• Provides the instant value of internal STC
counter when a frame begins
• Extracts PTS and DTS of video and audio for
Lip-synchronization
Interface
• Supports byte-parallel/bit-serial TS input
• Supports video/audio PES layer or elementary
stream layer output
• Provides error code insertion capability in video
elementary stream
• Supports an external error input signal for
declaring an erroneous packet
• Supports 8/16-bit host bus interface
5
GDC21D301A
DSP_DATA[12]
VDD
DSP_DATA[11]
DSP_DATA[10]
DSP_DATA[9]
DSP_DATA[8]
VSS
DSP_DATA[7]
DSP_DATA[6]
DSP_DATA[5]
DSP_DATA[4]
VDD
DSP_DATA[3]
DSP_DATA[2]
DSP_DATA[1]
DSP_DATA[0]
VSS
NC
VDD
CLOCK
BIT8MODE
DSP_ADDR[0]
DSP_ADDR[1]
DSP_ADDR[2]
DSP_ADDR[3]
DSP_ADDR[4]
DSP_ADDR[5]
DSP_ADDR[6]
DSP_ADDR[7]
DSP_ADDR[8]
DSP_ADDR[9]
DSP_ADDR[10]
DSP_ADDR[11]
DSP_ADDR[12]
DSP_ADDR[13]
DSP_ADDR[14]
DSP_ADDR[15]
DSP_ADDR[16]
DSP_ADDR[17]
DSP_ADDR[18]
DSP_ADDR[19]
DSP_ADDR[20]
DSP_ADDR[21]
DSP_ADDR[22]
3. Pin Description
DSP_DATA[13]
DSP_DATA[14]
DSP_DATA[15]
VSS
DSP_INT
DSP_READY
VDD
TDO0
TDO1
VDD
HSDEN
HIGH_SP_DATA[1]
HIGH_SP_DATA[0]
CLOCK_OUT
VSS
TA[7]
TA[6]
TA[5]
TA[4]
TA[3]
TA[2]
TA[1]
TA[0]
VSS
TWEB
TEST
TDI
P_S_MODE
F_START
FEC_DATA[7]
FEC_DATA[6]
FEC_CLOCK
VDD
NC
VSS
FEC_DATA[5]
FEC_DATA[4]
FEC_DATA[3]
FEC_DATA[2]
FEC_DATA[1]
FEC_DATA[0]
ERR_BLOCK_B
D_VALID
S C A N _ M O D E /T A [ 8 ]
1
176
133
HME
G D C 21D301A
YYW W
89
45
DRAM_DATA[2]
VSS
DRAM_DATA[3]
DRAM_DATA[4]
DRAM_DATA[5]
DRAM_DATA[6]
VDD
DRAM_DATA[7]
DRAM_DATA[8]
DRAM_DATA[9]
DRAM_DATA[10]
VSS
DRAM_DATA[11]
DRAM_DATA[12]
DRAM_DATA[13]
DRAM_DATA[14]
VSS
NC
VDD
CLOCK_27M
VDD
DRAM_DATA[15]
\DRAM_CAS0
\DRAM_CAS1
\DRAM_RAS0
VSS
\DRAM_RAS1
DRAM_ROW_COL_ADDR[0]
DRAM_ROW_COL_ADDR[1]
DRAM_ROW_COL_ADDR[2]
VDD
DRAM_ROW_COL_ADDR[3]
DRAM_ROW_COL_ADDR[4]
DRAM_ROW_COL_ADDR[5]
DRAM_ROW_COL_ADDR[6]
VSS
DRAM_ROW_COL_ADDR[7]
DRAM_ROW_COL_ADDR[8]
DRAM_ROW_COL_ADDR[9]
DRAM_RWB
VDD
M16
SCAN_IN1/TA[9]
SCAN_TEST
Figure 1. Pin Description
6
NC
NC
VSS
\DSP_PD
DSP_RW B
\DSP_STRB
VPW M
\VID_STRB
VDD
\VID_DCS
VAD_ DATA[0]
VDD
VAD_ DATA[1]
VAD_ DATA[2]
VSS
VAD_ DATA[3]
VAD_ DATA[4]
VAD_ DATA[5]
VAD_ DATA[6]
VDD
\RESET
SCAN_OUT1
VAD_ DATA[7]
PTS_DTS_STRB
\DATA_STRB
\DATA_DCS
VSS
\AUD_STRB
AUD_SER_DATA
\AUD_DCS
VSS
APW M
VDD
BOF_V
BOF_A
BOF_D
\VID_REQ
\VID_W AIT
\AUD_REQ
\AUD_W AIT
\DATA_REQ
\DATA_W AIT
DRAM_DATA[0]
DRAM_DATA[1]
GDC21D301A
(Package : 176TQFP)
NAME
CLOCK
CLOCK_27M
CLOCK_OUT
\RESET
TEST
TA[9:0]
TDI
TWEB
TDO0
TDO1
P_S_MODE
FEC_DATA[7:0]
F_START
FEC_CLOCK
PIN
TYPE
DESCRIPTION
CLOCKS & RESET
157
I
Operation clock.
The frequency of operating clock is 27MHz and it should be
locked in encoder system clock. The clock may be supplied by
external VCXO controlled by VPWM.
69
I
27MHz clock.
It is used to count STC value. This clock may be supplied by
external VCXO controlled by VPWM.
14
O
Operation Clock Output.
For high-speed output data
112
I
Global Reset (active low)
The signal asynchronously resets the GDC21D301A.
TEST INTERFACE (for IC self-test purpose only)
26
I
Test Mode
46,44,16,17,
I
Test address.
18,19,20,21,2
TA[9] and TA[8] are respectively multiplexed with SCAN_IN1
2,23
and SCAN_MODE pins.
27
I
Test Input Data
25
I
Test Write Enable (active low)
8
O
Test Output Data0
9
O
Test Output Data1
TRANSPORT STREAM INTERFACE
28
I
FEC Data Input Mode Selection.
0: byte-parallel input mode
1: bit-serial input mode
30,31,36,37,
I
TS Data.
38,39,40,41
It is used for byte-parallel or bit-serial transfers of a coded TS
data to the device. In bit-serial mode, FEC_DATA[0] is a serial
data input for TS data.
29
I
FEC Sync Byte Indicator.
F_START is valid in bit-serial input mode only. FEC_DATA
is aligned by the byte parallel with this signal. This signal
should be activated at the first bit of the TS sync byte or every
first bit of the data byte.
32
I
FEC Data Clock.
FEC_CLOCK is used to latch a data byte or a single bit of
coded TS into the device on the rising edge. FEC_CLOCK may
be asynchronous with the device. The value of FEC_DATA is
locked into the GDC21D301A internal buffer on the rising
edge of FEC_CLOCK, if D_VALID is asserted HIGH.
7
GDC21D301A
Pin Description (continued)
NAME
PIN
\ERR_BLOCK
42
D_VALID
43
HSDEN
HIGH_SP_DATA
[1:0]
11
12, 13
TYPE
DESCRIPTION
HIGH SPEED DATA INTERFACE
I
FEC Packet Error (active low).
This optional signal may be used to declare that the error has
occurred in a packet. It is used in place of
transport_error_indicator bit in the TS header by the equipment
interfacing with the GDC21D301A.
I
FEC Data Valid.
This signal indicates that the data value of FEC_DATA bus is
valid transport stream byte or serial bit. It will be latched in the
internal buffer on the rising edge of FEC_CLOCK.
O
High Speed Port Data Enable
O
High Speed Port Data
CLOCK RECOVERY INTERFACE
O
Pulse Width Modulated Pulse1.
Low pass filtered VPWM signal is fed to external VCXO for
adjusting its output frequency.
101
O
APWM
Pulse Width Modulated Pulse2.
This is used to lock the Audio clock in the Video clock for lip
synchronization. Low pass filtered APWM signal is fed to the
VCXO.
DRAM INTERFACE
47
I
M16
DRAM 16-Mbit Configuration
49
O
DRAM_RWB
DRAM Read/Write.
When you access DRAM, read mode or write mode can be
set as following.
0 : Write mode
1 : Read mode
O
DRAM_ROW_COL_ 50,51,52,54,
DRAM Parallel Address Bus [9:0].
55,56,57,59,
Row-column address is multiplexed when you access external
ADDR[9:0]
60,61
DRAM. For the fast page mode access, row address is applied
first, and column address is applied next.
I/O/Z
DRAM_DATA[15:0] 67,73,74,75,
DRAM Parallel Data Bus [15:0].
76,78,79,80,
81,83,84,85,
86,88,89,90
64
O
\DRAM_RAS0
DRAM Row Address Strobe0.
Select DRAM0 device. When this signal goes to low, DRAM_
ROW_COL_-ADDR[9:0] has a valid row address.
62
O
\DRAM_RAS1
DRAM Row Address Strobe1.
Select the DRAM1 device. When this signal goes to low,
DRAM_ROW_COL_-ADDR[9:0] has a valid row address.
66
O
\DRAM_CAS0
DRAM Column Address Strobe0.
Select the low byte DRAM data. When this signal goes to low,
DRAM_-ROW_COL_ADDR[9:0] has a valid column address.
65
O
\DRAM_CAS1
DRAM Column Address Strobe1.
Select the high byte DRAM data. When this signal goes to low,
DRAM_-ROW_COL_ADDR[9:0] has a valid column address.
VPWM
8
126
GDC21D301A
Pin Description (continued)
NAME
\DSP_STRB
DSP_RWB
\DSP_PD
DSP_ADDR[22:0]
BIT8MODE
DSP_DATA[15:0]
DSP_READY
DSP_INT
PIN
TYPE
DESCRIPTION
HOST PROCESSOR INTERFACE
127
I
Host Strobe (active low) : Asynchronous.
Used by the host processor to access the GDC21D301A. When
DSP_STRB
signal
is
active,
DSP_ADDR[22:0],
DSP_DATA[15:0], and DSP_PD should be valid.
128
I
Read/Write (active low) : Asynchronous.
The state of this signal defines data transfer type.
0 : Write to the device
1: Read from the device
129
I
Transport Decoder Chip Selection (active low).
This signal is used to activate and access the internal registers
of the GDC21D301A, the video decoder, the audio decoder, the
data decoder, and DRAM.
133,134,135,
I
Host Address Bus.
136,137,138,
These signals are connected to the address bus of the host
139,140,141,
processor interfaced with the GDC21D301A, the video
142,143,144,
decoder, the audio decoder, the data decoder, and DRAM.
145,146,147,
0x4FFFFF ~ 0x4C0000 : Transport Decoder address space
148,149,150,
0x5BFFFF ~ 0x480000 : Video decoder space
151,152,153,
0x47FFFF ~ 0x440000 : Audio decoder space
154,155
0x43FFFF ~ 0x400000 : Auxiliary data decoder space
0x3FFFFF ~ 0x000000 : DRAM space
156
I
Host Interface Mode Selection.
0 : 16-bit data bus interface
1 : 8-bit data bus interface
3, 2, 1, 176,
I/O/Z
Host Data Bus.
174,173,172,
These signals are connected to the address bus of external host
171,169,168,
processor.
167,166,164,
163,162,161
6
O/Z
Data Acknowledge (active high)
5
O
Interrupt Request (active high)
9
GDC21D301A
Pin Description (continued)
NAME
\VID_WAIT
\VID_REQ
\VID_STRB
\VID_DCS
VAD_DATA[7:0]
PTS_DTS_STRB
BOF_V
\AUD_WAIT
\AUD_REQ
AUD_SER_DATA
\AUD_STRB
\AUD_DCS
BOF_A
PIN
TYPE
DESCRIPTION
VIDEO DECODER INTERFACE
95
I
Video Wait (active low).
This signal indicates that the access of registers in the video
decoder is ready.
96
I
Video Compressed Data Request (active low).
A video decoder requests video data from the GDC21D301A
by using this signal.
125
O
Video Compressed Data Strobe (active low).
The signal indicates that the video data in VAD_DATA[7:0]
exists. The video decoder should latch the video data on the
rising edge of VID_STRB.
123
O
Video Chip Select (active low).
This signal activates data transfers between the video decoder
and the host processor. Host processor can access the registers
of the video decoder.
110,114,115,
I/O/Z
Video/Audio Decoder Data.
116,117,119,
Parallel bit stream output of compressed audio, video, and
120,122
auxiliary data.
109
O
Video PTS/DTS Strobe (active high).
When this signal is asserted High, the GDC21D301A puts PTS
(Presentation_Time_Stamp) or DTS (Decoding_Time_Stamp)
into VAD_DATA[7:0] bus.
99
I
Begin of Frame0.
On the rising edge of this signal, STC, the counted PCR value,
is copied to STC3_reg.
AUDIO DECODER INTERFACE
95
I
Audio Wait (active low).
This signal indicates that the access of registers in the audio
decoder is ready.
94
I
Audio Data Request (active low).
An audio decoder requests audio data from the GDC21D301A
by using this signal.
104
O
Audio Serial Data.
105
O
Audio Data Strobe (active low).
This signal indicates that audio data on VAD_DATA[7:0]
exists. \AUD_STRB signal can be used as the data clock for
serial and parallel data transmission. Thus, if output mode is
parallel, \AUD_STRB is 1-byte strobe. And if output mode is
serial, \AUD_STRB is 1-bit strobe.
103
O
Audio Select (active low).
This signal activates data transfers between the audio decoder
and the host processor. Host processor should communicate
data with the audio decoder through the GDC21D301A.
98
I
Begin of Frame1.
On the rising edge of this signal, STC, the counted PCR_value,
is copied to STC3_reg.
GDC21D301A
Pin Description (continued)
NAME
\DATA_WAIT
\DATA_REQ
\DATA_STRB
\DATA_DCS
BOF_D
SCAN_MODE
SCAN_TEST
SCAN_IN1
SCAN_OUT1
VDD
VSS
PIN
TYPE
DESCRIPTION
AUXILIARY DATA DECODER INTERFACE
91
I
Auxiliary Data Wait (active low).
This signal indicates that the access of registers in the auxiliary
decoder is ready.
92
I
Auxiliary Data Request (active low).
This signal is asserted when an auxiliary device requests data
from the GDC21D301A.
108
O
Auxiliary Data Strobe (active low).
This signal qualifies data contained in VAD_DATA[7:0]. This
auxiliary decoder should latch the auxiliary data on the rising
edge of DATA_STRB.
107
O
Auxiliary Select (active low).
This signal activates data transfers between the auxiliary
decoder and the host processor. Host processor can access the
registers of the auxiliary decoder.
97
I
Begin of Frame2.
On the rising edge of this signal, STC, the counted PCR value,
is copied to STC3_reg.
SCAN TEST
44
I
Scan Test Mode Enable Input.
It has to be connected to VSS level.
45
I
Scan Test Mode Enable Input.
It has to be connected to VSS level.
46
I
Scan-path Input on Scan Test Mode.
It has to be connected to VSS level.
111
O
Scan-path Output on Scan Test Mode
POWER AND GROUND
7, 10, 33, 48, PWR
3.3 V Power Supply
58,68,70,82,
100,113,121,
124
4,15,24,35,
GND
Ground
53,63,72,77,
87,102,106,
118,130
11
GDC21D301A
4. Block Diagram
The figure 2 shows the internal block diagram of
the GDC21D301A. This chip receives the byteparallel/bit-serial
transport
data
from
FEC(Forward-Error-Correction) device, and stores
the whole data into DRAM. After decoding the
transport data in DRAM, it de-multiplexes audio,
video, and auxiliary data packets, and transfers
them into the corresponding decoder devices
FEC
Decoder
Transport
Stream
FEC
Interface
through the decoder interface blocks. The host
processor can control the GDC21D301A and
access the decoder devices and DRAM through the
host interface. The GDC21D301A generates PWM
pulses to control the frequency of system clock and
audio clock. The pulse width of PWM can be
programmed by the host processor.
TS Buffer
Buffer
8/16bit
8/16bit
MCU
MCU
Host
Interface
Sync
Detect
PID
Memory
TS Header
Decode
Memory
Controller
High-speed
Interface
Adaptation
Field
Decode
VCXO
Clock
Control
PES
Decode
External
Decoder
Interface
Figure 2. The Block Diagram of the Transport Decoder
12
4Mb
DRAM
GDC21D301A
5. Functional Description
5.1 Forward-Error-Correction (FEC)
Interface
The GDC21D301A can receive Transport Stream
packets in byte-parallel or bit-serial mode. FEC
Interface block gets these TS data, and temporarily
saves them in the internal buffer(TS Buffer).
In bit-serial mode, F_START should be
activated(high) when the most significant bit or the
first bit of each packet is fed. \ERR_BLOCK pin is
used to indicate valid packet, and D_VALID pin to
indicate valid TS data (it should be deactivated at
parity bits). TS data is fed on the rising edge of
FEC_CLOCK.
5.2 Sync Detector
This block searches the sync byte of TS
packet(0x47) at Sync Hysterisis register during
specified time. If it detects correct sync data, then
TS Header Decoder block takes control of
decoding process.
5.3 TS Header Decoder
This block decodes Transport Stream header and
determines if packet should be decoded further by
comparing PID with the values in internal PID
memory. PSI data is stored in external DRAM, and
can be read by the host processor. If high speed out
enable(Hig) bit in PID registers is activated, the
whole corresponding TS data are output to highspeed ports (refer to Register Description section).
5.4 Adaptation Field Decoder
Refer to the Register Description section
5.5 PES Decoder
This block decodes PES header and de-multiplexes
payload data to appropriate parts (refer to Register
Description section).
Audio and auxiliary data are stored in DRAM,
re-read by the GDC21D301A, and sent to
external decoder. But video data is directly
output to the external decoder.
13
GDC21D301A
5.6 Memory Controller
This controls DRAM interface. It refreshes
DRAM, writes and reads data to and from
DRAM. The corresponding addresses where
the data is written and read are stored in
pointer memory by the Host processor. The
GDC21D301A requires one or two DRAMs
(256Kx16b or 1Mx16b).
DRAM 0
(256Kx16 or 1M x 1 6 )
GDC21D301
D R A M _ A D D R [9:0]
A D D R [9:0]
D R A M _ D A T A [15:0]
D A T A [15:0]
\D R A M _ R A S 0
\R A S
\D R A M _ C A S 0
\L C A S
\U C A S
DRAM_RWB
RWB
DRAM 1
A D D R [9:0]
D A T A [15:0]
\D R A M _ R A S 1
\R A S
\D R A M _ C A S 1
\L C A S
M 16
\U C A S
RWB
Figure 3. External DRAM Interface
5.7 High-Speed Interface
This is an interface block of external high-speed
ports which send whole TS packets.
5.8 External Decoder Interface
This reads data from buffer and sends it to the
corresponding external decoder. It also controls the
input/output of data to and from external decoder.
5.9 Host Interface
Host Processor can access external decoders
through the GDC21D301A transport decoder.
DSP_DATA[15:0] ports are used for data bus.
14
To access one of the external decoders through the
GDC21D301A,
host
address
bus
(DSP_ADDR[22:0]) should be as follows.
For video decoder access,
DSP_ADDR[22:18] = “100 11”.
For audio decoder access,
DSP_ADDR[22:18] = “100 01”.
For auxiliary decoder access,
DSP_ADDR[21:18] = “100 00”.
5.10 Clock Controller
It outputs two PWM signals(VPWM and APWM)
which can be controlled by the Host Processor. The
PWM signals can be used to control external
VCXOs.
GDC21D301A
6. Register Description
This chapter describes the registers in the
GDC21D301A. Table 1 summarizes these registers.
Note the following general information:
• All registers are 16-bit wide and can read/write
unless especially noted.
• All accesses to internal registers are allowed by
word or byte using DSP_ADDR[0] pin which
determines access mode unit.
• The reserved bits should be written to zero to
preserve compatibility with future features.
• Register addresses that are not defined in Table 1
are reserved. Read from these locations causes
unpredictable results. It is recommended not to
access these registers.
• In order to access these register, you should
set DSP_ADDR[22:18] to “100 11”.
Table 1. Register Summary
ADDR[A10:A0]
000
002
004
006
008
00a
00c
00e
010
012
014
02a ~ 02e
030 ~ 034
036 ~ 03c
040
042,044
046
048
060,062
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R
R
R
R
R
R
R
R
REGISTERS
Interrupt Flag 1
Interrupt Flag 2
Interrupt Mask 1
Interrupt Mask 2
Instruction
Round Buffer
PID Flag 1
PID Flag 2
PWM control 1
PWM control 2
Sync Hysterisis
PTS
DTS
PCR
splicing_count_ down
ES_rate
DSM_trick_mode
additional_copy_info
STC 1
064,066
R
STC 2
068,06a
R
STC 3
06c,06e
R
STC 4
070,072
R
STC 5
400,402
404,406
408,40a
40c,40e
410 ~ 47a
47c,47e
R/W
R/W
R/W
R/W
R/W
R/W
Vid PID (0)
Aud PID (1)
Aux PID (2)
PSI_3 PID
PSI_4 ~ PSI_30 PID
PSI_31 PID
DEFINITION
Indicates active interrupts
Indicates active interrupts
Interrupt Enable
Interrupt Enable
Controls the decoding
Controls Buffer Management
Current Packet transferred
Current Packet transferred
Controls PWM output
Controls PWM output
Sets lock/unlock parameters for sync detect
PTS of Current Packet transferred
DTS of Current Packet transferred
PCR of Current Packet transferred
Current Splicing Countdown transferred
Current ES rate transferred
Current DSM trick mode transferred
Additional copy information
STC register contains the instant value of internal STC counter
when new PCR is transferred.
STC register contains the instant value of internal STC counter
when the beginning of frame signal(BOF1) is detected.
STC register contains the instant value of internal STC counter
when the beginning of frame signal(BOF2) is detected.
STC register contains the instant value of internal STC counter
when the beginning of frame signal(BOF3) is detected.
STC register contains the instant value of internal STC counter
when STC fetch instruction is activated.
Assigns Video PID
Assigns Audio PID
Assigns Auxiliary PID
Assigns PSI_3 PID
Assigns PSI_4 ~ PSI_30 PID
Assigns PSI_31 PID
15
GDC21D301A
Table 1. Register Summary (continued)
ADDR[A10:A0] R/W
REGISTERS
R/W PSI_3’s data buffer
618 ~ 61e
pointer
R/W PSI_4 ~ PID_30’s data
620 ~ 6f6
buffer pointer
R/W PSI_31’s data buffer
6f8 ~ 6fe
pointer
R/W channel buffer pointer
700 ~ 706
R/W audio compressed data
708 ~ 70e
buffer pointer
R/W audio PES extension
710 ~ 716
data buffer pointer
R/W video PES extension
718 ~ 71e
data buffer pointer
R/W auxiliary compressed
720 ~ 726
data buffer pointer
R/W auxiliary PES extension
728 ~ 72e
data buffer pointer
R/W transport_private_data
730 ~ 736
buffer pointer
R/W adf_extension_data
738 ~ 73e
buffer pointer
DEFINITION
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Start, End, Read, and Write Address
Interrupt Flag 1 (0x000)
15
8
7
0
Dci Rai Epi Pcf Opf Spf Tpf Aef Cef Xpf Vpf Apf Psh Psl Tpr Tei
FIELD
Dci
Rai
Epi
Pcf
Opf
Spf
Tpf
Aef
Cef
Xpf
Vpf
Apf
Psh
Psl
Tpr
Tei
16
BITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DESCRIPTION
discontinuity_indicator
random_access_indicator
elementary_stream_priority_indicator
PCR_flag
OPCR_flag
splicing_point_flag
transport_private_flag
adaptation_field_extension_flag
continuity counter error
auxiliary packet comes
video packet comes
audio packet comes
one of PSI16 ~ PSI_31 packets comes
one of PSI3 ~ PSI_15 packets comes
transport_priority
transport_error_indicator
VALUES
DEFAULT
GDC21D301A
Interrupt Flag 2 (0x002)
When an interrupt condition occurs, the
corresponding bit in Interrupt Flag registers are
asserted 1. Whenever a bit in the Interrupt Flag is 1,
the corresponding bit in Interrupt Mask registers is
set to 1, the Ien bit in the Instruction register to 1,
and the GDC21D301A asserts DSP_INT, the
external interrupt signal. Note that the occurrence
of an interrupt condition always causes the
corresponding bit in Interrupt Flag registers to be
set, even if the condition is disabled(i.e., the
corresponding bit in Interrupt Mask registers is
set to 0).
Interrupt Flag 1, 2 registers are cleared by the
15
In the GDC21D301A, Slk and Sdr is added to
indicate the state of Sync. The GDC21D301A first
searches Sync byte from transport stream. If the
device succeeds in finding 0x47, it writes
Slk(Sync_lock) bit in Interrupt flag 2 register. Until
sync is detected, Sdr flag maintains active high
state, so the host processor can monitor whether
Sync(0x47) is detected or not.
All bits except Slk and Sdr are set when packet is
matched to PID register.
8
Slk Sdr
FIELD
Slk
Sdr
Psc
Ppr
Dai
Cpr
Ooc
Pdf
Esf
Erf
Dtf
Acf
Crf
Pef
Host whenever they are read, and DSP_INT is
deasserted.
Psc
BITS
15
14
13:12
11
10
9
8
7:6
5
4
3
2
1
0
Ppr Dai Cpr Ooc
DESCRIPTION
Sync_lock
Sync_drop
PES_scrambling_control
PES_priority
data_alignment_indicator
copyright
original_or_copy
PTS_DTS_flag
ESCR_flag
ES_rate_flag
DSM_trick_mode_flag
additional_copy_info_flag
PES_CRC_flag
PES_extension_flag
Interrupt Mask 1 (0x004)
7
0
Pdf
Esf Erf
Dtf Acf Crf Pef
VALUES
DEFAULT
Interrupt Mask 2 (0x006)
All bits respectively correspond with each ones in
Interrupt Flag 1 register.
All bits respectively correspond with each ones in
Interrupt Flag 2 register.
1 = Interrupt enabled
1 = Interrupt enabled
17
GDC21D301A
Instruction (0x008)
When error(discontinuity) happens in video packet,
i.e., in case Sec=‘1’, the GDC21D301A inputs
video sequence error code in data output.
In case Aps=‘0’, the GDC21D301A outputs audio
compressed data in parallel mode, and in case
Aps=‘1’, the GDC21D301A outputs the data in
serial mode through AUD_SER_DATA pin.
When Vts is 1, the GDC21D301A inputs PTS and
DTS data before sending them to video packet
according to Pdf flag bit of Interrupt Flag 2
register. When Ucb is 1, the GDC21D301A
15
receives data from channel input.
When Ice is 1, the GDC21D301A ignores channel
empty condition(i.e., the GDC21D301A continues
decoding data in channel buffer whether they were
decoded before or not.).
When Stc is 1, the GDC21D301A loads internal
PCR counter to STC5 register, and then this bit is
cleared automatically. In case Lst is 1, the
GDC21D301A loads internal PCR counter with
new value when next PCR value is loaded in the
packet, and then this bit is cleared automatically.
8
Sec Aps Vts
FIELD
Sec
Aps
BITS
15
14
Vts
Ucb
Ice
Stc
Lst
Den
Ien
13
9
8
3
2
1
0
7
0
Ucb Ice
Stc Lst Den Ien
DESCRIPTION
Sequence_error_code
Audio parallel/serial output
VALUES
1=sequence_error_code inserted
0=parallel
1= serial
1=PTS/DTS inserted
Video PTS,DTS output
Update channel buffer
Ignore channel empty
load STC5
load PCR
Global decoding enable
Global Interrupt enable
DEFAULT
1=decoding enable
1=interrupt enable
Round Buffer (0x00a)
When Rpn is 1, write pointer is reached to end
pointer, and the write pointer is changed to start
15
pointer(i.e., the GDC21D301A overwrites the
following data).
8
7
0
Rp8 Rp7 Rp6 Rp5 Rp4 Rp3 Rp2 Rp1 Rp0
FIELD
Rpn
18
BITS
8:0
DESCRIPTION
Round the buffer of the PSI_n
VALUES
DEFAULT
GDC21D301A
PID Flag 1 (0x00c)
When the GDC21D301A decodes the packet
whose PID is activated for decoding, it sets the
15
P15 P14 P13 P12 P11 P10 P9
FIELD
P15 ~ P3
P2
P1
P0
BITS
15:3
2
1
0
corresponding bit in PID Flag 1, or 2 register.
8
7
P8
P7
DESCRIPTION
PID flag for PSI_15 ~ PSI_3
Auxiliary PID flag
Audio PID flag
Video PID flag
0
P6
P5
P4
P3
VALUES
P2
P1
P0
DEFAULT
PID Flag 2(0x00e)
These bits indicate the type of the packet
which the GDC21D301A is now decoding.
15
8
7
0
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16
FIELD
P31 ~ P16
BITS
15:0
DESCRIPTION
PID flag for PSI_31 ~ PSI_16
VALUES
DEFAULT
APWM control (0x010)
APWM output signal is generated by this value.
External VCXO for audio can be controlled by this
value and the lip synchronization between video
15
and audio clock. The control of this register is the
same as that of VPWM.
8
7
0
APWM
FIELD
APWM
BITS
15:0
DESCRIPTION
Audio PWM control
VALUES
0x0000 to 0xFFFF
DEFAULT
0x7FFF
19
GDC21D301A
VPWM control (0x012)
The chip uses Sigma-delta modulation for VPWM
signal. Modulation clock is 1/34 system
clock(27MHz/34 = 794KHz). VPWM output signal
is generated by this value. When the register value
is 0x7FFF, the period of '1' and the period of '0'
have the same value of 0.630usec, and the cycle
time is 1.259usec, i.e., the duration of VPWM
output signal is 50%. The larger is the value greater
15
than 0x7FFF, the longer is the high period
generated. For example, if register value is 0x0000,
there is no data of '1' in 65536 data. Only the data
of '0' is almost uniformly distributed in 65536 data.
Adjusting PWM pulse, system VCXO can be
controlled to achieve lip synchronization or system
clocks locking.
8
7
0
VPWM
FIELD
VPWM
BITS
15:0
DESCRIPTION
Video PWM control
VALUES
0x0000 to 0xFFFF
DEFAULT
0x7FFF
Sync Hysteresis (0x014)
15
8
7
0
Scd
20
FIELD
Scd
BITS
7:5
Sync Drop
DESCRIPTION
Scl
4:0
Sync Lock
Scl
VALUES
0 = should not be used
1 – 7 = The number of consecutive
sync bytes must be discarded to
constitute a sync drop.
0 = should not be used
1 – 31 = The number of consecutive
sync bytes must be detected
before sync is acquired.
DEFAULT
0x1
0x03
GDC21D301A
PTS (0x02a ~ 0x02e)
PTS Register 1 (0x02a)
PTS Register 2 (0x02c)
PTS Register 3 (0x02e)
These read-only registers hold the PTS value that
GDC21D301A retrieves from the transport packet
whose PID value is activated for decoding.
Current Packet’ s PTS
32
31
16
15
0
15
0
15
PTS 3
0
15
PTS 2
0
PTS 1
DTS (0x030 ~ 0x034)
DTS Register 1 (0x030)
DTS Register 2 (0x032)
DTS Register 3 (0x034)
These read-only registers hold the DTS value that
GDC21D301A retrieves from the transport packet
whose PID value is activated for decoding.
Current Packet’ s DTS
32
31
16
15
0
DTS 3
15
15
0
0
DTS 2
15
0
DTS 1
21
GDC21D301A
PCR (0x036 ~ 0x03c)
PCR Register 1 (0x036)
PCR Register 2 (0x038)
PCR Register 3 (0x03a)
PCR Register 4 (0x03c)
These read-only registers hold the PCR value that
the GDC21D301A retrieves from the transport
packet whose PID value is activated for decoding.
Current Packet’ s PCR_base
32 31
15
PCR_Extension
16 15
0
15
PCR 3
0
0
15
PCR 2
8
0
0
15
PCR 1
9 8
PCR 4
0
Splicing_countdown (0x040)
This
read-only
register
holds
the
splicing_countdown value that the GDC21D301A
15
retrieves from the transport packet whose PID
value is activated for decoding.
8
7
0
Splicing_countdown
22
GDC21D301A
ES_rate (0x042 ~ 0x044)
ES_rate Register 1 (0x042)
ES_rate Register 2 (0x044)
These read-only registers hold the ES_rate value
that the GDC21D301A retrieves from the transport
packet whose PID value is activated for decoding.
Current Packet’ s ES_rate
21
15
6 5
ES_rate 2
15
0
0
15
0
ES_rate 1
DSM_trick_mode (0x046)
This read-only register holds the DSM_trick_mode
field that the GDC21D301A retrieves from the
15
transport packet whose PID value is activated for
decoding.
8
7
0
DSM_trick_mode
Additional_copy_info (0x048)
This
read-only
register
holds
the
additional_copy_info field that the GDC21D301A
15
retrieves from the transport packet whose PID
value is activated for decoding.
8
7
0
Additional_copy_info
23
GDC21D301A
STC1 (0x060 ~ 0x062)
STC1 Register 1 (0x060)
STC1 Register 2 (0x062)
These read-only registers hold the lower 20 bits of
STC value from the internal STC counter of the
GDC21D301A when the GDC21D301A retrieves
the PCR value from the transport packet whose
PID value is activated for decoding. The internal
STC counter is clocked at the frequency of input
on CLOCK_27M pin (nominally 27 MHz). In the
GDC21D301A, STC_Extension is written to
STC1_2[15:7] and can be read by user. STC1 is
also read-only register.
Internal STC counter base
21
15
19
7
6
4
STC1_2
15
3
STC Extension
0
0
8
15
0
STC1_1
STC2 (0x064 ~ 0x066)
STC4 (0x06c ~ 0x06e)
STC2 Register 1 (0x064)
STC2 Register 2 (0x066)
STC4 Register 1 (0x06c)
STC4 Register 2 (0x06e)
These read-only registers hold the lower 20 bits of
STC value from the internal STC counter of the
GDC21D301A when external BOF1 signal is
detected.
These read-only registers hold the lower 20 bits of
STC value from the internal STC counter of the
GDC21D301A when external BOF3 signal is
detected.
STC3 (0x068 ~ 0x06a)
STC5 (0x070 ~ 0x072)
STC3 Register 1 (0x068)
STC3 Register 2 (0x06a)
STC5 Register 1 (0x070)
STC5 Register 2 (0x072)
These read-only registers hold the lower 20 bits of
STC value from the internal STC counter of the
GDC21D301A when external BOF2 signal is
detected.
24
0
These read-only registers hold the lower 20 bits of
STC value from the internal STC counter of the
GDC21D301A when STC fetch instruction is
activated(see Instruction Register).
GDC21D301A
PID Registers (0x400 ~ 0x47e)
These registers should be written with certain
values during initialization phase, because the
values are undefined at first. Video, audio, and
auxiliary packet will be respectively transferred to
VAD_DATA port with VID_STRB, AUD_STRB,
and DATA_STRB signal in case Hig bit in the
register is ‘0’(i.e. High Speed Port has the highest
priority. This is equally applied to other packets.).
Other data will be transferred to the corresponding
buffer in DRAM.
Vid PID Register (0x400, 0x402)
These registers should be written with certain
values during initialization phase, because the
15
values are undefined at first. For correct processing,
Dst should be written to ‘0’.
8
7
0
Den Dst Frm
Field
Den
Dst
Bits
15
14
Frm
13
PID
12:0
PID
Description
PID enable
Decoding state(status reg.)
Values
1 = PID matching enabled
1 = corresponding PID packet
occurred at least once before
0 = transfer PES_payload to
external port
1 = transfer whole PES packet
Decoding Type
PID
These registers should be written with certain
values during initialization phase, because the
15
values are undefined at first.
8
7
0
Hig
Field
Hig
Bits
7
CCNT
3:0
Default
Description
High Speed out enable
Continuity Counter
Aud PID Register (0x404, 0x406)
Same as Vid PID register, but Audio packet
CCNT
Values
1 = transfer whole TS packet to
high speed port
store continuity_counter value
Default
Aux PID Register (0x408, 0x40a)
Same as Vid PID register, but Auxiliary packet
25
GDC21D301A
PSI PID Register (0x40c ~ 0x40e)
Same as Vid PID register, except the following.
Field
Frm
Bits
13
Description
Decoding Type
Values
0 = This packet is a kind of PES.
1 = This packet is a kind of PSI.
Default
In PES packet, there is no pointer_field.
Buffer Pointer Register (0x618 ~ 0x61e)
The values are undefined initially. These values are
the memory management registers for local DRAM.
These are 22-bit wide registers only whose 16 bits
can be accessed by the host.
In the following, N = n-2 and n = 3, 4, 5, ..... , 31.
PSI_n’ s data Buffer Start Pointer Register (0x618 + 4*N)
1) When M16 = ‘ 1’ (16Mbit DRAM used)
When it is ‘Write’, the lower 6 bits are written to
Internal Start Pointer register
6
21
0
15
When ‘ Write’
26
5
15
0
0
When ‘ Read’
GDC21D301A
2) When M16 = ‘ 0’ (4Mbit DRAM used)
When it is ‘Write’, the lower 4 bits and higher 2 bits are written to
Internal Start Pointer register
21
4
20 19
6
21
0
15
When ‘ Write’
3
5
15
0
0
0
When ‘ Read’
27
GDC21D301A
PSI_n’ s data Buffer End Pointer Register (0x61a+ 4*N)
Same as Start pointer register. But the real end
address of data buffer is one less than this register
value, for example, the real end address of PSI_4
data buffer is equal to 0x61b which is calculated by
‘0x61c minus 0x001’. The buffer size is calculated
by the following.
Size = End Pointer - Start Pointer.
PSI_n’ s data Buffer Read Pointer Register (0x61c + 4*N)
Actually this register is not used. In order to read
data in this buffer, you should access local DRAM
directly like accessing internal register.
1) When M16 = ‘ 1’ (16Mbit DRAM used)
,When
and the
value
should
it is
‘Write’,
thebelower 6 bits are written to
located between start
and end pointer. It is recommended that the initial
value is the same of the start pointer. When ‘Read’,
the lower 16 bits are read.
Internal Read Pointer Register
6
21
21
5
0
0
16 15
0
15
15
0
When ‘ Write’
When ‘ Read’
2) When M16 = ‘ 0’ (4Mbit DRAM used)
When it is ‘Write’, the lower 4 bits and higher 2
bits are written to ‘0’, and the value should be
located between start and end pointer. It is
recommended that this initial value is the same of
start pointer value. When ‘Read’, the lower 16 bits
are read.
Internal Read Pointer register
21
21
20 19
4
16 15
When ‘ Write’
0
0
0
15
28
3
15
0
When ‘ Read’
GDC21D301A
PSI_n’ s data Buffer
register (0x61e + 4*N)
Write
Pointer
Auxiliary compressed data buffer pointer
(0x720 ~ 0x726)
Same as Read pointer register. This value should
be located between start and end pointer. It is
recommended that this initial value is the same of
start pointer value. (See Round Buffer register
0x005)
Same as PSI_n’s data buffer pointer register.
This buffer is used to store the data which is sent to
external auxiliary decoder. the GDC21D301A will
read the data from this buffer to send them to
external auxiliary decoder. The read pointer is used
to read data.
Channel buffer pointer (0x700 ~ 0x706)
Same as PSI_n’s data buffer pointer register.
This buffer is used to store FEC input data. the
GDC21D301A will read the data from this buffer
to decode TS packets. The read pointer is used to
read data.
Audio compressed data buffer pointer
(0x708 ~ 0x70e)
Same as PSI_n’s data buffer pointer register.
This buffer is used to store the data which is sent to
external audio decoder. the GDC21D301A will
read the data from this buffer to send them to
external audio decoder. The read pointer is used to
read data.
Audio
PES_extension
pointer(0x710 ~ 0x716)
data
Auxiliary PES_extension
pointer (0x728 ~ 0x72e)
data
buffer
Same as PSI_n’s data buffer pointer register.
This buffer is used to store the PES_extension data
of auxiliary packets. Before storing the
PES_extension data, the GDC21D301A writes the
size of the PES_extension data + stuffing_bytes.
The read pointer is not used by the GDC21D301A.
Transport_private_data
(0x730 ~ 0x736)
buffer
pointer
Same as PSI_n’s data buffer pointer register.
This buffer is used to store transport_private_data
field. The read pointer is not used by the
GDC21D301A.
buffer
Same as PSI_n’s data buffer pointer register.
This buffer is used to store the PES_extension data
of audio packets. Before storing the PES_extension
data, the GDC21D301A writes the size of the
PES_extension data + stuffing_bytes. The read
pointer is not used by the GDC21D301A.
Adf_extension_data
(0x738 ~ 0x73e)
buffer
pointer
Same as PSI_n’s data buffer pointer register.
This buffer is used to store Adf_extension_data
field. The read pointer is not used by the
GDC21D301A.
Video PES_extension data buffer pointer
(0x718 ~ 0x71e)
Same as PSI_n’s data buffer pointer register.
This buffer is used to store the PES_extension data
of video packets. Before storing the PES_extension
data, the GDC21D301A writes the size of the
PES_extension data + stuffing_bytes. The read
pointer is not used by the GDC21D301A.
29
GDC21D301A
7. Electrical Specification
7.1 Absolute Maximum Rating
SYMBOL
VDD
VI
Vo
Tstg
Pd
PARAMETERS
VALUES
Power Supply Voltage
-0.33 to 5.5
Digital Input Voltage
-0.33 to VDD + 0.5
Digital Output Voltage
-0.33 to VDD + 0.5
Storage Temperature
-55 to 125
Power Dissipation
1.0
Note : Absolute Maximum Ratings means that the safety of the device cannot be
guaranteed beyond these values and it doesn’t imply that the device
should be operated within these limits.
UNIT
V
V
V
¡ É
W
7.2 Recommended Operating Range
SYMBOL
VDD
Topr
PARAMETERS
Power Supply Voltage
Operating Temperature
VALUES
3.3 ± 10%
0 to 70
UNIT
V
¡ É
7.3 DC Characteristics (VDD = 3.3 V ± 10%, TA = 0 ~ 70 °C )
SYMBOL
VIH
VIL
VOH
VOL
IDD
IDDQ
Fopr
30
PARAMETERS
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Dynamic Supply Current
Quiescent Supply Current
Max. Operating Frequency
MIN
0.7 X VDD
-0.33
2.4
0
-
MAX
VDD + 0.33
0.2 X VDD
VDD
0.4
150
1
27
UNIT
V
V
V
V
mA
uA
MHz
GDC21D301A
7.4 AC Characteristics (VDD = 3.3 V ± 10%, TA = 0 ~ 70 °C )
7.4.1 Transport Stream Interface Requirements
tFCLKf
tFCLKr
tFCLKp
FEC_CLOCK
tFCLKL
tFECs
tFCLKH
tFECh
FEC_DATA[7:0]
D_VALID
\ERR_BLOCK
PARAMETER
tFECh
tFECs
tFCLKr
tFCLKf
tFCLKH
tFCLKL
tFCLKp
DESCRIPTION
FEC_CLOCK to FEC_DATA hold time
FEC_CLOCK to FEC_DATA setup time
FEC_CLOCK rising time
FEC_CLOCK falling time
FEC_CLOCK high duration
FEC_CLOCK low duration
FEC_CLOCK period
MIN
5
5
10
10
100
TYP
-
MAX
1.5
1.5
-
UNIT
ns
ns
ns
ns
ns
ns
ns
MAX
1.5
1.5
37
18
18
UNIT
ns
ns
ns
ns
ns
ns
ns
7.4.2 Clock Interface Requirements
tCLOCKf
tCLOCKr
tCLOCKp
CLOCK
tCLOCKL
tPWMd
tCLOCKH
tPWMh
VPWM
APWM
PARAMETER
tCLOCKH
tCLOCKL
tCLOCKr
tCLOCKf
tCLOCKp
tPWMD
tPWMH
PARAMETER
CLOCK high duration
CLOCK low duration
CLOCK rising edge
CLOCK falling edge
CLOCK period
PWM delay time
PWM hold time
MIN
10
10
36
-
TYP
-
31
GDC21D301A
7.4.3 Reset Signal Requirement
tRSTw
\RESET
PARAMETER
tRSTw
PARAMETER
RESET pulse width
MIN
tCLOCKp
TYP
-
MAX
-
UNIT
ns
MAX
18
-
UNIT
ns
ns
ns
ns
ns
The low pulse width of reset signal should be larger than tCLCOKp, the operating clock period.
7.4.4 Audio/Video/Data Decoder Interface Requirements
CLOCK
tREQs
VID_REQ
AUD_REQ
DATA_REQ
VAD_DATA[7:0]
tSTRBd
VID_STRB
AUD_STRB
DATA_STRB
PARAMETER
tVADs
tVADh
tSTRBd
tSTRBw
tREQs
32
PARAMETER
VAD data setup time
VAD data hold time
STRB to clock delay time
STRB pulse width
REQ setup time
tSTRBw
tVADs
tVADh
MIN
30
30
30
5
TYP
-
GDC21D301A
7.4.5 Host Processor Interface Requirements
Host Write Mode
DSP_ADDR[22:0]
\DSP_PD
DSP_DATA[15:0]
tHs
tHh
DSP_RWB
tSP
\DSP_STRB
tHRh
DSP_READY
Host Read Mode
DSP_ADDR[22:0]
\DSP_PD
DSP_DATA[15:0]
tHs
tHDOE
tHh tHDh
DSP_RWB
tSP
\DSP_STRB
tHRh
DSP_READY
PARAMETER
tHs
tHh
tHRh
tHDOE
tHDh
tSP
PARAMETER
Host setup time
Host hold time
HREADY hold time
Host data output enabled
Host data hold time
Strobe precharge time
MIN
0
0
0
2
37
TYP
-
MAX
37
-
UNIT
ns
ns
ns
ns
ns
ns
33
GDC21D301A
8. Package Mechanical Data
8.1 Package Pin out
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
34
TYPE
I/O
I/O
I/O
GND
O
O
PWR
O
O
PWR
O
O
O
O
GND
I
I
I
I
I
I
I
I
GND
I
I
I
I
I
I
I
I
PWR
GND
I
I
I
I
I
I
I
I
I
NAME
DSP_DATA[13]
DSP_DATA[14]
DSP_DATA[15]
VSS
DSP_INT
DSP_READY
VDD
TDO0
TDO1
VDD
HSDEN
HIGH_SP_DATA[1]
HIGH_SP_DATA[0]
CLOCK_OUT
VSS
TA[7]
TA[6]
TA[5]
TA[4]
TA[3]
TA[2]
TA[1]
TA[0]
VSS
TWEB
TEST
TDI
P_S_MODE
F_START
FEC_DATA[7]
FEC_DATA[6]
FEC_CLOCK
VDD
NC
VSS
FEC_DATA[5]
FEC_DATA[4]
FEC_DATA[3]
FEC_DATA[2]
FEC_DATA[1]
FEC_DATA[0]
\ERR_BLOCK
D_VALID
SCAN_MODE / TA[8]
PIN
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
TYPE
I
I
I
PWR
O
O
O
O
GND
O
O
O
O
PWR
O
O
O
O
GND
O
O
O
I/O
PWR
I
PWR
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
PWR
I/O
I/O
I/O
I/O
GND
I/O
NAME
SCAN_TEST
SCAN_IN1 / TA[9]
M16
VDD
DRAM_RWB
DRAM_ROW_COL_ADDR[9]
DRAM_ROW_COL_ADDR[8]
DRAM_ROW_COL_ADDR[7]
VSS
DRAM_ROW_COL_ADDR[6]
DRAM_ROW_COL_ADDR[5]
DRAM_ROW_COL_ADDR[4]
DRAM_ROW_COL_ADDR[3]
VDD
DRAM_ROW_COL_ADDR[2]
DRAM_ROW_COL_ADDR[1]
DRAM_ROW_COL_ADDR[0]
\DRAM_RAS1
VSS
\DRAM_RAS0
\DRAM_CAS1
\DRAM_CAS0
DRAM_DATA[15]
VDD
CLOCK_27M
VDD
NC
VSS
DRAM_DATA[14]
DRAM_DATA[13]
DRAM_DATA[12]
DRAM_DATA[11]
VSS
DRAM_DATA[10]
DRAM_DATA[9]
DRAM_DATA[8]
DRAM_DATA[7]
VDD
DRAM_DATA[6]
DRAM_DATA[5]
DRAM_DATA[4]
DRAM_DATA[3]
VSS
DRAM_DATA[2]
GDC21D301A
Package Pin out (continued)
PIN
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
TYPE
I/O
I/O
I
I
I
I
I
I
I
I
I
PWR
O
GND
O
O
O
GND
O
O
O
I/O
O
I
PWR
I/O
I/O
I/O
I/O
GND
I/O
I/O
PWR
I/O
O
PWR
O
O
I
I
I
GND
-
NAME
DRAM_DATA[1]
DRAM_DATA[0]
\DATA_WAIT
\DATA_REQ
\AUD_WAIT
\AUD_REQ
\VID_WAIT
\VID_REQ
BOF_D
BOF_A
BOF_V
VDD
APWM
VSS
\AUD_DCS
AUD_SER_DATA
\AUD_STRB
VSS
\DATA_DCS
\DATA_STRB
PTS_DTS_STRB
VAD_DATA[7]
SCAN_OUT1
\RESET
VDD
VAD_DATA[6]
VAD_DATA[5]
VAD_DATA[4]
VAD_DATA[3]
VSS
VAD_DATA[2]
VAD_DATA[1]
VDD
VAD_DATA[0]
\VID_DCS
VDD
\VID_STRB
VPWM
\DSP_STRB
DSP_RWB
\DSP_PD
VSS
NC
NC
PIN
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
TYPE
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PWR
GND
I/O
I/O
I/O
I/O
PWR
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
PWR
I/O
NAME
DSP_ADDR[22]
DSP_ADDR[21]
DSP_ADDR[20]
DSP_ADDR[19]
DSP_ADDR[18]
DSP_ADDR[17]
DSP_ADDR[16]
DSP_ADDR[15]
DSP_ADDR[14]
DSP_ADDR[13]
DSP_ADDR[12]
DSP_ADDR[11]
DSP_ADDR[10]
DSP_ADDR[9]
DSP_ADDR[8]
DSP_ADDR[7]
DSP_ADDR[6]
DSP_ADDR[5]
DSP_ADDR[4]
DSP_ADDR[3]
DSP_ADDR[2]
DSP_ADDR[1]
DSP_ADDR [0]
BIT8MODE
CLOCK
VDD
NC
VSS
DSP_DATA[0]
DSP_DATA[1]
DSP_DATA[2]
DSP_DATA[3]
VDD
DSP_DATA[4]
DSP_DATA[5]
DSP_DATA[6]
DSP_DATA[7]
VSS
DSP_DATA[8]
DSP_DATA[9]
DSP_DATA[10]
DSP_DATA[11]
VDD
DSP_DATA[12]
35
GDC21D301A
8.2 Package Dimensions
Package Type : 176 Pin Thin Quad Flat Package
24x24 mm BODY, 1.4 mm THICK
Figure 4. Physical Dimensions
36