2399_Wirespeed 11/3/02 8:59 PM Page 2 Wirespeed Communication Solutions Framers • PHYs • Network Coprocessors • NSEs • NoBL™ SRAMs • Precision Clocks • QuadPort ™ DSEs • Specialty Memories PERSONAL ACCESS ENTERPRISE METRO CORE 2399_Wirespeed 11/3/02 8:59 PM Page 3 Data Over SONET/SDH Enabling the Next-Generation Metropolitan Area Network Communications systems continue to revolutionize the way we conduct our lives, both personally and professionally. With the continued growth of the Internet, specialized silicon-based solutions are necessary to provide reliable, state-of-theart network infrastructure equipment. The demand for bandwidth, types of new services, and number of new network users all continue to grow. There is growth in new data and telecom services such as remote storage, video conferencing, video training, and voice over IP. Coupled with consistent growth in bandwidth and users, these services place increasing demands on carriers and ISPs attempting to build a robust Metropolitan Area Network. The need to transport multiple services over existing SONET infrastructure requires the type of flexibility and efficiency only Cypress’s multi-protocol based solutions can offer. Cypress enables system vendors to meet their market demands by providing complete 10 Gbps solutions. Along with state-of-the-art physical layer devices, Cypress offers world-class transport solutions. To address the increasing complexity and bandwidth requirements of these communications systems, Cypress offers a comprehensive portfolio of highperformance solutions. Cypress’s broad product portfolio offers wirespeed solutions across the entire linecard. Port PHYs and framers optimize high-speed transmissions over SONET/SDH; Network Search Engines (NSEs) and coprocessors enable highperformance packet processing; and flexible PHY and backplane management solutions continue to drive highperformance serial backplanes. Cypress solutions are instrumental in enabling datapath connections from last mile to first mile. 2 10GbE LINE CARD Additional Services LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD OC-192 LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD Increased Bandwidth Metropolitan Area Network LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD LINE CARD Multi-protocol Support GbE, FC, ESCON, DVB 2399_Wirespeed 11/3/02 8:59 PM Page 4 Network Search Engine (NSE) Increased Bandwidth: OC-192/STM-64/10GbE Linecard POSIC ™ Framer Family Optical Module 10GbE WAN 10G SERDES OC-192/STM-64/10GbE SERDES • Supports OC-192/STM-64 and 10GbE • Low power • World-class jitter performance POSIC10G™ Framer III™ HOTLink Transceiver NPU POSIC10G Framer • 10GbE LAN PHY, 10GbE WAN PHY, OC-192c/STM-64 • Supports 20km round-trip delay • 10GbE MAC Packet Switch Fabric HOTLink III Transceiver • 2.5–3.2 Gbps • Supports XAUI, XGMII, and Infiniband • K28.5 (Comma) and A1/A2 framing Version Part # Standards Features 10GVC CY7C9546 VC, POS/GFP 10G CY7C9547 Quad OC-48,OC-192 STM-64,10GbE OC-192c/STM-64, 10GbE 10GLAN CY7C9548 10GbE LAN PHY 2GVC CY7C9536 2G CY7C9537 OC-48/STM-16, Quad OC-12, 16xOC-3 OC-48/STM-16 Quad OC-12, 16xOC-3 VC, POS/GFP/ ATM POS/GFP/ATM WAN SERDES Family Data Rate (Gbps) 9.9–10.7 GbE ESCON HOTLink Transceiver Link Layer Device POSIC2GVC™ Framer OC-48/STM-16 SERDES DVB HOTLink II Transceiver • 200Mbps–1.5 Gbps data rate • Independent channels support multiple protocols • Programmable version with 100K logic gates available POSIC2GVC Framer • Virtual concatenation (VC) allows efficient transport of multiple protocols over SONET • GFP & HDLC allow flexible mapping of data • 16 VC channels programmable in increments of STS-1 Standards CYS100G01xxDX OC-192/STM-64 Parallel Interface 16-bit LVDS SFI4.1, XSBI 16-bit, HSTL LVPECL 2.5 CYS25G0102DX OC-48/STM-16 2.5 CYS25G0101DX OC-48/STM-16 16-bit, HSTL LVPECL 2.5 CYS25G01K100 OC-48/STM-16 Prog. I/Os Data Rate (Gbps) II™ Part # HOTLink® LAN/SAN PHY Family Multi-protocol Support: Multi-protocol OC-48/STM-16 Linecard FC POS TDM Switch Fabric 9.9–10.7 Part # Standards CYP100G01xxDX 10GbE, 10xFC 1.0–3.4 CYP34G04xxDX XAUI, 1-2xFC, GbE, Infiniband 2.5–3.2 # of Channels 1 4 CYP32G04xxDX XAUI, Infiniband 4 0.2–1.5 CYP15GxxxxDX ESCON, GbE, 1xFC 1, 2, 4 0.2–1.5 CY15G04K100 ESCON, GbE, 1xFC 4 OC-48/STM-16 SERDES • Smallest, lowest-power 16-bit OC-48/STM-16 SERDES • Seamless interface to POSIC2GVC and POSIC2G™ framers • Full Telcordia/ITU-T jitter compliance 3 2399_Wirespeed 11/3/02 8:59 PM Page 5 Solving the Search Problem Wirespeed Packet Processing As Internet usage, line rates and traffic complexity increase, transmission bottlenecks are emerging, particularly in the packet processing section of the networking linecard. From the core to the edge, simple packet processing no longer provides a universal solution. Increasingly, designers require deep-packet processing solutions capable of resolving challenging, policy-oriented Class of Service (CoS) and Quality of Service (QoS) issues. They are moving away from simple, software-based solutions in favor of intelligent search architectures customized to address the requirements of specific applications. In short, a packet processing revolution is underway. Cypress is driving that revolution. Leading the way are new generations of network search engines (NSEs) and network coprocessors compatible with industry leading NPUs and ASICs. Cypress is committed to developing highperformance, large-entry search solutions that enable packet forwarding, policy resolution, and netflow tracking. Cypress’s portfolio of deterministic, deep-packet and algorithmic solutions meet the needs of next-generation system designers and set the standard for packet processing innovation. What’s driving the need for new search solutions? Additional Services • Multiple lookups per packet • Greater search complexity Increased Bandwidth • Faster line rates Data Packet Increased users • Larger tables Sahasra™ NSE—“Thousands” or “Infinite”. Sahasra provides the largest number of entries, nearly an infinite number, to support very large forwarding tables. Vichara™ Network Coprocessor —“Continued Thought”. Vichara provides additional intelligence to perform complex, deep-packet searches. 4 NPU/ASIC Modified Data Packet Cypress Search Subsystem: • Coprocessors • NSEs • Networking SRAMs Packet Processing Requirements: Parse Policy Resolution Route Modify Cypress Search Solutions • Fast, deterministic search results • Large tables in a single device • Low power solutions • Multilayer search capability Cypress Search Families Cypress’s NSE family names are based on the ancient language of Sanskrit. Ayama™ NSE—“Extension”. The Ayama family extends the performance, density, power management, and table management of Cypress’s market leading NSE 70000 family. Packet Processing Size ROUTE POLICY NSE 70000 Ayama™ NSE Sahasra™ NSE NSE 70000 Ayama™ NSE Ayama™ NSE and Vichara™ Coprocessor Complexity Schedule/ Queue 2399_Wirespeed 11/3/02 8:59 PM Page 6 Network Search Engine (NSE) Data Packet ASIC Modified Data Packet NoBL™ NSE 70000 SRAM NSE 70000 Family • Broad line of densities (32K, 64K, 128K, 256K IPv4 entries) • Performance up to 100 million searches per second (MSPS) • Full-bit ternary masking • Footprint-compatible with the Ayama 10000 NSEs • Cascade up to 31 devices NSE 70000 Family IPv4 Entries Density Performance CYNSE70032 32K 1 Mbit 83 MSPS CYNSE70064 64K 2 Mbits 83 MSPS CYNSE70128 128K 4 Mbits 100 MSPS CYNSE70256 256K 9 Mbits 83 MSPS IPv4 Entries Density Performance CYNSE10128 128K 4 Mbits 266 MSPS CYNSE10256 256K 9 Mbits 266 MSPS CYNSE10512 512K 18 Mbits 266 MSPS IPv4 Entries Density Performance CYNSE20128 128K 4 Mbits 266 MSPS CYNSE20256 256K 9 Mbits 266 MSPS CYNSE20512 512K 18 Mbits 266 MSPS Part # Ayama Family Ayama 10000 Data Packet NPU/ASIC Modified Data Packet Ayama™ NSE Data Packet NoBL™ SRAM NPU/ASIC Ayama™ NSE Modified Data Packet Sahasra™ NSE • • • • • Densities of 128K, 256K and 512K IPv4 entries Highest performance at 266 MSPS Lowest power with unique Mini-Key™ power management feature Configurable table widths within a single device (x36/72/144/288/576) Parity to detect errors in the NSE core and across the data bus Ayama 20000 • Glueless interface to IBM, Intel, AMCC, and all processors with LA-1 and XSC interfaces • Interface up to 4 NPUs to a single Ayama 20000 device • Parity error detection, Soft Priority™, and Mini-Key features Sahasra Forwarding NSE • Supports searches with density >1 million entries • Deterministic results • Unique high-performance, low power search solution • Larger tables through cascading • Lowest power per route • Advanced software suite Ayama™ 10000 Family Part # Ayama™ 20000 Family Part # Sahasra™ 50000 IPv4 Entries Part # CYNSE50000 NPU NoBL™ SRAM NPU NPU Vichara™ Coprocessor NPU CPU Vichara Coprocessor • Manages multiple searches for the NPU eliminating bus bottlenecks • Interface up to 4 NPUs to a single Vichara 81000 • Search key extraction and support for conditional branching operations • Aging, policing, and flow statistics • Glueless interface to IBM, Intel, AMCC, and all processors with LA-1 and XSC interfaces > 1M Performance > 200 MSPS Vichara™ 81000 Part # CYNCP81000 NPU Interface 4 LA-1; 4 XSC Features Recursive Search, Conditional Branch Operations, Aging, Policing, and Flow Statistics Ayama™ 10000 NSE 5 2399_Wirespeed 11/3/02 8:59 PM Page 7 Cypress Backplane Solutions—The Ultimate in Flexibility Backplanes Made Easy Backplane designers can count on two things: increasing port speed and increasing port density. Both of these require more data throughput and higher performance in the backplane. More and more backplane designs are taking advantage of low-noise, scalable serial links to enable high-performance backplanes. As a pioneer in serial backplanes, Cypress has continued to be an innovation leader. What do next generation backplanes require? • Increased bandwidth • Scalability • Frequency agility • Innovative managment Today, Cypress’s flexible physical layer and backplane management solutions mean designing serial backplanes has never been easier. Each Cypress family offers unparalled flexibility. Whether it is over 3 Gbps of frequency agility in the HOTLink® family, programmable skew timing in the RoboClock® family, high-performance programmable logic in the Delta 39K™ CPLDs, or data buffering flexibility in the QuadPort Datapath Switching Element (QuadPort™ DSE) device, Cypress has the backplane solution. ® HOTLink Backplane Family Data Rate (Gbps) 1.0–3.4 2.5–3.2 0.2–1.5 0.2–1.5 Part # Features <100mW/channel CYP34G04xxDX B1 Monitoring 8b/10B Encoding CYP32G04xxDX A1/A1 Framing 8b/10B Encoding CYP15GxxxxDX Channel Bonding CYP15G04K100 Programmable # of Channels 4 1.0–3.4 Gbps SONET Backplane • Ultra-low power (<100 mW per channel) • A1/A2 framing, B1 monitoring • Programmable pre-emphasis • Programmable output levels Clock Mgmt HOTLink III™ Transceiver TDM Switch Fabric 4 x 3.4 Gbps 4 1, 2, 4 4 2.5–3.2 Gbps Backplane • Frequency Agile • XAUI compatible • 8B/10B bypassable encoding • K28.5, and A1/A2 framing 200 Mbps–1.5 Gbps Backplane • Multichannel bonding • Frequency independent channels • 100K gates of logic • 8B/10B bypassable encoding 6 Logic/Memory Logic/Memory Clock Mgmt Logic/Memory Clock Mgmt Packet Switch Fabric HOTLink III™ Transceiver 4 x 3.2 Gbps Packet Switch Fabric HOTLink II™ Transceiver 4 x 1.5 Gbps 2399_Wirespeed 11/3/02 9:00 PM Page 8 Network Search Engine (NSE) Backplane Management Data QuadPort DSE ™ QuadPort™ DSE Family PHY Data ® HOTLink Transceiver Part # Density Config. CY7C0452 5 Mbits 128K x 40 167 676 BGA (27 x 27) CY7C0451 2 Mbits 64K x 40 167 676 BGA (27 x 27) CY7C0431 128K x 20 167 676 BGA (27 x 27) CY7C0430 2 Mbits 1 Mbit 64K x 18 133 272 BGA (27 x 27) CY7C04312 1/2 Mbit 32K x 18 133 272 BGA (27 x 27) CY7C04314 1/4 Mbit 16K x 18 133 272 BGA (27 x 27) Density Config. Freq. Packages CY7C0853 9 Mbits CY7C0852 4 Mbits 256K x 36 128K x 36 150 167 CY7C0851 2 Mbits 64K x 36 167 CY7C0832 4 Mbits 256K x 18 167 172 BGA (15 x 15) 172 BGA (15 x 15) 176 TQFP (24 x 24) 172 TQFP (15 x 15) 176 TQFP (24 x 24) 120 TQFP (14 x 14) CY7C0831 2 Mbits 128K x 18 167 120 TQFP (14 x 14) Freq. Packages Freq. Packages Dual-Port Family Part # Control Delta39K ™ CPLD ® RoboClock Timing FIFO Family Memory Solutions Cypress supports a full portfolio of memory solutions, offering a broad selection of performance, features, and design flexibility. QuadPort™ DSE • Allows innovative system design • Densities up to 5 Mbits • 4 ports up to 167MHz Dual-Port RAMs • Densities up to 9 Mbits • Speeds up to 167MHz • Supports burst counters FIFOs • Densities up to 5 Mbits • Speeds up to 200MHz • Bus matching for flexibility Flexible Timing Broadest portfolio of high-performance clock distribution products. RoboClock® Timing • Programmable output skew per bank • Programmable divide/multiply per bank • 18 outputs up to 200MHz ComLink™ Buffers • Differential to LVPECL/LVDS buffers • Up to 650MHz single-ended outputs • Up to 350MHz differential outputs Zero Delay, Non-ZDB Buffers • Split 2.5V/3.3V outputs • Up to 21 outputs at 200MHz • Motorola alternate solutions Programmable Logic Cypress has the highest-density CPLDs, up to 200K gates of logic. Delta39K™ CPLDs • Up to 200K gates • Most integrated memory • Highest number of I/Os • Self-boot support • Deterministic timing Quantum38K™ CPLDs • Easy migration to Delta39K • Up to 100K gates • Pin-compatible footprints Ultra37000™ CPLDs • Speeds up to 200MHz • In-System Reprogrammable™ (ISR™) Part # Density Config. CY7C4808 5 Mbits CY7C4806 1 Mbit 64K x 80 16K x 80 200 200 288 BGA (19 x 19) 288 BGA (19 x 19) CY7C43684 1 Mbit 16K x 36 x2 133 128 TQFP (14 x 20) CY7C43683 1/2 Mbit 16K x 36 133 128 TQFP (14 x 20) Delta39K ™ Family Device Typ. Gates 39K200 39K165 39K100 39K50 39K30 92K–288K 77K–241K 46K–144K 23K–72K 16K–48K Macro 3072 2560 1536 768 512 RAM (Kb) fMAX2 (MHz) 480 400 240 120 80 181 181 222 233 233 Quantum38K ™ Family Device Typ. Gates 38K100 38K50 38K30 46K–144K 23K–72K 16K–48K Macro 1536 768 512 RAM (Kb) fMAX2 (MHz) 48 24 16 125 125 125 7 2399_Wirespeed 11/3/02 9:00 PM Page 9 Timing Solutions SRAM Solutions Cypress offers the largest portfolio of clock distribution solutions including Zero Delay Buffers (ZDBs); highperformance, non-zero-delay buffers; and RoboClock® programmable skew buffers. RoboClock skew buffers provide the flexibility and reliability needed in complex communications systems through programmability and redundancy. In addition, the ComLink™ family includes multiplexed, differential line drivers that provide redundant links for serial backplanes, three-state buffers, and clock distribution. Typical Backplane Timing Distribution PTG RoboClock® Prog. Skew ComLink™ Buffers Standard ZDBs Standard Buffers CPU NoBL™ (No Bus Latency™) synchronous SRAMs optimize the most demanding high-speed applications requiring maximum bandwidth by eliminating latency when transitioning between read and write operations. 72-Mbit NoBL SRAM Part # Config. Power I/Os Frequencies CY7C1470V33 CY7C1470V25 CY7C1472V33 CY7C1472V25 CY7C1474V25 2M x 36 2M x 36 4M x 18 4M x 18 1M x 72 3.3V 2.5V 3.3V 2.5V 2.5V 3.3V, 2.5V 2.5V 3.3V, 2.5V 2.5V 2.5V 250, 200, 167 250, 200, 167 250, 200, 167 250, 200, 167 250, 200, 167 Power I/Os Frequencies 3.3V 2.5V 3.3V 2.5V 2.5V 3.3V, 2.5V 2.5V 3.3V, 2.5V 2.5V 2.5V 250, 200, 167 250, 200, 167 250, 200, 167 250, 200, 167 250, 200, 167 36-Mbit NoBL SRAM Clock Bus Backplane Clock Bus Part # ASIC MEMORY ComLink Buffers SERDES ComLink Switches ™ ComLink Family Part # Outputs Freq. Output Voltage CY2CC910 CY2DP814/8 CY2DL814/8 CY2LL8422/23 CY23020-1 10 4/8 4/8 4 20 650MHz 350MHz 350MHz 350MHz 200MHz LVCMOS LVPECL LVDS LVDS LVCMOS 1.8V 3.3V 3.3V 3.3V 2.5V, 3.3V Outputs Freq. Output Voltage 10 18 8 8 200MHz 200MHz 200MHz 200MHz LVCMOS LVCMOS LVCMOS LVCMOS 3.3V 3.3V 2.5 2.5 RoboClock ® Family Part # CY7B9945V CY7B994V CY7B995 CY7B9950 Config. CY7C1460 1M x 36 CY7C1460V25 1M x 36 CY7C1462 2M x 18 CY7C1462V25 2M x 18 CY7C1464V25 512K x 72 18-Mbit NoBL SRAM Part # Config. Power I/Os Frequencies CY7C1370B/C CY7C1370B/CV25 CY7C1372B/C CY7C1372B/CV25 512K x 36 512K x 36 1M x 18 1M x 18 3.3V 2.5V 3.3V 2.5V 3.3V, 2.5V 2.5V 3.3V, 2.5V 2.5V 250, 200, 167 250, 200, 167 250, 200, 167 250, 200, 167 9-Mbit NoBL SRAM Part # CCY7C1354A/B CY7C1354/BV25 CY7C1356A/B CY7C1356/BV25 Config. Power I/Os Frequencies 256K x 36 256K x 36 512K x 18 512K x 18 3.3V 2.5V 3.3V 2.5V 3.3V, 2.5V 2.5V 3.3V, 2.5V 2.5V 250, 200, 167, 133 250, 200, 167, 133 250, 200, 167, 133 250, 200, 167, 133 4-Mbit NoBL SRAM Part # CY7C1350B/C CY7C1352B/C Config. Power I/Os Frequencies 128K x 36 256K x 18 3.3V 3.3V 3.3V 3.3V 143, 133, 100 143, 133, 100 2399_Wirespeed 11/3/02 8:59 PM Page 1 Corporate Headquarters Cypress Semiconductor 3901 North First Street San Jose, CA 95134 Tel (800) 858-1810 (toll free in U.S.) Press “1” to reach your local sales rep Direct: (408) 943-2600 Fax (408) 943-6848 http://www.cypress.com Connecting From Last Mile To First Mile.™ Europe Headquarters Cypress Semiconductor Intl. Waterloo Office Park, Bldg. C Dreve Richelle 161 Waterloo, Belgium 1410 Tel.: (32) 2-357-0220 FAX: (32) 2-357-0230 Asia Headquarters Cypress Semiconductor 541 Orchard Road #07-02 Liat Towers Singapore 238881 Tel.: (65) 735-0338 FAX: (65) 735-0228 Japan Headquarters Nihon Cypress K.K. Harmony Tower 17F 1-32-2 Hon-Cho Nakano-ku, Tokyo 164-0012 Tel.: (81) 3-5371-1921 FAX: (81) 3-5371-1955 Cypress (w/logo), HOTLink, and RoboClock are registered trademarks of Cypress Semiconductor Corporation. Ayama, ComLink, Connecting From Last Mile To First Mile, Delta39K, HOTLink II, HOTLink III, In-System Reprogrammable, ISR, Mini-Key, NoBL, POSIC, POSIC2GVC, POSIC10G, QuadPort, Quantum38K, Sahasra, Soft Priority, Vichara, and Ultra37000 are trademarks of Cypress Semiconductor Corporation. The names of any other products or services mentioned herein are for identification purposes only and may be trademarks, registered trademarks, or service marks of or copyrighted by their respective holders. Cypress Semiconductor Corporation assumes no responsibility for customer product design and assumes no responsibility for infringement of patents or rights of others that may result from Cypress’s assistance and no product licenses are implied. © Copyright 2002 Cypress Semiconductor Corporation. All rights reserved. 2–0702COMMS