The IR1210 part number has Data Sheet No. PD60165-C been updated and changed to IR4426/IR4427/IR4428 Please see new data sheet IR1210 DUAL LOW SIDE DRIVER Features • Gate drive supply range from 6 to 20V • CMOS Schmitt-triggered inputs with pull-up • Matched propagation delay for both channels • Outputs out of phase with inputs Description The IR1210 is a low voltage, high speed power MOSFET and IGBT driver. Proprietary latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays between two channels are matched. Product Summary IO+/- 1.5A / 1.5A VOUT 6V - 20V ton/off (typ.) 85 & 65 ns Package 8 Lead SOIC Block Diagram 1 INA 2 3 INB 4 NC NC INA OUTA IR1210 GND INB Vs OUTB 8 7 TO LOAD 6 5 ADVANCED INFORMATION IR1210 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. -0.3 25 Units VS Fixed supply voltage VO Output voltage VIN Logic input voltage (INA/N & INB/N) -0.3 VS + 0.3 PD Package power dissipation @ TA ≤ +25°C — 0.625 W °C/W RthJA -0.3 V VS + 0.3 Thermal resistance, junction to ambient — 200 TJ Junction temperature — 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 °C Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND. Symbol Min. Max. VS Definition Fixed supply oltage 6 20 VO Output voltage 0 VS VIN Logic input voltage (INA/N & INB/N) TA Ambient temperature 0 VS -40 125 Units V °C DC Electrical Characteristics VBIAS (VS) = 15V, TA = 25°C unless otherwise specified. The VIN, and IIN parameters are referenced to GND and are applicable to input leads: INA/N and INB/N. The VO and IO parameters are referenced to GND and are applicable to the output leads: OUTA and OUTB. Symbol Definition VIH Logic “0” input voltage (OUT=LO) VIL Min. Typ. Max. Units Test Conditions 2.7 — — Logic “1” input voltage (OUT=HI) — — 0.8 VOH High level output voltage, VBIAS -VO — — 1.2 VOL Low level output voltage, VO — — 0.1 V IIN+ Logic “1” input bias current (OUT=HI) — 5 15 IIN- Logic “0” input bias current (OUT=LO) — -10 -30 VIN = 0V IQS Quiescent Vs supply current — 100 200 VIN = 0V or VS IO+ Output high short circuit pulsed current 1.5 2.3 — VO = 0V, VIN = 0 PW ≤ 10 µs IO- Output low short circuit pulsed current 1.5 3.3 — µA A VIN = VS VO = 15V, VIN = VS PW ≤ 10 µs 2 www.irf.com ADVANCED INFORMATION IR1210 Dynamic Electrical Characteristics VBIAS (VS) = 15V, CL = 1000 pF, TA = 25°C unless otherwise specified. Symbol td1 td2 tr tf Definition Min. Typ. Max. Units Test Conditions Turn-on propagation delay — 85 160 Turn-off propagation delay — 65 150 Turn-on rise time — 15 35 Turn-off fall time — 10 25 figures 2 & 3 ns Functional Block Diagram 5V Vs INA PREDRV OUTA DRV 5V Vs INB PREDRV OUTB DRV GND Lead Assignment and Definitions Symbol Description VS Supply voltage GND Ground INA Logic input for gate driver output (OUTA), out of phase INB Logic input for gate driver output (OUTB), out of phase GND OUTA Gate drive output A INB OUTB Gate drive output B www.irf.com INA OUTA VS OUTB 3 IR1210 ADVANCED INFORMATION 8 Lead SOIC 4 01-0021 08 www.irf.com ADVANCED INFORMATION 50% INA INA IR1210 50% INB INB t d1 OUTA OUTA OUTB OUTB t d2 tr 90% 10% Figure 1. Timing Diagram tf 90% 10% Figure 2. Switching Time Waveforms V S = 15V 6 4.7UF 0.1UF 7 2 INA OUTA C L = 1000PF 4 INB 5 OUTB C L = 1000PF 3 Figure 3. Switching Time Test Circuit WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. www.irf.com 12/20/2000 5