IRF FA38SA50LC

PD - 91615B
FA38SA50LC
HEXFET® Power MOSFET
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Fully Isolated Package
Easy to Use and Parallel
Low On-Resistance
Dynamic dv/dt Rating
Fully Avalanche Rated
Simple Drive Requirements
Low Drain to Case Capacitance
Low Internal Inductance
D
VDSS = 500V
RDS(on) = 0.13Ω
G
ID = 38A
S
Description
Third Generation HEXFETs from International Rectifier
provide the designer with the best combination of fast
switching, ruggedized device design, low on-resistance
and cost-effectiveness.
The SOT-227 package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 500 watts. The low thermal
resistance of the SOT-227 contribute to its wide acceptance
throughout the industry.
S O T -2 2 7
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
VISO
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Insulation Withstand Voltage (AC-RMS)
Mounting torque, M4 srew
38
24
150
500
4.0
± 20
580
38
50
16
-55 to + 150
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
2.5
(1.3N•M)
kV
Thermal Resistance
Parameter
RθJC
RθCS
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Typ.
Max.
Units
–––
0.05
0.25
–––
°C/W
1
2/2/99
FA38SA50LC
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ls
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Min.
500
–––
–––
2.0
22
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
IDSS
Drain-to-Source Leakage Current
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Typ.
–––
0.66
–––
–––
–––
–––
–––
–––
–––
280
37
150
42
340
200
330
5.0
Max. Units
Conditions
–––
V
VGS = 0V, ID = 1.0mA
––– V/°C Reference to 25°C, ID = 1mA
0.13
Ω
VGS = 10V, ID = 23A „
4.0
V
VDS = VGS, ID = 250µA
–––
S
VDS = 25V, ID = 23A
50
VDS = 500V, VGS = 0V
µA
500
VDS = 400V, VGS = 0V, TJ = 125°C
200
VGS = 20V
nA
-200
VGS = -20V
420
ID = 38A
55
nC
VDS = 400V
220
VGS = 10V, See Fig. 6 and 13 „
–––
VDD = 250V
–––
ID = 38A
ns
–––
RG = 10Ω (Internal)
–––
RD = 8Ω, See Fig. 10 „
–––
nH Between lead,
and center of die contact
6900 –––
VGS = 0V
1600 –––
pF
VDS = 25V
580 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
MOSFET symbol
38
––– –––
showing the
A
integral reverse
––– ––– 150
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 38A, VGS = 0V „
––– 830 1300
ns
TJ = 25°C, IF = 38A
––– 15
22
µC di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
‚ Starting TJ = 25°C, L = 0.80mH
ƒ ISD ≤ 38A, di/dt ≤ 410A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
RG = 25Ω, IAS = 38A. (See Figure 12)
2
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FA38SA50LC
1000
1000
VGS
1 5V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
B OT T O M 4.5V
100
10
4.5V
1
10
100
4.5V
20µ s P U LS E W ID TH
T C = 25°C
1
A
1
100
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
3.0
100
TJ = 150 ° C
TJ = 25 ° C
10
V DS = 50V
20µs PULSE WIDTH
5
6
7
Fig 3. Typical Transfer Characteristics
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100
Fig 2. Typical Output Characteristics
1000
VGS , Gate-to-Source Voltage (V)
10
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1
20µs PULSE WIDTH
TJ = 150 °C
10
VD S , Drain-to-So urce V oltage (V )
4
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
TOP
8
ID = 38A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
FA38SA50LC
16000
20
14000
VGS , Gate-to-Source Voltage (V)
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
12000
10000
Ciss
8000
6000
Coss
4000
Crss
2000
ID = 38A
VDS = 400V
VDS = 250V
VDS = 100V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
1
10
0
100
80
160
240
320
400
QG , Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
I D , Drain Current (A)
100
100
TJ = 150 ° C
10
TJ = 25 ° C
10us
100us
10
1
0.1
0.2
1ms
V GS = 0 V
0.4
0.6
0.8
1.0
1.2
1.4
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
TC = 25 °C
TJ = 150 ° C
Single Pulse
1
1.6
1
10
10ms
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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FA38SA50LC
10V
VGS
QGS
RD
VDS
QG
QGD
D.U.T.
RG
+
- VDD
VG
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Charge
Fig 9a. Basic Gate Charge Waveform
Fig 10a. Switching Time Test Circuit
Current Regulator
Same Type as D.U.T.
VDS
90%
50KΩ
.2µF
12V
.3µF
D.U.T.
+
V
- DS
10%
VGS
VGS
td(on)
3mA
IG
tr
t d(off)
tf
ID
Current Sampling Resistors
Fig 9b. Gate Charge Test Circuit
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
0.50
0.1
0.01
0.20
0.10
0.05
0.02
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
FA38SA50LC
EAS , Single Pulse Avalanche Energy (mJ)
1200
1 5V
TOP
1000
L
VDS
D .U .T
RG
IA S
20 V
D RIV E R
+
- VD D
0 .01 Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp
A
BOTTOM
ID
17A
24A
38A
800
600
400
200
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
6
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FA38SA50LC
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

•
•
•
•
RG
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D=
Period
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 13. For N-Channel HEXFETS
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7
FA38SA50LC
SOT-227 Package Details
3 8 .3 0 ( 1.5 08 )
3 7 .8 0 ( 1.4 88 )
4 .4 0 (.17 3 )
4 .2 0 (.16 5 )
C HAM FER
2 .0 0 ( .0 7 9 ) X 45 7
L E A D A S S IG M E N T S
E
-A 4
C
S
3
G
E
IG B T
2 5 .7 0 ( 1.0 12 )
2 5 .2 0 ( .9 9 2 )
6.2 5 ( .24 6 )
1 2.50 ( .4 92 )
A1
-B 1
D
4
1
R FULL
7 .50 ( .29 5 )
1 5.00 ( .5 90 )
2
S
G
HEXFET
K2
3
4
1
2
3
2
K1 A2
H E XF R E D
3 0 .2 0 ( 1 .1 89 )
2 9 .8 0 ( 1 .1 73 )
4X
2 .1 0 ( .0 82 )
1 .9 0 ( .0 75 )
8.10 ( .3 19 )
7.70 ( .3 03 )
0 .25 ( .01 0 ) M C A M B M
2 .10 ( .08 2 )
1 .90 ( .07 5 )
12 .3 0 ( .4 84 )
11 .8 0 ( .4 64 )
-C 0.1 2 ( .00 5 )
Tube
QUANTITY PER TU BE IS 1 0
M4 SREW AND W ASHE R IN CLUDED
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Data and specifications subject to change without notice. 2/99
8
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