IRF IRL1104

PD -91805
IRL1104
HEXFET® Power MOSFET
Logic-Level Gate Drive
● Advanced Process Technology
● Ultra Low On-Resistance
● Dynamic dv/dt Rating
● 175°C Operating Temperature
● Fast Switching
● Fully Avalanche Rated
Description
●
D
VDSS = 40V
RDS(on) = 0.008Ω
G
ID = 104A…
S
Fifth Generation HEXFET ® power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve the lowest possible on-resistance
per silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET® power MOSFETs are well known for, provides
the designer with an extremely efficient device for use in a
wide variety of applications.
The TO-220 package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 watts. The low thermal resistance
and low package cost of the TO-220 contribute to its wide
acceptance throughout the industry.
TO-220AB
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy ‚
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw.
104…
74
416
167
1.1
±16
340
62
17
5.0
-55 to + 175
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case)
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Min.
Typ.
Max.
Units
––––
––––
––––
––––
0.50
––––
0.9
––––
62
°C/W
1
10/19/99
IRL1104
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
Qg
Q gs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
40
–––
–––
–––
1.0
53
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
V(BR)DSS
RDS(on)
Static Drain-to-Source On-Resis-
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
IGSS
Typ.
–––
0.04
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
18
257
32
64
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.008
VGS = 10V, ID = 62A „
Ω
0.012
VGS = 4.5V, ID = 52A „
–––
V
VDS = VGS, ID = 250µA
–––
S
VDS = 25V, ID = 62A
25
VDS = 40V, VGS = 0V
µA
250
VDS = 32V, VGS = 0V, TJ = 150°C
100
VGS = 16V
nA
-100
VGS = -16V
68
ID = 62A
24
nC VDS = 32V
33
VGS = 4.5V, See Fig. 6 and 13 „
–––
VDD = 20V
–––
ID = 62A
ns
–––
RG = 3.6Ω, VGS = 4.5V
–––
RD = 0.4Ω, See Fig. 10 „
Between lead,
4.5 –––
6mm (0.25in.)
nH
from package
7.5 –––
and center of die contact
3445 –––
VGS = 0V
1065 –––
pF
VDS = 25V
270 –––
ƒ = 1.0MHz, See Fig. 5
D
G
S
Source-Drain Ratings and Characteristics
IS
I SM
VSD
trr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
‚ VDD = 15V, starting TJ = 25°C, L = 0.18mH
RG = 25Ω, IAS =62A. (See Figure 12)
ƒ ISD ≤ 62A, di/dt ≤ 217A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
2
Min. Typ. Max. Units
Conditions
MOSFET symbol
––– ––– 104…
showing the
A
G
integral reverse
––– ––– 416
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 62A, VGS = 0V „
––– 84 126
ns
TJ = 25°C, IF = 62A
––– 223 335
nC di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
D
S
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… Calculated continuous current based on maximum allowable
junction temperature;for recommended current-handling of the
package refer to Design Tip # 93-4
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IRL1104
1000
1000
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 2.7V
100
100
10
2.7V
20µs PULSE WIDTH
TJ = 25 °C
1
0.1
1
10
R DS(on) , Drain-to-Source On Resistance
(Normalized)
TJ = 25 ° C
TJ = 175 ° C
100
10
V DS = 25
50V
20µs PULSE WIDTH
8.0
10.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
2.5
6.0
1
VDS , Drain-to-Source Voltage (V)
1000
4.0
20µs PULSE WIDTH
TJ = 175 °C
1
0.1
100
Fig 1. Typical Output Characteristics
1
2.0
2.7V
10
VDS , Drain-to-Source Voltage (V)
I D , Drain-to-Source Current (A)
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 2.7V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
ID = 104A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRL1104
VGS =
Ciss =
Crss =
Coss =
C, Capacitance (pF)
5000
4000
0V,
f = 1MHz
Cgs + Cgd , Cds SHORTED
Cgd
Cds + Cgd
Ciss
3000
2000
Coss
1000
10
VGS, Gate-to-Source Voltage (V)
6000
ID = 62 A
VDS = 32V
VDS = 20V
8
6
4
2
Crss
0
1
10
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
VDS , Drain-to-Source Voltage (V)
20
40
60
80
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
10000
1000
100
TJ = 175 ° C
1000
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10
TJ = 25 ° C
1
0.1
0.2
100
100us
1ms
10
10ms
TC = 25 °C
TJ = 175 °C
Single Pulse
V GS = 0 V
0.8
1.4
2.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10us
2.6
1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL1104
120
100
I D , Drain Current (A)
RD
VDS
LIMITED BY PACKAGE
VGS
D.U.T.
RG
+
-VDD
80
4.5V
60
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
40
Fig 10a. Switching Time Test Circuit
20
VDS
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
0.01
0.00001
P DM
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL1104
1 5V
D R IV E R
L
VD S
D .U .T
RG
IA S
150 V
tp
+
- VD D
A
0.0 1 Ω
Fig 12a. Unclamped Inductive Test Circuit
EAS , Single Pulse Avalanche Energy (mJ)
800
TOP
BOTTOM
600
400
200
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
V (B R )D SS
tp
ID
25A
44A
62A
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Current Regulator
Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
QG
12V
.2µF
.3µF
4.5 V
QGS
+
V
- DS
D.U.T.
QGD
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRL1104
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

•
•
•
•
RG
dv/dt controlled by R G
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
D=
Period
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET power MOSFETs
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7
IRL1104
TO-220AB Package Details
Dimensions are shown in millimeters (inches)
2.87 (.11 3)
2.62 (.10 3)
10 .54 (.4 15)
10 .29 (.4 05)
-B -
3 .7 8 (.149 )
3 .5 4 (.139 )
4.69 ( .18 5 )
4.20 ( .16 5 )
-A -
1 .32 (.05 2)
1 .22 (.04 8)
6.47 (.25 5)
6.10 (.24 0)
4
1 5.24 (.60 0)
1 4.84 (.58 4)
1.15 (.04 5)
M IN
1
2
1 4.09 (.55 5)
1 3.47 (.53 0)
4.06 (.16 0)
3.55 (.14 0)
3X
3X
L E A D A S S IG NM E NT S
1 - GATE
2 - D R A IN
3 - S O U RC E
4 - D R A IN
3
1 .4 0 (.0 55 )
1 .1 5 (.0 45 )
0.93 (.03 7)
0.69 (.02 7)
0 .3 6 (.01 4)
3X
M
B A M
0.55 (.02 2)
0.46 (.01 8)
2 .92 (.11 5)
2 .64 (.10 4)
2.54 (.10 0)
2X
N O TE S :
1 D IM E N S IO N IN G & TO L E R A N C ING P E R A N S I Y 1 4.5M , 1 9 82.
2 C O N TR O L LIN G D IM E N S IO N : IN C H
3 O U T LIN E C O N F O R M S TO JE D E C O U T LIN E TO -2 20 A B .
4 H E A TS IN K & LE A D M E A S U R E M E N T S D O N O T IN C LU DE B U R R S .
TO-220AB Part Marking
E X A M P L E : TH IS IS A N IR F1 0 1 0
W IT H A S S E M B L Y
LOT C ODE 9B1M
A
IN TE R N A TIO N A L
R E C TIF IE R
LOGO
ASSEMBLY
LOT CO DE
PART NU MBER
IR F 10 1 0
9246
9B
1M
D A TE C O D E
(Y Y W W )
YY = YEAR
W W = W EEK
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
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Data and specifications subject to change without notice. 10/99
8
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