IRF IRL8113PBF

PD - 95582
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l Lead-Free
Benefits
l Low RDS(on) at 4.5V VGS
l Low Gate Charge
l Fully Characterized Avalanche Voltage
and Current
IRL8113PbF
IRL8113SPbF
IRL8113LPbF
HEXFET® Power MOSFET
VDSS RDS(on) max Qg (Typ.)
6.0m:
30V
23nC
D2Pak
IRL8113S
TO-220AB
IRL8113
TO-262
IRL8113L
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
30
V
VGS
Gate-to-Source Voltage
± 20
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
h
74 h
IDM
Pulsed Drain Current
420
PD @TC = 25°C
Maximum Power Dissipation
110
PD @TC = 100°C
Maximum Power Dissipation
57
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
105
c
A
W
0.76
-55 to + 175
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
f
W/°C
°C
300 (1.6mm from case)
y
y
10 lbf in (1.1N m)
Thermal Resistance
Parameter
i
RθJC
Junction-to-Case
RθCS
Case-to-Sink, Flat Greased Surface
RθJA
Junction-to-Ambient
RθJA
Junction-to-Ambient (PCB Mount)
fi
f
gi
Typ.
Max.
Units
–––
1.32
°C/W
0.50
–––
–––
62
–––
40
Notes  through ‡ are on page 12
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1
07/20/04
IRL8113/S/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
30
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.020
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
4.8
6.0
–––
5.7
7.1
VGS(th)
Gate Threshold Voltage
1.35
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
IDSS
Drain-to-Source Leakage Current
–––
V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 21A
VGS = 4.5V, ID = 17A
2.25
V
-5.0
–––
mV/°C
–––
1.0
µA
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
86
–––
–––
Total Gate Charge
–––
23
35
Qgs1
Pre-Vth Gate-to-Source Charge
–––
6.0
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
2.0
–––
Qgd
Gate-to-Drain Charge
–––
8.3
–––
ID = 17A
Qgodr
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
6.7
–––
See Fig. 16
Qsw
–––
10
–––
Qoss
Output Charge
–––
14
–––
td(on)
Turn-On Delay Time
–––
14
–––
tr
Rise Time
–––
38
–––
td(off)
Turn-Off Delay Time
–––
18
–––
tf
Fall Time
–––
5.0
–––
Ciss
Input Capacitance
–––
2840
–––
Coss
Output Capacitance
–––
620
–––
Crss
Reverse Transfer Capacitance
–––
290
–––
IGSS
gfs
Qg
e
e
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
S
VDS = 15V, ID = 17A
nC
VGS = 4.5V
VDS = 15V
nC
VDS = 16V, VGS = 0V
VDD = 15V, VGS = 4.5V
e
ID = 17A
ns
Clamped Inductive Load
pF
VDS = 15V
VGS = 0V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
–––
Max.
220
Units
mJ
–––
17
A
–––
11
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
ISM
(Body Diode)
Pulsed Source Current
–––
–––
VSD
(Body Diode)
Diode Forward Voltage
–––
trr
Reverse Recovery Time
–––
Qrr
Reverse Recovery Charge
–––
2
c
105
h
Conditions
MOSFET symbol
A
D
420
showing the
integral reverse
–––
1.0
V
p-n junction diode.
TJ = 25°C, IS = 17A, VGS = 0V
18
27
ns
7.2
11
nC
G
S
e
TJ = 25°C, IF = 17A, VDD = 15V
di/dt = 100A/µs
e
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IRL8113/S/LPbF
1000
1000
BOTTOM
100
3.0V
≤ 60µs PULSE WIDTH
Tj = 25°C
BOTTOM
100
10
3.0V
≤ 60µs PULSE WIDTH
Tj = 175°C
10
0.1
1
10
0.1
VDS, Drain-to-Source Voltage (V)
1
10
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (Α)
VGS
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
100
T J = 175°C
T J = 25°C
10
VDS = 10V
≤ 60µs PULSE WIDTH
1
1.0
2.0
3.0
4.0
5.0
6.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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7.0
ID = 42A
VGS = 10V
1.5
1.0
0.5
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRL8113/S/LPbF
100000
12
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 17A
C, Capacitance (pF)
C oss = C ds + C gd
10000
Ciss
1000
Coss
Crss
VDS= 24V
VDS= 15V
10
8
6
4
2
0
100
1
10
0
100
10
20
30
40
50
60
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000.0
10000
100.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
T J = 175°C
10.0
T J = 25°C
1.0
1000
100
10
1
VGS = 0V
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
0.1
0.1
0.0
0.5
1.0
1.5
2.0
2.5
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
100µsec
3.0
0.1
1.0
10.0
100.0
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL8113/S/LPbF
2.5
120
VGS(th) Gate threshold Voltage (V)
LIMITED BY PACKAGE
ID , Drain Current (A)
100
80
60
40
20
0
25
50
75
100
125
150
2.0
ID = 250µA
1.5
1.0
0.5
175
-75 -50 -25
T C , Case Temperature (°C)
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC )
1
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
τJ
R1
R1
τJ
τ1
R2
R2
τ2
τ1
τ2
Ci= τi/Ri
Ci= τi/Ri
0.001
SINGLE PULSE
( THERMAL RESPONSE )
R3
R3
τ3
τC
τ
τ3
Ri (°C/W) τi (sec)
0.430
0.000266
0.397
0.493
0.000685
0.007393
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
40
1000
EAS, Single Pulse Avalanche Energy (mJ)
RDS(on), Drain-to -Source On Resistance ( mΩ)
IRL8113/S/LPbF
ID = 21A
30
20
10
T J = 125°C
T J = 25°C
0
2.0
4.0
6.0
8.0
10.0
ID
8.8A
11A
BOTTOM 17A
TOP
800
600
400
200
0
25
VGS, Gate-to-Source Voltage (V)
50
75
100
125
150
175
Starting T J, Junction Temperature (°C)
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13c. Maximum Avalanche Energy
Vs. Drain Current
15V
LD
VDS
L
VDS
DRIVER
+
VDD -
D.U.T
RG
IAS
20V
VGS
tp
+
V
- DD
D.U.T
A
VGS
0.01Ω
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 13a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
Fig 14a. Switching Time Test Circuit
VDS
90%
10%
VGS
I AS
Fig 13b. Unclamped Inductive Waveforms
6
td(on)
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
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IRL8113/S/LPbF
D.U.T
Driver Gate Drive
P.W.
+
ƒ
-
‚
„
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 16. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 17. Gate Charge Waveform
7
IRL8113/S/LPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgd
+⎜I ×
× Vin ×
ig
⎝
⎞
⎞ ⎛
Qgs 2
f⎟ + ⎜ I ×
× Vin × f ⎟
ig
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRL8113/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113)
2.62 (.103)
10.54 (.415)
10.29 (.405)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
3
14.09 (.555)
13.47 (.530)
1.40 (.055)
1.15 (.045)
IGBTs, CoPACK
2 - DRAIN
1- GATE
3 - SOURCE
2- DRAIN
3- SOURCE
4 - DRAIN
4- DRAIN
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
HEXFET
1 - GATE
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
0.55 (.022)
0.46 (.018)
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMP L E : T HIS IS AN IR F 1010
L OT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB L Y L INE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
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PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
9
IRL8113/S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T H IS IS AN IR F 530S WIT H
L OT CODE 8024
AS S E MB L E D ON WW 02, 2000
IN T H E AS S E MB L Y L INE "L "
INT E R NAT IONAL
R E CT IF IE R
L OGO
Note: "P" in as s embly line
pos ition indicates "L ead-F ree"
PAR T NU MB E R
F 530S
AS S E MB L Y
L OT CODE
DAT E CODE
YE AR 0 = 2000
WE E K 02
L INE L
OR
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
10
P ART NU MB E R
F 53 0S
DAT E CODE
P = DE S IGNAT E S L E AD-F R E E
P R ODU CT (OP T IONAL )
YE AR 0 = 2000
WE E K 02
A = AS S E MB L Y S IT E CODE
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IRL8113/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E XAMPLE : T HIS IS AN IRL3103L
LOT CODE 1789
AS S E MB L ED ON WW 19, 1997
IN T HE AS S E MB L Y LINE "C"
Note: "P" in ass embly line
pos ition indicates "L ead-F ree"
INT E RNAT IONAL
RECT IF IER
L OGO
AS S E MB LY
L OT CODE
PART NUMBE R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
OR
INT E RNAT IONAL
RE CT IF IE R
L OGO
AS S E MB LY
L OT CODE
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PART NUMB E R
DAT E CODE
P = DE S IGNAT E S L EAD-F RE E
PRODUCT (OPT IONAL )
YEAR 7 = 1997
WE EK 19
A = AS S E MB L Y S IT E CODE
11
IRL8113/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 1.58mH, RG = 25Ω,
IAS = 21A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ This is only applied to TO-220AB pakcage.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
… This is applied to D2Pak, when mounted on 1" square PCB (FR4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
† Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 42A.
‡ Rθ is measured at TJ approximately 90°C
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
12
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/