PD - 95220 IRL3715ZCSPbF IRL3715ZCLPbF Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l Lead-Free HEXFET® Power MOSFET VDSS RDS(on) max 11mΩ 7.0nC D2Pak IRL3715ZCS TO-262 IRL3715ZCL 20V Benefits l Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current Qg Absolute Maximum Ratings Parameter Max. Units 20 V VDS Drain-to-Source Voltage VGS Gate-to-Source Voltage ± 20 ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 50 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 36 IDM Pulsed Drain Current 200 PD @TC = 25°C Maximum Power Dissipation 45 PD @TC = 100°C Maximum Power Dissipation 23 TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range Soldering Temperature, for 10 seconds A W W/°C °C 0.30 -55 to + 175 300 (1.6mm from case) Thermal Resistance Parameter RθJC RθJA Typ. Max. Units Junction-to-Case ––– 3.33 °C/W Junction-to-Ambient (PCB Mount) ––– 40 Notes through are on page 11 www.irf.com 1 04/27/04 IRL3715ZCS/LPbF Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions BVDSS Drain-to-Source Breakdown Voltage 20 ––– ––– ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.014 ––– RDS(on) Static Drain-to-Source On-Resistance ––– 9.2 11 ––– 12.4 15.5 VGS(th) Gate Threshold Voltage 1.65 2.1 2.55 V ∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -5.2 ––– mV/°C IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA VDS = 16V, VGS = 0V ––– ––– 150 Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V Gate-to-Source Reverse Leakage ––– ––– -100 Forward Transconductance 31 ––– ––– IGSS gfs Qg V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 15A VGS = 4.5V, ID = 12A VDS = VGS, ID = 250µA VDS = 16V, VGS = 0V, TJ = 125°C VGS = -20V S VDS = 10V, ID = 12A Total Gate Charge ––– 7.0 11 Qgs1 Pre-Vth Gate-to-Source Charge ––– 2.1 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 0.9 ––– Qgd Gate-to-Drain Charge ––– 2.3 ––– ID = 12A Qgodr Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– 1.7 ––– See Fig. 16 Qsw ––– 3.2 ––– Qoss Output Charge ––– 3.7 ––– td(on) Turn-On Delay Time ––– 7.1 ––– VDD = 10V, VGS = 4.5V tr Rise Time ––– 44 ––– ID = 12A td(off) Turn-Off Delay Time ––– 11 ––– tf Fall Time ––– 4.6 ––– Ciss Input Capacitance ––– 870 ––– Coss Output Capacitance ––– 270 ––– Crss Reverse Transfer Capacitance ––– 140 ––– VDS = 10V nC nC VGS = 4.5V VDS = 10V, VGS = 0V ns Clamped Inductive Load pF VDS = 10V VGS = 0V ƒ = 1.0MHz Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy Typ. ––– Units mJ Max. 44 ––– 12 A ––– 4.5 mJ Diode Characteristics Parameter Min. Typ. Max. Units Conditions IS Continuous Source Current ––– ––– 50 ISM (Body Diode) Pulsed Source Current ––– ––– 200 showing the integral reverse VSD (Body Diode) Diode Forward Voltage ––– ––– 1.0 V S p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V trr Reverse Recovery Time ––– 9.1 14 ns Qrr Reverse Recovery Charge ––– 2.2 3.3 nC 2 MOSFET symbol A D G TJ = 25°C, IF = 12A, VDD = 10V di/dt = 100A/µs www.irf.com IRL3715ZCS/LPbF 1000 1000 VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V 100 10 3.0V 60µs PULSE WIDTH Tj = 25°C 100 1 3.0V 10 60µs PULSE WIDTH Tj = 175°C 1 0.1 1 10 0.1 VDS, Drain-to-Source Voltage (V) 1 10 VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.0 T J = 25°C T J = 175°C 100 VDS = 10V 60µs PULSE WIDTH 10 3.0 4.0 5.0 6.0 7.0 8.0 9.0 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 10.0 RDS(on) , Drain-to-Source On Resistance (Normalized) 1000 ID, Drain-to-Source Current (Α) VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP ID = 30A VGS = 10V 1.5 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRL3715ZCS/LPbF 10000 12 VGS, Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = C gd C, Capacitance (pF) Coss = Cds + Cgd 1000 Ciss Coss Crss 8 6 4 2 10 0 100 8 12 16 Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 1000 ID, Drain-to-Source Current (A) 1000.0 ISD, Reverse Drain Current (A) 4 QG Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) 100.0 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 T J = 175°C 10.0 T J = 25°C 1.0 VGS = 0V 0.0 0.5 1.0 1.5 VSD, Source-toDrain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 100µsec 10 1 0.1 4 VDS= 20V VDS= 10V 10 0 100 1 ID= 12A 2.0 1msec Tc = 25°C Tj = 175°C Single Pulse 0 10msec 1 10 100 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRL3715ZCS/LPbF 60 2.6 VGS(th) Gate threshold Voltage (V) LIMITED BY PACKAGE ID , Drain Current (A) 50 40 30 20 10 2.2 1.8 1.4 0 25 50 75 100 125 150 ID = 250µA 1.0 175 -75 -50 -25 T C , Case Temperature (°C) 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature Thermal Response ( Z thJC ) 10 1 D = 0.50 0.20 0.10 0.05 0.1 0.02 0.01 τJ SINGLE PULSE ( THERMAL RESPONSE ) 0.01 R1 R1 τJ τ1 τ1 R2 R2 τ2 τ2 R3 R3 τ3 τC τ τ3 Ci= τi/Ri Ci= τi/Ri Ri (°C/W) τi (sec) 0.942 0.000145 0.982 0.000805 0.406 0.004757 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 1E-006 1E-005 0.0001 0.001 0.01 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRL3715ZCS/LPbF 200 D R IV E R L VDS D .U .T RG + V - DD IA S 2V0GS V A 0 .0 1 Ω tp Fig 12a. Unclamped Inductive Test Circuit V (B R )D S S tp EAS, Single Pulse Avalanche Energy (mJ) 15V ID 3.9A 5.4A BOTTOM 12A TOP 160 120 80 40 0 25 50 75 100 125 150 175 Starting T J, Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy vs. Drain Current IAS LD VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF Fig 14a. Switching Time Test Circuit .3µF D.U.T. + V - DS VDS 90% VGS 3mA 10% IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit 6 VGS td(on) tr td(off) tf Fig 14b. Switching Time Waveforms www.irf.com IRL3715ZCS/LPbF D.U.T Driver Gate Drive P.W. + + - - • • • • D.U.T. ISD Waveform Reverse Recovery Current + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period * RG D= VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer Period VDD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRL3715ZCS/LPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput Q + oss × Vin × f + (Qrr × Vin × f ) 2 This can be expanded and approximated by; *dissipated primarily in Q1. Ploss = (Irms 2 × Rds( on ) ) Q + I × gd × Vin × ig Q f + I × gs 2 × Vin × ig f + (Qg × Vg × f ) + Qoss × Vin × f 2 This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRL3715ZCS/LPbF D2Pak Package Outline Dimensions are shown in millimeters (inches) D2Pak Part Marking Information (Lead-Free) T H IS IS AN IR F 530S WIT H L OT CODE 8024 AS S E MB L E D ON WW 02, 2000 IN T H E AS S E MB L Y L INE "L " IN T E R N AT IONAL R E CT IF IE R L OGO Note: "P " in as s embly line pos ition indicates "L ead-F ree" P AR T NU MB E R F 530S AS S E MB L Y L OT CODE DAT E CODE YE AR 0 = 2000 WE E K 02 L INE L OR INT E R N AT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE www.irf.com P AR T N U MB E R F 530S DAT E CODE P = DE S IGNAT E S L E AD-F R E E P R ODU CT (OP T ION AL ) YE AR 0 = 2000 WE E K 02 A = AS S E MB L Y S IT E CODE 9 IRL3715ZCS/LPbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information E XAMPL E : T H IS IS AN IR L 3103L L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB L Y L INE "C" Note: "P " in as s embly line pos ition indicates "L ead-F ree" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE P AR T NU MB E R DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C OR INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE 10 P AR T NU MB E R DAT E CODE P = DE S IGNAT E S L E AD-F R E E P R ODU CT (OPT IONAL ) YE AR 7 = 1997 WE E K 19 A = AS S E MB L Y S IT E CODE www.irf.com IRL3715ZCS/LPbF D2Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TR R 1 .6 0 (.0 6 3 ) 1 .5 0 (.0 5 9 ) 4 .1 0 (.1 6 1 ) 3 .9 0 (.1 5 3 ) F E E D D IR E C T IO N 1 .6 0 (.0 6 3 ) 1 .5 0 (.0 5 9 ) 1 1 .6 0 (.4 5 7 ) 1 1 .4 0 (.4 4 9 ) 1 .8 5 (.0 7 3 ) 1 .6 5 (.0 6 5 ) 0 .3 6 8 (.0 1 4 5 ) 0 .3 4 2 (.0 1 3 5 ) 1 5 .4 2 (.6 0 9 ) 1 5 .2 2 (.6 0 1 ) 2 4 .3 0 (.9 5 7 ) 2 3 .9 0 (.9 4 1 ) TR L 1 .7 5 (.0 6 9 ) 1 .2 5 (.0 4 9 ) 1 0 .9 0 (.4 2 9 ) 1 0 .7 0 (.4 2 1 ) 4 .7 2 (.1 3 6 ) 4 .5 2 (.1 7 8 ) 1 6 .1 0 (.6 3 4 ) 1 5 .9 0 (.6 2 6 ) F E E D D IR E C T IO N 2 7 .4 0 (1.0 7 9) 2 3 .9 0 (.9 4 1 ) 13 .5 0 (.53 2 ) 12 .8 0 (.50 4 ) 4 3 3 0 .0 0 (14 .1 7 3 ) M AX. 60 .0 0 (2 .3 6 2) M IN . NO TES : 1 . C O M F O R M S TO E IA-41 8 . 2 . C O N T R O LL IN G D IM EN S IO N : M IL L IM ET E R . 3 . D IM E N S IO N M E A S U R E D @ H U B . 4 . IN C L U D E S F L A N G E D IST O R T IO N @ O U T E R E D G E. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.61mH, RG = 25Ω, IAS = 12A. Pulse width ≤ 400µs; duty cycle ≤ 2%. 3 0.40 (1 .1 9 7) M AX. 2 6 .4 0 (1 .0 3 9 ) 2 4 .4 0 (.96 1 ) 3 4 This is applied to D2Pak, when mounted on 1" square PCB (FR4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 04/04 www.irf.com 11 Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/