PD - 95432
IRF1503SPbF
IRF1503LPbF
Typical Applications
l
l
l
HEXFET® Power MOSFET
14V Automotive Electrical Systems
14V Electronic Power Steering
Lead-Free
D
VDSS = 30V
Benefits
l
l
l
l
l
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
RDS(on) = 3.3mΩ
G
ID = 75A
S
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFETs utilizes the lastest processing
techniques to achieve extremely low on-resistance per silicon area.
Additional features of this HEXFET power MOSFET are a 175°C
junction operating temperature, fast switching speed and improved
repetitive avalanche rating. These benefits combine to make this
design an extremely efficient and reliable device for use in Automotive
applications and a wide variety of other applications.
D2Pak
IRF1503S
TO-262
IRF1503L
Absolute Maximum Ratings
Parameter
ID @ TC
ID @ TC
ID @ TC
IDM
PD @TC
= 25°C
= 100°C
= 25°C
= 25°C
VGS
EAS
EAS (tested)
IAR
EAR
TJ
TSTG
Max.
Continuous Drain Current, VGS @ 10V (Silicon limited)
Continuous Drain Current, V GS @ 10V (See Fig.9)
Continuous Drain Current, VGS @ 10V (Package limited)
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
Repetitive Avalanche Energy
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
Units
190
130
75
960
200
1.3
± 20
510
980
See Fig.12a, 12b, 15, 16
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Typ.
Max.
Units
–––
0.50
–––
0.75
–––
62
°C/W
1
06/21/04
IRF1503S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
30
–––
–––
2.0
75
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.028
2.6
–––
–––
–––
–––
–––
–––
130
36
41
17
130
59
48
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
5.0
LS
Internal Source Inductance
–––
13
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
5730
2250
290
7580
2290
3420
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
3.3
mΩ VGS = 10V, ID = 140A
4.0
V
VDS = 10V, ID = 250µA
–––
S
VDS = 25V, ID = 140A
20
VDS = 30V, VGS = 0V
µA
250
VDS = 24V, VGS = 0V, TJ = 150°C
200
VGS = 20V
nA
-200
VGS = -20V
200
ID = 140A
54
nC
VDS = 24V
62
VGS = 10V
–––
VDD = 15V
–––
ID = 140A
ns
–––
RG = 2.5Ω
–––
VGS = 10V
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 24V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 24V
Source-Drain Ratings and Characteristics
IS
ISM
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
VSD
trr
Qrr
ton
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.049mH
RG = 25Ω, IAS = 140A. (See Figure 12).
ISD ≤ 140A, di/dt ≤ 110A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 190
showing the
A
G
integral reverse
––– ––– 960
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 140A, VGS = 0V
––– 71 110
ns
TJ = 25°C, IF = 140A
––– 110 170
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
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IRF1503S/LPbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
4.5V
10
100
4.5V
20µs PULSE WIDTH
Tj = 25°C
1
20µs PULSE WIDTH
Tj = 175°C
10
0.1
1
10
100
0.1
1
VDS, Drain-to-Source Voltage (V)
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
200
1000
Gfs, Forward Transconductance (S)
T J = 25°C
ID, Drain-to-Source Current (Α)
10
T J = 175°C
100
VDS = 25V
20µs PULSE WIDTH
10
4.0
5.0
6.0
7.0
8.0
9.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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T J = 175°C
160
120
T J = 25°C
80
40
VDS = 25V
20µs PULSE WIDTH
0
10.0
0
40
80
120
160
200
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
3
IRF1503S/LPbF
10000
Crss
Coss
ID= 140A
VGS , Gate-to-Source Voltage (V)
8000
C, Capacitance (pF)
20
VGS = 0V,
f = 1 MHZ
C iss
= C gs + C gd , C ds
SHORTED
= Cgd
= Cds + Cgd
Ciss
6000
4000
Coss
2000
Crss
16
12
8
4
0
0
1
VDS= 24V
10
0
100
40
80
120
160
200
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000.0
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100.0
T J = 175°C
10.0
1.0
T J = 25°C
VGS = 0V
0.1
0.0
0.4
0.8
1.2
1.6
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1000
100µsec
100
1msec
10
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
1
2.0
1
10
100
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF1503S/LPbF
200
2.0
I D = 240A
LIMITED BY PACKAGE
120
80
40
0
25
50
75
100
125
150
175
1.5
(Normalized)
RDS(on) , Drain-to-Source On Resistance
ID , Drain Current (A)
160
1.0
0.5
V GS = 10V
0.0
-60
-40
TC , Case Temperature ( °C)
-20
0
20
40
60
80
100 120 140 160 180
( °C)
TJ, Junction Temperature
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
(Z thJC )
1
D = 0.50
Thermal Response
0.20
0.1
0.10
P DM
0.05
t1
0.02
0.01
t2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t
2
J = P DM x Z thJC
+T C
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF1503S/LPbF
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
VGS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
1400
15V
1200
1000
800
600
400
200
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGD
4.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
QGS
3.0
ID = 250µA
2.0
1.0
VGS
-75 -50 -25
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRF1503S/LPbF
10000
Avalanche Current (A)
Duty Cycle = Single Pulse
1000
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
100
0.05
0.10
10
1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
600
TOP
Single Pulse
BOTTOM 50% Duty Cycle
ID = 140A
500
400
300
200
100
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I av = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRF1503S/LPbF
D.U.T
Driver Gate Drive
+
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
V DD
• dv/dt controlled by R G
• Driver same type as D.U.T.
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
V GS
RG
RD
D.U.T.
+
-V DD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRF1503S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF 530S WIT H
LOT CODE 8024
ASS E MBL ED ON WW 02, 2000
IN T HE AS S E MBLY L INE "L"
INT E RNAT IONAL
RECT IF IE R
LOGO
Note: "P" in as s embly line
pos ition indicates "Lead-F ree"
PART NUMBE R
F 530S
AS S EMB LY
LOT CODE
DAT E CODE
YEAR 0 = 2000
WE EK 02
LINE L
OR
INT ERNAT IONAL
RE CT IF IER
LOGO
AS S E MBLY
LOT CODE
www.irf.com
PAR T NUMBER
F530S
DAT E CODE
P = DE S IGNAT ES LEAD-F REE
PRODU CT (OPT IONAL)
YEAR 0 = 2000
WEEK 02
A = AS S EMBLY S ITE CODE
9
IRF1503S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
AS S EMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
Note: "P" in as sembly line
position indicates "Lead-Free"
INT ERNAT IONAL
RECTIFIER
LOGO
AS S EMBLY
L OT CODE
PART NUMBER
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RE CTIFIER
LOGO
AS S EMBLY
LOT CODE
10
PART NUMBER
DAT E CODE
P = DE S IGNAT ES L EAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = AS S E MBL Y S IT E CODE
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IRF1503S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/04
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11