PD - 95379 IRFZ44ZPbF IRFZ44ZSPbF IRFZ44ZLPbF AUTOMOTIVE MOSFET Features O O O O O O O Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175°C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free HEXFET® Power MOSFET D VDSS = 55V RDS(on) = 13.9mΩ G Description Specifically designed for Automotive applications, this HEXFET® Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. ID = 51A S TO-220AB IRFZ44Z D2Pak IRFZ44ZS TO-262 IRFZ44ZL Absolute Maximum Ratings Max. Units ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) Parameter 51 A ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig. 9) 36 200 c IDM Pulsed Drain Current PD @TC = 25°C Maximum Power Dissipation VGS Gate-to-Source Voltage EAS Single Pulse Avalanche Energy (Thermally Limited) Linear Derating Factor EAS (tested) Single Pulse Avalanche Energy Tested Value IAR Avalanche Current EAR Repetitive Avalanche Energy TJ Operating Junction and TSTG Storage Temperature Range c i d 80 W 0.53 ± 20 W/°C V 86 mJ 105 See Fig.12a,12b,15,16 h A mJ -55 to + 175 Soldering Temperature, for 10 seconds °C 300 (1.6mm from case ) Mounting torque, 6-32 or M3 screw 10 lbf•in (1.1N•m) Thermal Resistance Typ. Max. Units RθJC Junction-to-Case Parameter ––– 1.87 °C/W RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– RθJA Junction-to-Ambient ––– 62 RθJA Junction-to-Ambient (PCB Mount, steady state) ––– 40 j HEXFET® is a registered trademark of International Rectifier. www.irf.com 1 06/07/04 IRFZ44Z/S/LPbF Static @ TJ = 25°C (unless otherwise specified) Parameter V(BR)DSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) Min. Typ. Max. Units Qg Qgs Qgd td(on) tr td(off) tf LD Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance 55 ––– ––– 2.0 22 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– LS Internal Source Inductance ––– 7.5 ––– Ciss Coss Crss Coss Coss Coss eff. Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance ––– ––– ––– ––– ––– ––– 1420 240 130 830 190 300 ––– ––– ––– ––– ––– ––– gfs IDSS IGSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current ––– ––– 0.054 ––– 11.1 13.9 ––– 4.0 ––– ––– ––– 20 ––– 250 ––– 200 ––– -200 29 43 7.2 11 12 18 14 ––– 68 ––– 33 ––– 41 ––– 4.5 ––– V V/°C mΩ V S µA nA nC Conditions VGS = 0V, ID = 250µA Reference to 25°C, ID = 1mA VGS = 10V, ID = 31A VDS = VGS, ID = 250µA VDS = 25V, ID = 31A VDS = 55V, VGS = 0V VDS = 55V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V ID = 31A VDS = 44V VGS = 10V VDD = 28V ID = 31A RG = 15Ω VGS = 10V Between lead, D f f ns f nH 6mm (0.25in.) from package pF G and center of die contact S VGS = 0V VDS = 25V ƒ = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz VGS = 0V, VDS = 44V, ƒ = 1.0MHz VGS = 0V, VDS = 0V to 44V Diode Characteristics Parameter Min. Typ. Max. Units IS Continuous Source Current ––– ––– 51 ISM (Body Diode) Pulsed Source Current ––– ––– 200 VSD trr Qrr ton (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time ––– ––– ––– ––– 23 17 1.2 35 26 c Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by TJmax, starting TJ = 25°C, L =0.18mH, RG = 25Ω, IAS = 31A, VGS =10V. Part not recommended for use above this value. ISD ≤ 31A, di/dt ≤ 840A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 1.0ms; duty cycle ≤ 2%. 2 Conditions MOSFET symbol A V ns nC showing the integral reverse D p-n junction diode. G TJ = 25°C, IS = 31A, VGS = 0V TJ = 25°C, IF = 31A, VDD = 28V di/dt = 100A/µs f S f Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. 100% tested to this value in production. This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Rθ is rated at TJ of approximately 90°C. www.irf.com IRFZ44Z/S/LPbF 1000 1000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 100 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 100 10 4.5V BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V 10 ≤60µs PULSE WIDTH ≤60µs PULSE WIDTH Tj = 25°C 1 Tj = 175°C 1 0.1 1 10 100 0.1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 10 100 Fig 2. Typical Output Characteristics 1000 60 100 TJ = 175°C T J = 25°C 10 VDS = 15V ≤60µs PULSE WIDTH 1.0 2 4 6 8 10 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 12 Gfs, Forward Transconductance (S) ID, Drain-to-Source Current (Α) 1 V DS, Drain-to-Source Voltage (V) 50 T J = 25°C 40 30 TJ = 175°C 20 10 V DS = 10V 0 0 10 20 30 40 50 ID,Drain-to-Source Current (A) Fig 4. Typical Forward Transconductance vs. Drain Current 3 IRFZ44Z/S/LPbF 10000 12.0 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd VGS, Gate-to-Source Voltage (V) ID= 31A C, Capacitance(pF) C oss = C ds + C gd Ciss 1000 Coss Crss VDS= 44V VDS= 28V 10.0 VDS= 11V 8.0 6.0 4.0 2.0 100 0.0 1 10 100 0 VDS, Drain-to-Source Voltage (V) 10 15 20 25 30 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 1000 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 5 100 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 T J = 175°C 10 T J = 25°C 1 0.10 100µsec 10 1msec 1 Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.01 0.1 0.0 0.5 1.0 1.5 VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 10msec 2.0 1 10 100 1000 VDS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRFZ44Z/S/LPbF 55 RDS(on) , Drain-to-Source On Resistance (Normalized) 2.5 50 ID, Drain Current (A) 45 40 35 30 25 20 15 10 5 0 ID = 31A VGS = 10V 2.0 1.5 1.0 0.5 25 50 75 100 125 150 175 -60 -40 -20 0 T C , Case Temperature (°C) 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) Fig 10. Normalized On-Resistance vs. Temperature Fig 9. Maximum Drain Current vs. Case Temperature Thermal Response ( Z thJC ) 10 1 D = 0.50 0.20 0.10 0.05 0.1 τJ 0.02 0.01 0.01 R1 R1 τJ τ1 τ1 R2 R2 τ2 R3 R3 τ3 τ2 Ci= τi/Ri Ci= i/Ri SINGLE PULSE ( THERMAL RESPONSE ) τC τ τ3 Ri (°C/W) τi (sec) 0.8487 0.00044 0.6254 0.00221 0.3974 0.01173 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFZ44Z/S/LPbF 400 DRIVER L VDS D.U.T RG + V - DD IAS VGS 20V tp A 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS , Single Pulse Avalanche Energy (mJ) 15V ID TOP 3.8A 5.5A BOTTOM 31A 350 300 250 200 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) I AS Fig 12c. Maximum Avalanche Energy vs. Drain Current Fig 12b. Unclamped Inductive Waveforms QG 10 V QGS QGD VG Charge Fig 13a. Basic Gate Charge Waveform L DUT 0 VGS(th) Gate threshold Voltage (V) 4.0 ID = 250µA 3.0 2.0 VCC 1K 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) Fig 13b. Gate Charge Test Circuit 6 Fig 14. Threshold Voltage vs. Temperature www.irf.com IRFZ44Z/S/LPbF 100 Avalanche Current (A) Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆ Tj = 25°C due to avalanche losses 0.01 10 0.05 0.10 1 0.1 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 100 TOP Single Pulse BOTTOM 1% Duty Cycle ID = 31A 80 60 40 20 0 25 50 75 100 125 150 Starting T J , Junction Temperature (°C) Fig 16. Maximum Avalanche Energy vs. Temperature www.irf.com 175 Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav 7 IRFZ44Z/S/LPbF D.U.T Driver Gate Drive + - • • • • D.U.T. ISD Waveform Reverse Recovery Current + dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period * RG D= VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer - Period P.W. + V DD + Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage - Body Diode VDD Forward Drop Inductor Curent Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V DS VGS RG RD D.U.T. + -VDD 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % Fig 18a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr t d(off) tf Fig 18b. Switching Time Waveforms 8 www.irf.com IRFZ44Z/S/LPbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) -B- 3.78 (.149) 3.54 (.139) 4.69 (.185) 4.20 (.165) -A- 1.32 (.052) 1.22 (.048) 6.47 (.255) 6.10 (.240) 4 15.24 (.600) 14.84 (.584) LEAD ASSIGNMENTS 1.15 (.045) MIN 1 2 3 14.09 (.555) 13.47 (.530) 1.40 (.055) 1.15 (.045) IGBTs, CoPACK 2 - DRAIN 1- GATE 3 - SOURCE 2- DRAIN 3- SOURCE 4 - DRAIN 4- DRAIN 1234- GATE COLLECTOR EMITTER COLLECTOR 4.06 (.160) 3.55 (.140) 3X 3X LEAD ASSIGNMENTS HEXFET 1 - GATE 0.93 (.037) 0.69 (.027) 0.36 (.014) 3X M B A M 0.55 (.022) 0.46 (.018) 2.92 (.115) 2.64 (.104) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information E XAMP L E : T H IS IS AN IR F 1010 L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB L Y L INE "C" Note: "P" in assembly line position indicates "Lead-Free" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE www.irf.com P AR T NU MB E R DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C 9 IRFZ44Z/S/LPbF D2Pak Package Outline Dimensions are shown in millimeters (inches) D2Pak Part Marking Information T HIS IS AN IRF530S WIT H LOT CODE 8024 AS S EMB LED ON WW 02, 2000 IN T HE AS S EMBLY LINE "L" INT ERNAT IONAL RECTIF IER LOGO Note: "P" in as s embly line pos ition indicates "Lead-F ree" PART NUMB ER F 530S ASS EMBLY LOT CODE DAT E CODE YEAR 0 = 2000 WEEK 02 LINE L OR INTE RNAT IONAL RECTIFIER LOGO AS S E MBLY LOT CODE 10 PART NUMBER F 530S DAT E CODE P = DES IGNAT ES LEAD-FRE E PRODUCT (OPT IONAL) YE AR 0 = 2000 WEEK 02 A = AS S E MBLY S ITE CODE www.irf.com IRFZ44Z/S/LPbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 AS S EMBLED ON WW 19, 1997 IN T HE AS S EMBLY LINE "C" Note: "P" in as s embly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C OR INT ERNAT IONAL RECT IF IER LOGO AS S EMBLY LOT CODE www.irf.com PART NUMBER DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 7 = 1997 WEEK 19 A = AS S EMBLY S IT E CODE 11 IRFZ44Z/S/LPbF D2Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) FEED DIRECTION 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 11.60 (.457) 11.40 (.449) 0.368 (.0145) 0.342 (.0135) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 4.72 (.136) 4.52 (.178) 16.10 (.634) 15.90 (.626) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 60.00 (2.362) MIN. 30.40 (1.197) MAX. 26.40 (1.039) 24.40 (.961) 3 4 TO-220AB package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 06/04 12 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/