MPC5645SDEMOUG, MPC5645S-DEMO-V2 User Guide

Freescale Semiconductor
User Guide
Document Number:MPC5645SDEMOUG
Rev. 0,09/2012
MPC5645S-DEMO-V2
Contents
1 Introduction
The MPC5645S-DEMO-V2 features the MPC5645S 32-bit
microcontroller targeting single-chip automotive instrument
cluster applications. MPC5645S devices are part of the
MPC56xxS family of Power Architecture™-based devices.
This family has been designed with an emphasis on providing
cost-effective and high quality graphics capabilities to satisfy
the increasing market demand for color Thin Film Transistor
(TFT) displays within the vehicle cockpit. Traditional cluster
functions, such as gauge drive, real time counter, and sound
generation are also integrated on each device. The board
simplifies the development of applications for the MPC5645S
microcontroller by providing the most commonly used
external peripherals on a single PCB. Specifically the board
features:
• Connections for 2 x SHARP LQ043T1DG01 touch
screen LCD TFT panels or LQ043T1DG02 LCD TFT
panels (DCU and DCULite)
• General purpose MICTOR connector for connection of
your own panels
• Two DVI outputs for connection of desktop TFT LCD
panels
• Headphone amplifier and 3.5 mm stereo jacks for sound
output from MPC5645S
• Video in port and video ADC supporting composite
video connected to the VIU module
• 64 MB of serial flash in two 32 MB chips connected in
parallel to QuadSPI ports
• 64 MB of mobile LPDDR memory in two 32 MB chips
© 2012 Freescale Semiconductor, Inc.
1
Introduction................................................................1
2
Initial Setup...............................................................2
3
On-board memory.....................................................4
4
Application Configuration........................................4
5
Index of MCU pin usage.........................................11
6
Project Examples.....................................................13
Initial Setup
• 1 x CAN and 1 x LIN serial interfaces with physical interfaces
• USB port for connection to UART or SPI interfaces
• Nexus interfaces on MICTOR connector and JTAG connector and embedded USB debug connection
2 Initial Setup
The MPC5645S-DEMO-V2 comes configured for use with the most common settings. You can change the configuration of
the board by configuring jumpers as described below.
NOTE
In all cases remove power from the board before changing any jumper configurations.
2.1 Power supply
The board operates from a +12 V, 1 A supply provided on a barrel jack, centre positive, at P1. The board is protected by a 20
mm cartridge fuse F1 and a value of 1 A is recommended for this. Note that the board includes protection for reverse polarity
connection.
The +12 V supply to the board is enabled by switch SW1.
The board generates further voltages from this initial supply. It is recommended that these are always enabled for normal
operation but they can be disabled or disconnected by connecting or removing jumpers as follows:
• +5 V switching regulator — Disable fit J40
• +3.3 V switching regulator — Disable fit J35
• +1.8 V switching regulator — Disable fit J36
It is possible to isolate the MCU from its power supplies for measurement purposes or to change the supply voltage by
cutting traces on the PCB and providing jumpers to replace the connections.
NOTE
Take extreme care to avoid unintentionally disconnecting the MCU from its power
supplies.
Jumper
Description
Cut link
J38
Analog 5 V supply
SH4
J39
MCU stepper motor +5 V supply
SH5
J37
MCU 3V3 supply
SH3
By default the VDDR supply for the MCU is configured to operate from +5 V but this can be changed by cutting a link and
connecting a jumper.
Jumper
Description
J11 1-2
MCU VDDR operates from +5 V
J11 2-3
MCU VDDR operates from +3.3 V
Cut link
SH1
2.2 Oscillator
The MCU operates from an 8 MHz crystal.
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Initial Setup
A second auxiliary 32 kHz crystal is directly connected to port pins PC14 and PC15. This means that these pins cannot also
be used for other functions.
2.3 Reset
The board includes an external low-voltage reset controller that pulls reset on the part when the +5 V regulator drops below
approximately 2.6 V. A reset button SW6 is also supplied to force the MCU reset line low. LED D9 will be active when the
MCU reset line is active.
2.4 Development tools
Several suppliers provide development and debugging support for the MPC5645S. Freescale provides the CodeWarrior
Development Studio, this is a complete integrated Development Environment (IDE) that provides a highly visual and
automated framework to accelerate the development of the most complex embedded applications. An evaluation license is
available from freescale.com.
2.5 Debug interfaces
There are three debug interfaces available on the board:
• Integrated OSBDM debug interface on J2
• JTAG 14-pin universal debug connector on P1
• Nexus trace debug connector on P3
The USB connector J2 allows connection of the MPC5645S-DEMO-V2 directly to a PC with the CodeWarrior Development
Studio for the MPC56xx. The debug software provided with this package recognizes the attached hardware as a development
tool and attempts to connect. Depending on the version of the tool in use it may be necessary to select the MPC5645S as the
target processor. The MPC5645S-DEMO-V2 does not take any power from the connected USB cable and so the primary 12
V power supply must always be provided even when using the integrated debugger.
The P1 and P3 connectors allow connection of any compatible debugger. Refer to freescale.com for information about
suppliers of these debuggers
The choice of a debug interface in use is made using jumper J12. Fit jumpers to J12 to enable the integrated OSBDM
debugger.
Header
Description
J12 1-2
Enable the integrated debugger option
12 3-4, 5-6
Enable the integrated debugger to reset the MPC5645S MCU
If using an external debugger then there is an option to place the TDO pin in a known default state. Jumper J8 provides an
optional pull-up on the TDO pin.
Header
J8
Description
Provides 10k pull up on JTAG TDO pin
Header J10 is provided to reprogram the integrated MC9S08JM60 device if required.
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3
On-board memory
2.6 Starting up the board
Follow these steps when starting the board:
•
•
•
•
•
Install the required development software include any additional software required for your debugger of choice
Ensure switch SW1 is in the OFF position. It connects the supplied +12 V power supply from connector P2
Select the debugger option required using jumpers on J12
Connect the debugger or USB cable
If any change has been made to the default power supply cut-links then ensure that a suitable jumper is in place (see
section 2.1)
• Apply power to the board by setting SW1 to the ON position.
• If the integrated OSBDM debugger is in use then the host PC recognizes a USB connection and may require new
drivers to be installed. Install the required drivers.
• Run your debug software and the MPC5645S MCU will be visible and ready for development
Note that the OSBDM connection requires a delay of 200 ms after reset for correct connection.
3 On-board memory
There are two external memory systems available on the MPC5645S and both are supported on the MPC5645S-DEMO-V2.
• 2 x Micron MT46H16M16LFBF-6 (256 Mb) LPDDR memories providing a 32-bit interface to the MPC5645S for a
total of 32 MB of SDRAM
• 2 x Spansion S25FL256P (256 Mb) serial QuadSPI flashes providing a dual QuadSPI serial flash interface to the
MPC5645S for a total of 32 MB of serial flash
The LPDDR memory uses the dedicated SDRAM interface on the MPC5645S and requires no GPIO for this function. The
serial flash uses 12 GPIO pins.
There is no hardware configuration required to use these on-board memories.
Both memory systems require software configuration before they can be used. See Section 6 for how to obtain example
configurations provided by Freescale.
4 Application Configuration
This section includes a description of the interfaces provided on the board and how to configure them.
NOTE
In all cases remove power from the board before changing any jumper configurations or
connecting any external hardware.
4.1 LCD TFT panels
The board contains direct connections for two independent TFT panels. These are connected to the DCU and the DCULite
interfaces and each provides a choice of three connection possibilities:
• 2 x Sharp LQ043T1DG01 touch screen LCD TFT panels or LQ043T1DG02 LCD TFT panels
• General purpose MICTOR connector for connection of your own panel
• DVI to video monitor
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Application Configuration
The panels can be configured independently from each other, but only one option should be used at a time for each of the
DCU or DCULite.
4.2 Configuring touch screen panels
Fit the Sharp LQ043T1DG01 touch screen panels by connecting the panel FFCs to J42, J44, and J46 for the DCU and J41,
J43, J45 for the DCULite.
When using the Sharp LQ043T1DG01 touch screen LCD TFT panels a backlight voltage of +30 V is provided.
4.3 Using an alternate panel
It is possible to connect a different panel to the board by using the general purpose connectors P9 for the DCU and P8 for the
DCULite. These are industry-standard 38-pin MICTOR connectors.
4.4 DVI connection
It is also possible to connect the board to external TFT panels via DVI (Digital Video Interface) connectors P10 and P11. To
enable the DVI output, configure the DCU or DCULite to a suitable panel format (normally VGA or higher) then connect a
jumper at J14 1-2 for the DCU and J14 3-4 for the DCULite. Any timing skew on the panel can be corrected by adjusting the
switches at SW5. The status of the connection may be monitored at J14 pin 5 for the DCU or J14 pin 6 for the DCULite; a
low signal on these pins indicates a panel has been connected.
NOTE
The default connection on the board assumes that four ADC pins will be used on
connectors P8 and P9 for resistive touch screen operation. Since the connector also
allows an I2C interface on these pins the factory configuration connects the following
pins directly to each other: PC0=PC4=PK10 and PC1=PC5=PK11. If these pins are to be
used independently then it is necessary to cut links SH6, SH7, SH9, and SH10.
Table 5. DCU connections on connector P9
Pin no
RGB Digital
RSDS
Pin no
RGB Digital
RSDS
1
R0
RSDS0P
2
B0
RSDS8P
3
R1
RSDS0M
4
B1
RSDS8M
5
R2
RSDS1P
6
B2
RSDS9P
7
R3
RSDS1M
8
B3
RSDS9M
9
R4
RSDS2P
10
B4
RSDS10P
11
R5
RSDS2M
12
B5
RSDS10M
13
R6
RSDS3P
14
B6
RSDS11P
15
R7
RSDS3M
16
B7
RSDS11M
17
G0
RSDS4P
18
+3.3 V
19
G1
RSDS4M
20
+3.3 V
21
G2
RSDS5P
22
VSYNC
—
23
G3
RSDS5M
24
HSYNC
—
25
G4
RSDS6P
26
DE/ENABLE
RSDCLKM
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Application Configuration
Table 5. DCU connections on connector P9 (continued)
Pin no
RGB Digital
RSDS
Pin no
RGB Digital
RSDS
27
G5
RSDS6M
28
CLK
RSDSCLKP
29
G6
RSDS7P
30
+5 V
31
G7
RSDS7M
32
+5 V
33
Y down
34
Y up1
35
X right
36
X left 2
37
+12 V
38
+12 V
1. Optional I2C SDA_1 function on PK10 by link at SH10
2. Optional I2C SCK_1 function on PK11 by link at SH9
Table 6. DCULite connections on connector P8
Pin no
RGB Digital
Pin no
RGB Digital
1
R0
2
B0
3
R1
4
B1
5
R2
6
B2
7
R3
8
B3
9
R4
10
B4
11
R5
12
B5
13
R6
14
B6
15
R7
16
B7
17
G0
18
+3.3 V
19
G1
20
+3.3 V
21
G2
22
VSYNC
23
G3
24
HSYNC
25
G4
26
DE/ENABLE
27
G5
28
CLK
29
G6
30
+5 V
31
G7
32
+5 V
33
Y down
34
Y up1
35
X right
36
X left 2
37
+12 V
38
+12 V
1. Optional I2C SDA_1 function on PK10 by link at SH7
2. Optional I2C SCK_1 function on PK11 by link at SH6
4.5 Sound
The board contains a Freescale sound codec and headphone amplifier SGTL5000 connected to the MCU. This codec can
provide headphone and line out levels from either the I2S or the PWM output of the MCU’s Sound Generation Module
(SGM).
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Application Configuration
The choice of output between the PWM and I2S is controlled in software by registers in the SGM. The board is configured
such that the I2S DO pin is connected to PB8, and the PWMO pin is connected to PB10. Therefore, for PWM output the
software must configure the MCU to use PB10 and for I2S output the software must configure the MCU to use PB8.
The sound output is available to directly connect headphones at connector J30. A line-level output is also provided at
connector J34.
4.6 PWM Output
The PWM output is filtered by a 8 kHz low pass 4th order Bessel filter and fed to the left Line-in pin of the SGTL5000. An
unfiltered version is fed to the right Line-in pin. This allows comparison of the sound quality of filtered and unfiltered PWM
under software control.
4.7 I2S Output
The SGTL5000 codec is configured using I2C_1 on pins PF4 and PF7. Refer to the documentation of the codec for
configuration options.
4.8 Video
The board allows connection of two types of video input. Connector J24 allows input of an analogue composite video signal
(either PAL or NTSC) and connector P4 allows connection of a digital RGB or YUV bus.
The composite signal conversion is performed by an Analog Devices video DAC ADV7180. This device is configured using
I2C_0 on pins PF8 and PF9 and controlled by MCU I/O PM0, PM1, PJ3, and PF2.
MCU port
MCU Function
Comment
PF8
SDA_0
PF9
SCL_0
I2C_0 bus
PM0
Output pin
Video DAC reset input pin (active low)
PM1
Output pin
Video DAC power down pin (active low)
PF2
Input pin
Video DAC interrupt request pin (active
low)
The digital input signals are connected such that the VIU or PDI inputs can be used. Note that I2C_0 is also used as the
configuration bus for peripherals connected to this connector.
Table 8. Pinout for P4
Pin no
Signal
Pin no
Signal
1
VIU0 (PK2)
2
PDI0 (PJ4)
3
VIU1 (PK3)
4
PDI1 (PJ5)
5
VIU2 (PK4)
6
PDI2 (PJ6)
7
VIU3 (PK5)
8
PDI3 (PJ7)
9
VIU4 (PK6)
10
PDI4 (PJ8)
11
VIU5 (PL4)
12
PDI5 (PJ9)
Table continues on the next page...
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Application Configuration
Table 8. Pinout for P4 (continued)
Pin no
Signal
Pin no
Signal
13
VIU6 (PL5)
14
PDI6 (PJ10)
15
VIU7 (PL6)
16
PDI7 (PJ11)
17
VIU8 (PL7)
18
+3.3 V
19
VIU9 (PL8)
20
+3.3 V
21
—
22
PDI_VSYNC (PJ2)
23
—
24
PDI_HSYNC (PJ1)
25
—
26
PDI_DE/ENABLE (PG12)
27
VIU CLK (PJ3)
28
PDI_CLK (PL9)
29
—
30
+5 V
31
—
32
+5 V
33
—
34
SDA_0 (PF8)
35
—
36
SCL_0 (PF9)
37
+12 V
38
+12 V
4.9 CAN Interface
The board implements a physical interface (TJA1041T) on one of the MCU FlexCAN busses: FlexCAN0 is connected to J5.
It is possible to supply the physical interface from an external power supply. The physical interface enable and inhibit signals
are brought out to headers to allow connection of additional control signals from the CPU. However, jumper J13 provides
simple connections to the STB and EN pins to allow the interface to be operated with the addition of two jumpers.
Connector
Description
J20
Vbat supply for physical interface for FlexCAN0, fit jumper to use on-board +12 V supply
J16 – 1
FlexCAN0 Physical interface INH pin
J16 – 2
FlexCAN0 Physical interface ERR pin
J13 – 1
FlexCAN0 Physical interface WAKE pin
J13 – 4
FlexCAN0 Physical interface EN pin — jumper to pin 2 for pull to +5 V, jumper to pin 6 for software control
via PM4
J13 – 5
FlexCAN0 Physical interface STB pin — jumper to pin 3 for pull to +5 V, jumper to pin 6 for software control
via PM4
4.10 Serial Boot mode support
FlexCAN0 uses MCU pins PB0 and PB1 for compatibility with serial boot mode support on the MPC5645S. To configure
the device to perform FlexCAN serial boot mode place jumpers on J13 pin 2-4 and pin 3-5, then select CAN boot mode by
placing jumpers on J23 pin 9-10 (no jumper on J23 pin 11-12).
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Application Configuration
4.11 LIN Interface
The board implements a physical interface (MCZ33661EF) on one of the MCU LINFlex buses: LINFlex1 is connected to J3.
It is possible to pull up the LIN bus from an external power supply.
Connector
J7
Description
Diode and 1k pull up enabled between Vsup and LIN bus
4.12 Serial Boot mode support
See Section 3.6.1 for details.
4.13 USB adapter
There are two options for serial connection to a host computer over USB. The UART function of LINFlex0 can be routed
through the integrated OSBDM debug connector at J2 or to a dedicated connector at J1.
• The use of the serial channel on J2 requires suitable software for the OSBDM interface.
• The J1 connector provides a high-speed interface to the MCU via a dedicated USB adapter (FT2232D). The USB
adapter supports the USB serial port format and is recognized automatically by a host computer, however, you may
need to install drivers to use the port. The drivers are available from http://www.ftdichip.com/FTDrivers.htm. Select the
drivers that support FT2232D interface IC.
Select the required USB interface by setting jumpers on J17.
Header
USB Port
MCU pin/port
J17 – 1-3
FT2232D BDBUS0
PB3
J17 – 2-4
FT2232D BDBUS1
PB2
J17 – 3-5
OSBDM Rx
PB3
J17 – 4-6
OSBDM Tx
PB2
The USB converter IC has six spare pins on port A. These are available on header J6.
Header
FT2232D Port
MCU pin/port
J6 – 1
ADBUS0
—
J6 – 2
ADBUS4
—
J6 – 3
ADBUS1
—
J6 – 4
ADBUS5
—
J6 – 5
ADBUS2
—
J6 – 6
ADBUS6
—
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Application Configuration
4.14 Serial Boot mode support
The LinFlex0 (UART) function uses MCU pins PB2 and PB3 for compatibility with serial boot mode support on the
MPC5645S. To configure the device to perform LINFlex serial boot mode place jumpers on J23 pin 9-10 and pin 11-12 and
J17 pins 1-3 and 2-4.
4.15 Stepper Motor and ADC ports
The board provides two connectors that simplify stepper motor connections to the board. Each port also includes four ADC
pins to allow other analog feedback and measurement if required.
These pins may be used as general purpose I/O as required.
Connector pin
Description
Connector pin
Description
P6 — 1
PC10 (ANS10)
P6 — 2
PD4 (M1C0M)
P6 — 3
PL0 (ANS19)
P6 — 4
PD5 (M1C0P)
P6 — 5
GND
P6 — 6
PD6 (M1C1M)
P6 —7
PD3 (M0C1M)
P6 — 8
PD7 (M1C1P)
P6 — 9
PD2 (M0C1P)
P6 — 10
+5 V
P6 — 11
PD1 (M0C0M)
P6 — 12
PL1 (ANS18)
P6 — 13
PD0 (M0C0P)
P6 — 14
PC11 (ANS11)
P5 — 1
PD11 (M2C1P)
P5 — 2
PL3 (ANS16)
P5 — 3
PD10 (M2C1M)
P5 — 4
PC13 (ANS13)
P5 — 5
PD9 (M2C0P)
P5 — 6
+5 V
P5 — 7
PD8 (M2C0M)
P5 — 8
PD12 (M3C0M)
P5 — 9
GND
P5 — 10
PD13 (M3C0P)
P5 — 11
PC12 (ANS12)
P5 — 12
PD14 (M3C1M)
P5 — 13
PL2 (ANS17)
P5 –—14
PD15 (M3C1P)
4.16 General purpose I/O interfaces
To simplify hardware debug the board provides some basic I/O functions on the remaining unused MCU pins. These pins
may be connected to external hardware or jumpered to the on-board functions.
Connector
MCU Port
Hardware function
Recommended function
J32 1-2
PK0
Red LED: anode connected via 100R to +3.3 eMIOS[18]
V
J32 3-4
PF0
Green LED: anode connected via 100R to
+3.3 V
eMIOS1[19]
J32 5-6
PF1
Push switch of thumbwheel SW9
EIF8 (SIU interrupt)
J32 7-8
PF3
Push switch of thumbwheel SW8
WKUP10
J32 9-10
PL10
A pin of thumbwheel SW8
eMIOS1[10:11] in quadrature mode
J32 10-12
PL11
B pin of thumbwheel SW8
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Index of MCU pin usage
Connector
MCU Port
Hardware function
Recommended function
J32 13-14
PL12
A pin of thumbwheel SW9
J32 15-16
PL13
B pin of thumbwheel SW9
eMIOS1[12:13] in quadrature mode
J23 1-2
PK7
DIP switch 1
GPIO
J23 3-4
PK8
DIP switch 2
GPIO
J23 5-6
PK9
DIP switch 3
GPIO
J23 7-8
PB4
None
J23 9-10
PB5
Pull up to 3.3 V
FABM serial boot mode
J23 11-12
PB6
Pull down to GND
ABS serial boot select
J23 13-14
PH4
None
J23 15-16
PJ12
DIP switch 4
GPIO
J47 1
PE0
None
High drive GPIO / Stepper
J47 3
PE1
None
High drive GPIO / Stepper
J47 5
PE2
None
High drive GPIO / Stepper
J47 7
PE3
None
High drive GPIO / Stepper
J47 9
PE4
None
High drive GPIO / Stepper
J47 11
PE5
None
High drive GPIO / Stepper
J47 13
PE6
None
High drive GPIO / Stepper
J47 15
PE7
None
High drive GPIO / Stepper
J48 1
PC8
None
ADC
J48 3
PC9
None
ADC
5 Index of MCU pin usage
To optimize function and performance most of the MCU I/O pins are pre-configured for specific uses on the board. This table
summarizes where the I/O pins are used and for what function.
Table 15. I/O pins
MCU Port
Connected to
Recommended function
PA[0:15]
DCU display connectors
DCU
PB[0:1]
FlexCAN0 Interface
FlexCAN0
PB[2:3]
USB Interface or OSBDM Debug
Interface
LINFlex0 (UART mode)
PB[4:6]
J23
GPIO/DPSI/Alternate boot function
PB7
SCK function of Sound codec
SGM (I2S)
PB8
DO function of Sound codec
SGM (I2S)
PB9
FS function of Sound codec
SGM (I2S)
PB10
PWM function of Sound codec
SGM (PWM)
PB11
MCLK function of Sound codec
SGM
PB[12:13]
LINFlex1 Interface
LINFlex1
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Index of MCU pin usage
Table 15. I/O pins (continued)
MCU Port
Connected to
Recommended function
PC[0:3]
Touch screen for DCU
ADC
PC[4:7]
Touch screen for DCULite
ADC
PC[8:9]
J48
ADC / GPIO
PC[10:11]
P6
ADC / GPIO
PC[12:13]
P5
ADC / GPIO
PC[14:15]
32 kHz crystal
SXOSC (32 kHz oscillator)
PD[0:7]
P6
SMC / SSD / GPIO
PD[8:15]
P5
SMC / SSD / GPIO
PE[0:7]
J47
SMC / SSD / GPIO
PF0
J32 or Green LED
GPIO / eMIOS1[19]
PF1
J32 or thumbwheel switch on SW9
GPIO / EIF[8] / eMIOS1[20]
PF2
Video ADC interrupt
WKUP9 or NMI
PF3
J32 or thumbwheel switch on SW8
GPIO / WKUP10] / eMIOS1[21]
PF4
I2C for sound codec
I2C_1
PF5
I/O for QuadSPI1
QuadSPI
PF6
I/O for QuadSPI1
QuadSPI
PF7
I2C for sound codec
I2C_1
PF[8:9]
I2C for video ADC and video input port
I2C_0
PF[10:15]
Serial flash U18 (QuadSPI0)
QuadSPI
PG[0:11]
DCU display connectors
DCU
PG12
P4 Camera input port
PDI
PH[0:3]
P1 and P3 debug connectors
JTAG
PH4
J23
GPIO / eMIOS1[21]
PJ0
DCULite display connectors
DCULite
PJ[1:2]
P4 Camera input port
VIU/PDI
PJ3
Video clock in on video ADC and
camera input port
VIU
PJ[4:11]
P4 camera input port
PDI
PJ12
J23 or DIP switch
GPIO
PJ[13:15]
Serial flash U21 (QuadSPI1)
QuadSPI
PK0
J32 or Red LED
GPIO / eMIOS1[18]
PK1
I/O for QuadSPI1
QuadSPI
PK[2:6]
P4 camera input port
VIU
PK[7:9]
J23 or DIP switch
GPIO / LINFlex2 / SGM (PWM)
PK[10:11]
Optional I2C interface for DCU adapter
and DCULite adapter (fit SH6, SH7,
SH10, SH11)
PL[0:1]
P6
ADC / FlexCAN1
PL[2:3]
P5
ADC / eMIOS1[22:23]
PL[4:9]
P4 Camera input port
VIU
Table continues on the next page...
MPC5645S-DEMO-V2 , Rev. 0,09/2012
12
Freescale Semiconductor, Inc.
Project Examples
Table 15. I/O pins (continued)
MCU Port
Connected to
Recommended function
PL[10:11]
J32 and thumbwheel encoder
GPIO / eMIOS1[10:11]
PL[12:13]
J32 and thumbwheel encoder
GPIO / eMIOS1[12:13]
PM[0:1]
Reset and power down for video ADC
and 10k pull down
PM2
DCULite display connectors
DCULite
PM3
LIN enable
GPIO
PM4
J13 or FlexCAN0 enable
GPIO
PM[12:13]
DCULite display connectors
DCULite
PN[0:15]
DCULite display connectors
DCULite
PP[0:7]
DCULite display connectors
DCULite
6 Project Examples
Freescale provides CodeWarrior Development Studio projects to assist in the development of software. These software
projects initialize the MPC5645S-DEMO-V2 hardware and provide simple examples of how the hardware may be used. See
freescale.com for the latest version.
MPC5645S-DEMO-V2 , Rev. 0,09/2012
Freescale Semiconductor, Inc.
13
5
4
3
Table of Contents
D
1
2
3
4
5
6
7
8
9
10
11
12
2
Rev
Revision History & TOC
Notes
Power supply
MPC5645S Power
Decoupling
MPC5645S Peripherals
Displays
Memory
Audio and motors
Serial Interface
Video Input
Debug
1
Revisions
Description
First
production
MPC5645S board
X1
Date
Approved
05August11
S.McAslan
1. Capacitors C2, C31, C23, C26 changed to higher voltage
rating
2.Capacitor C201 moved from VDD_30V to P12V
X2
18August11
S.McAslan
3.Capacitors C215,C216 added to VDD_30V
D
4.Capacitors C217,C218, C219,C220 added to DM_VTT_DDR2
power
5.Capacitor C37 added to P12V
1.Capacitor C38 & C39 filtering added to USB nets and
made as DNP.
X3
2.Net names added before and after FB in power and
regulator sections.
23August11
S.McAslan
3.Differential clock nets suitably appended with _P/_N
4. U14 updated to 344-01142
X4
1. Header J31 rotated per Alberto request.
2. IC U4, LIN Transceiver changed from 312-76816 to
TMP-WF-15527 (TJA1020T from NXP)
26August11
S.McAslan
30August11
S.McAslan
05Sep11
S.McAslan
06Sep11
S.McAslan
07Sep11
S.McAslan
19Sep11
S.McAslan
17Nov11
S.McAslan
3. Decaps added to U19,U20 and U22
1. Pullup resistor added to PF8 (SDA_0), PF9(SCL_0)
PF4 (SDA_1) and PF7(SCL_0) and made as DNP
C
X5
X6
C
2. Netname between U25 and P11 changed from DCU_*
to DCUL_*
1. DDR series termination resistor's package changed
from 0603 to 0402
1. DDR series termination resistors RN5 and RN6 package
changed to individual 0402 package to aid routing.
X7
2. Capacitor C38 & C39 filtering added to USB nets
JM_USB_N/P and made as DNP.
X8
1. CAN-DB9 pinouts changed to standard connection.
A
A085 Release
AX1
A070 Release - J41,J42 connector pin outs reversed
R89 removed from U12- pin no 3
R23 value changed from 100ohms to 470ohms
B
B
18Nov11
U12 - pin 4 is supply changed from 5V_SR to 3.3V_SR
– J12 pin 4 is connected with U12- pin 3
( Net name JM_RST_B)
B
21Nov11
R89(DNP) added at U12- pin no 3, connected to 3.3V_SR
MKT part number updated as MPC5645S-DEMO-V2
S.McAslan
23Nov11
Board ID, Board Revision are Hard wired.
29Nov11
A085 Release
1Dec11
Microcontroller Solutions Group
A
A
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
ICAP Classification:
FCP: ____
FIUO:
PUBI: ____
X
Designer:
Drawing Title:
S.McAslan
MPC5645S-DEMO-V2
5
4
3
2
Drawn by:
S.McAslan
Page Title:
Approved:
S.McAslan
Size
C
Document Number
Date:
Friday, January 11, 2013
TITLE PAGE
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
1
of
12
5
4
3
2
1
1. Unless Otherwise Specified:
All resistors are in ohms, 5%, 1/8 Watt
All capacitors are in uF, 20%, 50V
All voltages are DC
All polarized capacitors are aluminum electrolytic
2. Interrupted lines coded with the same letter or letter
combinations are electrically connected.
D
D
3. Device type number is for reference only. The number
varies with the manufacturer.
4. Special signal usage:
_B Denotes - Active-Low Signal
<> or [] Denotes - Vectored Signals
5. Interpret diagram in accordance with American
National Standards Institute specifications, current
revision, with the exception of logic block symbology.
C
C
B
B
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO:
PUBI: ___
X
MPC5645S-DEMO-V2
Page Title:
NOTES
5
4
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
2
of
12
5
4
3
2
1
Power 1: Input and Switchers
D
D
Switching Regulators
Power supply input and filter
P12V
U16
2
Nexus Connector
Power Monitor
P12V
2
Fuse Holder
POWER SWITCH
C2
0.1UF
12V_DC
VFused
C65
+
D5
C1
P12V_R
R59
5V disable
5.0V_SR_EN
C32
+
7
5
100
NC
J40
10UF
C4
+
1
2
0.1UF
C200
0.01uF
L9
1
ON/OFF SW_OUT
C31
68UF
B130LB-13
1000PF
1
47UH
2
3
C_BOOST
FEEDBACK
5.0V_SR
68UH
R108
D12
C202
+
LM2676S-5.0
B130LB-13
68UF
560
HDR 1X2
1000UF
D14 C
5V Switching Regulator (@1A)
GND
GND
TP22
1
5.0V_SR_L
A
1
VSwitched
C
12V-IN
L5
F1
A
1
2
3
ON
5
P2
OFF
INPUT
C
Main Power-In
6
4
8
2.1mm Barrel
Connector
GND
TAB
SW1
G-107-0513
1
3
4
2
A
LED GREEN
GND
C
C
U13
7
C23
5
J35
10UF
3
C116
1
3.3V_SR_L
0.01uF
3.3V_SR
FEEDBACK
L6
ON/OFF SW_OUT
NC
LM2676S-3.3
TP15
47UH
1
2
1
D8
C149
+
B340A
100uF
R102
A
4
8
1
2
0.1UF
C_BOOST
C
6
3.3V disable
3.3V_SR_EN
C21
+
INPUT
GND
TAB
2
HDR 1X2
A
3.3V Switching Regulator (@1A)
GND
270
D10
C
LED GREEN
Vout = 1.21(1 + R2/R1)
Vout = 1.21(1 + 487/1000) = 1.80 V
Test and reference points
R29
1.0K
GND
TP23
TP13
TP18
TP20
TP3
TP2
TP17
TP14
TP1
TP9
TP16
R28
487.0
1
1
1
1
1
1
1
1
B
B
U15
1.8V_SR_EN
C28
1UF
1UF
7
5
C26
0.1UF
C_BOOST
C184
0.01uF
1.8V_SR
FEEDBACK
L7
ON/OFF SW_OUT
NC
J36
2
1
3
1
1.8V_SR_L
1
TP19
47UH
2
1
C
1.8V disable
C27
INPUT
D11
LM2676S-ADJ
C199
+
B130LB-13
A
GND
GND Test Points
6
GND
TAB
2
4
8
1
1
1
1.8V_SR_FB
220uF
HDR 1X2
GND
1.8V Switching Regulator (@0.75A)
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO:
PUBI: ___
X
MPC5645S-DEMO-V2
Page Title:
Power Supply
5
4
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
3
of
12
5
4
3
2
1
Do not fit jumpers
J11
HDR TH 1X3
3.3V_SR
1
2
3
5.0V_SR
MCU POWER
V_REG
VDDA
D
D
V_AN
U14C
SH1
0
L8
AD22
VSSA
VDDA
AC22
1
2
J38
5.0V_SR
VSSA
C
B
VDD33_DDR_1
VDD33_DDR_2
VDD33_DDR_3
VDD33_DDR_4
MPC5645S
416BGA
POWER
SIGNALS
VDDE_1
VDDE_2
VDDE_3
VDDE_4
VDDE_5
VDDE_6
VDDE_7
VDDE_8
VDDE_9
VDDE_10
VDDE_11
VDDE_12
VDDE_13
VDDE_14
VDDE_15
VDDE_16
VDDREG
C2
E3
H3
L3
N3
T3
C5
C8
C11
C14
SH3
0
1.8V_SR
J39
5.0V_SR
SMD_5V
HDR 1X2
MCU_3V3
F4
R4
D6
D12
AD2
W3
AE4
AD7
AE10
AD13
AE16
B17
C19
AD19
B21
B24
H24
N24
E25
L25
V_AN
HDR 1X2
1
2
GND
0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VDDE_DDR_1
VDDE_DDR_2
VDDE_DDR_3
VDDE_DDR_4
VDDE_DDR_5
VDDE_DDR_6
VDDE_DDR_7
VDDE_DDR_8
VDDE_DDR_9
VDDE_DDR_10
SH4
0
3.3V_SR
J37
MCU_3V3
HDR 1X2
1
2
R103
Y1
B2
E2
H2
L2
P2
V2
AE2
C3
F3
J3
M3
R3
AB3
AD4
B5
C6
AE7
B8
C9
L10
N10
R10
U10
AD10
B11
K11
M11
P11
T11
C12
L12
M12
N12
P12
R12
U12
K13
M13
N13
P13
R13
T13
AE13
B14
L14
M14
N14
P14
R14
U14
C15
K15
M15
N15
P15
R15
T15
L16
N16
R16
U16
AD16
C17
K17
M17
P17
T17
B19
AE19
C21
E24
K24
B25
H25
P25
1
2
BLM31AJ601SN1L
VSSA
MCU_3V3
SH2
0
V_REG
C
AA4
VDD12
VDDPLL
VDD12_1
VDD12_2
VDD12_3
VDD12_4
VDD12_5
VDD12_6
VDD12_7
VDD12_8
VDD12_9
VDD12_10
VDD12_11
VDD12_12
VDD12_13
VDD12_14
VDD12_15
VDD12_16
VDD12_17
VDD12_18
VDD12_19
VDD12_20
VDD12_21
VDD12_22
VDD12_23
VDD12_24
AB4
K10
M10
P10
T10
L11
N11
R11
U11
K12
T12
L13
U13
K14
T14
L15
U15
K16
M16
P16
T16
L17
N17
R17
U17
VDD12
B
V_AN
GND
SMD_5V
AC23
U24
AA24
W25
VSSEH_ADC
VSSM_SMD_1
VSSM_SMD_2
VSSM_SMD_3
VDDEH_ADC
VDDM_SMD_1
VDDM_SMD_2
VDDM_SMD_3
AD23
W24
U25
AA25
GND
MPC5645S-416PKG
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO:
PUBI: ___
X
MPC5645S-DEMO-V2
Page Title:
MPC5645 Power
5
4
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
4
of
12
5
4
3
2
1
Decoupling Caps
VDDA
D
C182
C162
C169
1uF
0.047UF
10nF
D
VSSA
VDD12
VDD12
VDD12
Place close to emitter of Q1
C5
+
C82
+
C67
+
C89
+
10UF
10UF
10UF
10UF
C153
C141
C124
C121
C180
C135
C144
C175
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C86
C84
DNP 10UF
DNP 10UF
GND
GND
GND
V_REG
VDD12
C
C
Place decoupling on MCU VDDPLL pin
C114
C112
C3
0.1UF
470pF
10UF
C93
C94
0.1UF
10nF
GND
GND
Place decoupling on MCU VDDR pin
SMD_5V
Place decoupling on MCU VDDM pins
C196
C187
C189
C191
C188
C190
C186
1uF
0.1UF
0.1UF
0.1UF
470pF
470pF
470pF
GND
1.8V_SR
Place decoupling on MCU VDDE_DDR pins - 10 in total, 0.1 and 470pF in a pair
C92
C96
C115
C102
C100
C109
C166
C98
C111
C106
C104
C101
C163
C113
C97
C110
C95
C107
C99
C103
C105
1uF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
B
B
GND
V_AN
Place decoupling close to MCU VDDE_A pins
C193
C192
0.1UF
470pF
GND
MCU_3V3
Place decoupling on MCU VDDE and VDD33_DR pins - 20 in total, 0.1 and 470pF in a pair
C127
C164
C117
C123
C178
C118
C152
C140
C168
C120
C171
C173
C151
C136
C158
C125
C176
C130
C161
C132
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C150
C154
C179
C145
C170
C159
C138
C174
C155
C165
C134
C177
C126
C137
C160
C122
C128
C119
C172
C129
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
GND
MCU_3V3
A
A
GND
ICAP Classification:
Drawing Title:
FCP: ___
FIUO:
PUBI: ___
X
MPC5645S-DEMO-V2
Page Title:
Decoupling
5
4
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
5
of
12
5
4
3
2
1
U14B
PA[0..15]
PG[0..12]
D
PB[0..13]
1
32.768KHZ
C30
12PF
Loop Controlled Pierce
Oscillator Circuit
{12}
GND
3.3V_SR
3.3V_SR
R26
3.3V_SR 3.3V_SR
470
10.0K
(INTRQ_B)
To QuadSPI1
D9
LED RED
R89
MCU_RST
VCC
RST
2
C
4
DNP
RESET Button
SW6
U12
RESET_B
1
2
3
4
AB26
AB25
AB24
AB23
AA26
AA23
Y26
Y25
Y24
Y23
W26
W23
V26
V25
V24
V23
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
U26
U23
T26
T25
T24
T23
R24
R23
To QuadSPI0
(SDA_1)
(IO1)
(IO0)
(SCL_1)
(SDA_0)
(SCL_0)
(CS)
(IO2)
(IO3)
(IO0)
(IO1)
(CLK)
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
C20
B20
AC7
A20
D19
A19
D18
C18
A18
D17
A17
D16
C16
B16
A16
B18
10.0K
JM_RST_B
3
JM_RST_B
MR
VSS
1
C22
PD0/M0C0M/SSD0_0/EMIOS1_8
PD1/M0C0P/SSD0_1/EMIOS1_16
PD2/M0C1M/SSD0_2/EMIOS1_23
PD3/M0C1P/SSD0_3/EMIOS0_9
PD4/M1C0M/SSD1_0/EMIOS0_8
PD5/M1C0P/SSD1_1/EMIOS0_16
PD6/M1C1M/SSD1_2/EMIOS0_23
PD7/M1C1P/SSD1_3
PD8/M2C0M/SSD2_0
PD9/M2C0P/SSD2_1/EMIOS0_9
PD10/M2C1M/SSD2_2/EMIOS0_10
PD11/M2C1P/SSD2_3/EMIOS0_11
PD12/M3C0M/SSD3_0/EMIOS0_12
PD13/M3C0P/SSD3_1/EMIOS0_13
PD14/M3C1M/SSD3_2/EMIOS0_14
PD15/M3C1P/SSD3_3/EMIOS0_15
PE0/M4C0M/SSD4_0
PE1/M4C0P/SSD4_1
PE2/M4C1M/SSD4_2
PE3/M4C1P/SSD4_3
PE4/M5C0M/SSD5_0
PE5/M5C0P/SSD5_1
PE6/M5C1M/SSD5_2
PE7/M5C1P/SSD5_3
PF[0..15]
A
R23
(M4C0M)
(M4C0P)
(M4C1M)
(M4C1P)
(M5C0M)
(M5C0P)
(M5C1M)
(M5C1P)
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PF0/EMIOS1_19Q/EVTO/DCULITE_B2
PF1/EMIOS1_20/MSEO/DCULITE_B3
PF2/NMI
PF3/EMIOS1_21Q/MSEO2/DCULITE_B4
PF4/EMIOS1_14/SDA_B/DCULITE_B5
PF5/QSPI_IO1_B/EMIOS1_15/PDI16_(VIU8)
PF6/QSPI_IO0_B/EMIOS1_16/PDI17_(VIU9)
PF7/EMIOS1_15/SCL_B/DCULITE_B6
PF8/SDA_A/PCS_B2/RXD_B
PF9/SCL_A/PCS_B1/TXD_B
PF10/QSPI_PCS_A/EVTI
PF11/QSPI_IO2_A/MDO0
PF12/QSPI_IO3_A/MDO1
PF13/QSPI_IO0_A/MDO2
PF14/QSPI_IO1_A/MDO3
PF15/QSPI_CLK_A/CLKOUT/MCKO
PTS645
{12}
STM6315RDW13F
GND
GND
{12}
{12}
R24
1
1.0M
MDO[0..11]
12PF
Y2
8MHz
DNP
RESET_B
{12}
{12}
{12}
MDO[0..11]
C25
2
CLK_XTAL8
CLK_EXTAL8
C24
12PF
{12}
{12}
A
Loop Controlled Pierce
Oscillator Circuit
AB1
AA1
CLK_EXTAL8
CLK_XTAL8
GND
MSEO_B
MSEO2_B
EVTI_B
EVTO_B
MCKO
RESET_B
MDO11
MDO10
MDO9
MDO8
MDO7
MDO6
MDO5
MDO4
MDO3
MDO2
MDO1
MDO0
W1
AD8
AE8
AC17
AF19
AC19
AF18
AE18
AD18
AC18
AF17
AE17
AF20
AE20
AD20
AC20
AD9
AD17
EXTAL
XTAL
RESET
PH0
PH1
PH2
PH3
PH4
L26
U4
U3
AD15
AD14
AE14
AF14
AC15
U2
U1
V4
V3
A23
D22
C22
B22
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
A21
D20
AE3
AF3
AC4
AF4
AC5
AD5
AE5
AF5
AF8
AC9
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
PK8
PK9
PK10
PK11
AE22
AE21
AF22
AF21
AB2
AC2
AD1
AE1
AF1
AF2
C24
A24
C23
B23
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
PL8
PL9 (PDI_CLK)
PL10
PL11
PL12
PL13
AE9
AF9
D23
Y3
Y2
L24
L23
PM0
PM1
PM2
PM3
PM4
PM12
PM13
AC3
AD3
AC10
AF10
AC11
AD11
AE11
AF11
AC12
AD12
AE12
AF12
R26
R25
P26
P24
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
PN10
PN11
PN12
PN13
PN14
PN15
P23
N26
N25
N23
M26
M25
M24
M23
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
TCK
TDI
TDO
TMS
{12}
PJ[0..15]
PJ0/DCULITE_B6/I2S_DO
PJ1/VIU1/PDI_HSYNC/EMIOS1_9/EMIOS0_8
PJ2/VIU0/PDI_VSYNC/EMIOS1_14/EMIOS0_9
PJ3/VIU_PCLK/EMIOS0_22/PDI_DE
PJ4/VIU2_PDI0/EMIOS0_21/EMIOS0_23
PJ5/VIU3_PDI1/EMIOS0_20/EMIOS0_16
PJ6/VIU4_PDI2/EMIOS0_19/EMIOS0_15
PJ7/VIU5_PDI3/EMIOS0_18/EMIOS0_14
PJ8/VIU6_PDI4/EMIOS0_17/EMIOS0_13
PJ9/VIU7_PDI5/EMIOS1_22/EMIOS0_12
PJ10/VIU8_PDI6/EMIOS1_17/EMIOS0_11
PJ11/VIU9_PDI7/EMIOS1_15/EMIOS0_10
PJ12/DCU_TAG/TCON0/DCULITE_G6
PJ13/QSPI_PCS_B/EMIOS1_8/PDI13_(VIU5)
PJ14/QSPI_CLK_B/EMIOS1_17/PDI_PCLK
PJ15/QSPI_IO3_B/EMIOS1_9/PDI14_(VIU6)
PK0/EMIOS1_18/DCULITE_G7
PK1/QSPI_IO2_B/EMIOS1_14/PDI15_(VIU7)
PK2/PDI8_(VIU0)/EMIOS1_10/DCULITE_TAG
PK3/PDI9_(VIU1)/EMIOS1_11Q/DCULITE_DE
PK4/PDI10_(VIU2)/EMIOS1_12/DCULITE_HSYNC
PK5/PDI11_(VIU3)/EMIOS1_13Q/DCULITE_VSYNC
PK6/PDI12_(VIU4)/EMIOS1_9/DCULITE_PCLK
PK7/RXD_C/DCULITE_R2/TCON8
PK8/TXD_C/DCULITE_R3/TCON9
PK9/I2S_DO/DCULITE_R4/TCON10
PK10/SDA_B/EMIOS1_12/DCULITE_TAG
PK11/SCL_B/EMIOS1_13Q/DCU_TAG/TCON0
PL0/AN19/CNRX_B/SDA_B
PL1/AN18/CNTX_B/SCL_B
PL2/AN17/CNRX_A/EMIOS1_22
PL3/AN16/CNTX_A/EMIOS1_23
PL4/PCS_C2/PDI13_(VIU5)/TCON6
PL5/PCS_C1/PDI14_(VIU6)/TCON7
PL6/PCS_C0/PDI15_(VIU7)/EMIOS1_18
PL7/SIN_C/PDI16_(VIU8)/EMIOS1_19Q
PL8/SOUT_C/PDI17_(VIU9)/EMIOS1_20
PL9/SCK_C/PDI_PCLK/EMIOS1_21Q
PL10/EMIOS1_10/DCULITE_G2
PL11/EMIOS1_11Q/DCULITE_G3
PL12/EMIOS1_12/DCULITE_G4
PL13/EMIOS1_13Q/DCULITE_G5
PM0/I2S_SCK/DCULITE_R5/TCON11
PM1/I2S_FS/DCULITE_R6
PM2/EMIOS1_17/DCULITE_R7/DCULITE_DE/RSDSLCK_N
PM3/CNRX_C/RXD_D/TCON4
PM4/CNTX_C/TXD_D/TCON5
PM12/DCULITE_B7/I2S_SCK
PM13/DCULITE_PCLK/SGM_MCLK
PN0/DCULITE_HSYNC/TCON4
PN1/DCULITE_VSYNC/TCON5
PN2/DCULITE_R0/RXD_C/PDI8_(VIU0)
PN3/DCULITE_R1/TXD_C/PDI9_(VIU1)
PN4/DCULITE_R2/TCON6
PN5/DCULITE_R3/TCON7
PN6/DCULITE_R4/TCON8
PN7/DCULITE_R5/TCON9
PN8/DCULITE_R6/TCON10
PN9/DCULITE_R7/TCON11
PN10/DCULITE_G0/RXD_D/PDI10_(VIU2)
PN11/DCULITE_G1/TXD_D/PDI11_(VIU3)
PN12/DCULITE_G2/EMIOS0_17
PN13/DCULITE_G3/EMIOS0_18
PN14/DCULITE_G4/EMIOS0_19
PN15/DCULITE_G5/EMIOS0_20
(PDI HSYNC/VIU9)
(PDI VSYNC/VIU8)
V_CLK
(PDI0)
(PDI1)
(PDI2)
(PDI3)
(PDI4)
(PDI5)
(PDI6)
(PDI7)
(CS)
(CLK)
(IO3)
To QuadSPI1
PK[0..11]
(IO2)
(VIU0)
(VIU1)
(VIU2)
(VIU3)
(VIU4)
C
PL[0..13]
V_RESET
V_PWR
(DE)
PM0
PM1
PM2
PM3
PM4
PM12
PM13
(B7)
(PCLK)
{9,11,12}
{11}
{11}
{7}
{10}
{10}
{7}
{7}
(HSYNC)
(VSYNC)
(R0)
(R1)
(R2)
(R3)
(R4)
(R5)
(R6)
(R7)
(G0)
(G1)
(G2)
(G3)
(G4)
(G5)
(G6)
(G7)
(B0)
(B1)
(B2)
(B3)
(B4)
(B5)
{7,8,11,12}
To QuadSPI1
PN[0..15]
{7}
B
PP[0..7]
PP0/DCULITE_G6/EMIOS0_21
PP1/DCULITE_G7/EMIOS0_22
PP2/DCULITE_B0/CNRX_C/PDI12_(VIU4)
PP3/DCULITE_B1/CNTX_C/PDI_DE
PP4/DCULITE_B2/EMIOS0_11
PP5/DCULITE_B3/EMIOS0_13
PP6/DCULITE_B4/EMIOS0_15
PP7/DCULITE_B5/I2S_FS
{7,8,11,12}
(B6)
{7}
PP[0..7]
0.1UF
AC6
AD6
AE6
AF6
AE15
D
(PDI DE)
PH[0..4]
PH0/TCK
PH1/TDI
PH2/TDO
PH3/TMS
PH4/PCS_A0/EMIOS1_21Q/DCULITE_G6
{7,11}
PN[0..15]
B
{8,9,11,12}
PE[0..7]
PD[0..15]
R27
PE[0..7]
12PF
DNP
1.0M
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
PC8/AN8
PC9/AN9
PC10/AN10(MUX)/I2S_DO
PC11/AN11/MA0/PCS_B2
PC12/AN12/MA1/PCS_B1
PC13/AN13/MA2/PCS_B0
PC14/AN14/EXTAL32
PC15/AN15/XTAL32
(B0)
PG0
(B1)
PG1
(B2)
PG2
(B3)
PG3
(B4)
PG4
(B5)
PG5
(B6)
PG6
(B7)
PG7
(VSYNC)
PG8
PG9 (HSYNC)
(DE)
PG10
PG11 (PCLK)
PG12
PL[0..13]
(M0C0M)
(M0C0P)
(M0C1M)
(M0C1P)
(M1C0M)
(M1C0P)
(M1C1M)
(M1C1P)
(M2C0M)
(M2C0P)
(M2C1M)
(M2C1P)
(M3C0M)
(M3C0P)
(M3C1M)
(M3C1P)
Y3
CLK_EXTAL32K_PC14
AC21
AC25
AC26
AC24
AD24
AD26
AD21
AD25
AE26
AE25
AE23
AE24
AF26
AF25
AF24
AF23
PD[0..15]
PF[0..15]
2
C29
PB0/CNTX_A/TXD_A
PB1/CNRX_A/RXD_A
PB2/TXD_A
PB3/RXD_A
PB4/SCK_B/MA0
PB5/SOUT_B/MA1/FABM
PB6/SIN_B/MA2/ABS[0]
PB7/SIN_A/EMIOS1_20/I2S_SCK
PB8/SOUT_A/EMIOS1_19Q/I2S_DO
PB9/SCK_A/EMIOS1_18/I2S_FS
PB10/CNRX_B/I2S_DO
PB11/CNTX_B/SGM_MCLK
PB12/RXD_B/EMIOS1_10/PCS_A2
PB13/TXD_B/EMIOS1_11Q/PCS_A1
E26
D26
D25
C25
C26
B26
A26
A25
T4
T2
T1
E23
A15
PK[0..11]
C
PC[0..13]
Need clock and Reset ccts
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
CLK_EXTAL32K_PC14
CLK_XTAL32K_PC15
PG0/DCU_B0/SCL_D/EMIOS0_21/RSDS8_P
PG1/DCU_B1/SDA_D/EMIOS0_22/RSDS8_N
PG2/DCU_B2/RSDS9_P
PG3/DCU_B3/RSDS9_N
PG4/DCU_B4/RSDS10_P
PG5/DCU_B5/RSDS10_N
PG6/DCU_B6/RSDS11_P
PG7/DCU_B7/RSDS11_N
PG8/DCU_VSYNC/TCON2
PG9/DCU_HSYNC/TCON1
PG10/DCU_DE/TCON3
PG11/DCU_PCLK/RSDSLCK_P
PG12/PCS_B0/PDI_DE/DCULITE_B7
MPC5645S 416BGA
SIGNALS
PC[0..13]
DCU_YU
DCU_XL
DCU_YD
DCU_XR
DCUL_YU
DCUL_XL
DCUL_YD
DCUL_XR
CLK_XTAL32K_PC15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
W4
V1
D21
A22
AF15
AC16
AF16
AC14
AF13
AC13
W2
Y4
AF7
AC8
PA0/DCU_R0/SDA_B/EMIOS0_18/RSDS0_P
PA1/DCU_R1/SCL_B/EMIOS0_17/RSDS0_N
PA2/DCU_R2/RSDS1_P
PA3/DCU_R3/RSRS1_N
PA4/DCU_R4/RSDS2_P
PA5/DCU_R5/RSDS2_N
PA6/DCU_R6/RSRS3_P
PA7/DCU_R7/RSDS3_N
PA8/DCU_G0/SCL_C/EMIOS0_20/RSDS4_P
PA9/DCU_G1/SDA_C/EMIOS0_19/RSDS4_N
PA10/DCU_G2/RSDS5_P
PA11/DCU_G3/RSDS5_N
PA12/DCU_G4/RSDS6_P
PA13/DCU_G5/RSDS6_N
PA14/DCU_G6/RSDS7_P
PA15/DCU_G7/RSDS7_N
PJ[0..15]
(SCK)
(DO)
(FS)
(DO)
(SYS_MCLK)
(RXD_1)
(TXD_1)
{9}
K26
K25
K23
J23
J26
J25
H26
G26
G25
G24
H23
G23
F26
F25
F24
F23
PB[0..13]
(CANTX_0)
(CANRX_0)
(TXD_0)
(RXD_0)
{7,9,12}
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PH[0..4]
{9,10,12}
(R0)
(R1)
(R2)
(R3)
(R4)
(R5)
(R6)
(R7)
(G0)
(G1)
(G2)
(G3)
(G4)
(G5)
(G6)
(G7)
PG[0..12]
PA[0..15]
{7}
EVTI
EVTO
MCKO
MDO11
MDO10
MDO9
MDO8
MDO7
MDO6
MDO5
MDO4
MDO3
MDO2
MDO1
MDO0
MSEO
MSEO2
A
GND
MPC5645S-416PKG
ICAP Classification:
Drawing Title:
FCP: ___
FIUO:
PUBI: ___
X
MPC5645S-DEMO-V2
Page Title:
MCU Peripherals
5
4
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
6
of
12
5
4
3
2
Sharp LQ043
3.3V_SR
1
Decoupling for U24
DVI-I_Dual_29
J44
DCU
{6}
P9
PA[0..15]
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
D
{6,11}
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
(R0)
(R1)
(R2)
(R3)
(R4)
(R5)
(R6)
(R7)
(G0)
(G1)
(G2)
(G3)
(G4)
(G5)
(G6)
(G7)
DCU_YD
DCU_XR
PG[0..12]
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
(B0)
(B1)
(B2)
(B3)
(B4)
(B5)
(B6)
(B7)
PG8
PG9
PG10
PG11
(VSYNC)
(HSYNC)
(DE)
(PCLK)
P12V
39
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
G1
G2
G3
G4
G5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
3.3V_SR
3.3V_SR
PG8
PG9
PG10
PG11
5.0V_SR
5.0V_SR
DCU_YU
DCU_XL
SH10
SH9
0
0
PK10
PK11
PG11
PG10
PG9
PG8
P12V
41
42
43
5.0V_SR
5.0V_SR
HDR_2X19_F
GND
GND
(PCLK)
(DE)
(HSYNC)
(VSYNC)
GND
GND
GND
TP24
TP25
TP26
TP27
C203
C204
C205
C206
C207
C208
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
56
57
GND
PG11
2
4
5
PG10
PG9
PG8
DSK_CTL3
DSK_CTL2
DSK_CTL1
CONN FPC/FFC 40
GND
3.3V_SR
GND
J42
PC[0..13]
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
C
R36
R37
R38
R39
R32
R33
R34
R35
DCU_YU
DCU_XL
DCU_YD
DCU_XR
DCUL_YU
DCUL_XL
DCUL_YD
DCUL_XR
560
560
0
0
560
560
0
0
1
GND
2
3
4VDD_30V_J42 SH8
DCU_YU
DCU_XL
DCU_YD
DCU_XR
DCUL_YU
DCUL_XL
DCUL_YD
DCUL_XR
6
7
8
13
15
14
9
35
3
10
DSK_EN
3.3V_SR
{6,9,12}
GND
U24
63
62
61
60
59
58
55
54
53
52
51
50
47
46
45
44
43
42
41
40
39
38
37
36
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
GND
DCU_PD
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
TX0+
TX0TX1+
TX1TX2+
TX2TXC+
TXCTFADJ
MSEN/PO1
CTL3/A3/DK3
CTL2/A2/DK2 TGND0
CTL1/A1/DK1 TGND2
ISEL/RST
TGND1
BSEL/SCL
DSEL/SDA
EDGE/HTPLG
560
R41
DCU_MSEN
3.3V_SR
GND
3.3V_SR
3.3V_SR
3.3V_SR
C5_2
C5_1
C4
C3
C2
C1
3.3V_SR
3.3V_SR
3.3V_SR
GND
GND
GND
GND
D
analog RTN2
analog RTN1
analog H-SYNC
analog BLUE
analog GRN
analog RED
S1
SHELL1
P10
SH11
0
GND
GND
GND
49
34
65
GND
GND
GND
8
7
6
5
3
4
DSK_EN
DSK_CTL3
DSK_CTL2
DSK_CTL1
R110
R111
R112
R113
10.0K
10.0K
10.0K
10.0K
DVI Config
3.3V_SR
3.3V_SR
3.3V_SR
3.3V_SR
GND1
1
2
3
4
SW_DIP-4/SM
GND
1
2
3
4
M2
GND
19
11
GND
SW5
J46
M1
DCU_TXCP
DCU_TXCM
GND
C
0
CON FPC/FFC 4
DCU_YU
DCU_XL
DCU_YD
DCU_XR
22
21
GND
TXCTXC+
TXC Shld
TX5+
TX5TX0/5 Shld
TX0+
TX0HP detect
GND
+5V
TX3+
TX3TX1/3 Shld
TX1+
TX1analog V-SYNC
DDC DATA
DDC CLK
TX4+
TX4TX2/4 Shld
TX2+
TX2-
TFP410PAP
DESKEW 12
GND
DCU_TX2P
DCU_TX2M
20
32
26
NC
RESERVED
EX_PAD
VDD_30V
DCU_TX1P
DCU_TX1M
31
30
16
48
64
17
DGND0
DGND1
DGND2
PGND
DKEN
VREF
PD
28
27
23
29
TVDD0
TVDD1
DE
HSYNC
VSYNC
DCU_TX0P
DCU_TX0M
18
PVDD
IDCKIDCK+
25
24
1
12
33
DVDD0
DVDD1
DVDD2
S2
SHELL2
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DVI-I
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
GND
3.3V_SR
3.3V_SR
(R0)
(R1)
(R2)
(R3)
(R4)
(R5)
(R6)
(R7)
(G0)
(G1)
(G2)
(G3)
(G4)
(G5)
(G6)
(G7)
(B0)
(B1)
(B2)
(B3)
(B4)
(B5)
(B6)
(B7)
J14
GND
GND
3.3V_SR
GND2
R114
R115
R53
10.0K
10.0K
10.0K
DVI ENABLE
DCU_PD 1
DCUL_PD 3
DCU_MSEN 5
CON 1X4
2
4
6
3.3V_SR
3.3V_SR
DCUL_MSEN
R109
10.0K
3.3V_SR
HDR 2X3
DVI-I_Dual_29
Sharp LQ043
{6}
{6}
PM2
PM13
{6}
PN[0..15]
PM2
PM13
{6}
{6,8,11,12}
{6}
PP[0..7]
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PJ0
PM12
PJ[0..15]
PM12
TP30 (HSYNC)
TP31 (VSYNC)
(R0)
(R1)
(R2)
(R3)
(R4)
(R5)
(R6)
(R7)
(G0)
(G1)
(G2)
(G3)
(G4)
(G5)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
DCUL_YD
DCUL_XR
(G6)
(G7)
(B0)
(B1)
(B2)
(B3)
(B4)
(B5)
(B6)
(B7)
P12V
39
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
G1
G2
G3
G4
G5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
PP2
PP3
PP4
PP5
PP6
PP7
PJ0
PM12
3.3V_SR
3.3V_SR
PN1
(HSYNC)
PN0
(DE)
PM2
PM13 (PCLK)
5.0V_SR
5.0V_SR
DCUL_YU
DCUL_XL
SH7
SH6
0
0
PK10
PK11
P12V
41
42
43
GND
PM13 (PCLK)
PM2 (DE)
PN0 (HSYNC)
PN1 (VSYNC)
HDR_2X19_F
GND
GND
5.0V_SR
5.0V_SR
VDD_30V
{6,8,11,12}
TP21
GND
GND
1
PK[0..11]
SHELL2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
GND
3.3V_SR
3.3V_SR
(R0)
PN2
(R1)
PN3
(R2)
PN4
(R3)
PN5
(R4)
PN6
(R5)
PN7
(R6)
PN8
(R7)
PN9
PN10 (G0)
PN11 (G1)
PN12 (G2)
PN13 (G3)
PN14 (G4)
PN15 (G5)
(G6)
PP0
(G7)
PP1
(B0)
PP2
(B1)
PP3
(B2)
PP4
(B3)
PP5
(B4)
PP6
(B5)
PP7
(B6)
PJ0
PM12 (B7)
P8
J43
P12V
GND
PM13 (PCLK)
CONN FPC/FFC 40
PK10
PK11
2
4
5
DSK_CTL3
DSK_CTL2
DSK_CTL1
6
7
8
13
15
14
9
GND
51.1K
VDD_30V_DRVC
VDD_30V_IPK
100uF
1
2
DRVC
IPK
VCC
0.1uF
1
GND
2
3
4VDD_30V_J41 SH5
DCUL_PD
35
3
10
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
MC33063ADG
TX2+
TX2TXC+
TXCTFADJ
MSEN/PO1
DVDD0
DVDD1
DVDD2
PVDD
TVDD0
TVDD1
IDCKIDCK+
DGND0
DGND1
DGND2
PGND
DE
HSYNC
VSYNC
CTL3/A3/DK3
CTL2/A2/DK2 TGND0
CTL1/A1/DK1 TGND2
ISEL/RST
TGND1
BSEL/SCL
DSEL/SDA
EDGE/HTPLG
DKEN
VREF
PD
NC
RESERVED
EX_PAD
DCUL_TX0P
DCUL_TX0M
28
27
DCUL_TX1P
DCUL_TX1M
31
30
DCUL_TX2P
DCUL_TX2M
22
21
DCUL_TXCP
DCUL_TXCM
19
11
560
R43
3.3V_SR
DCUL_MSEN
1
12
33
18
GND
GND
GND
3.3V_SR
3.3V_SR
3.3V_SR
C5_2
C5_1
C4
C3
C2
C1
3.3V_SR
23
29
3.3V_SR
3.3V_SR
16
48
64
17
GND
GND
GND
GND
20
32
26
GND
GND
GND
49
34
65
GND
B
analog RTN2
analog RTN1
analog H-SYNC
analog BLUE
analog GRN
analog RED
SHELL1
S1
P11
SH12
0
GND
GND
TFP410PAP
VDD_30V
GND
3.3V_SR
0
A
C209
C210
C212
C211
C213
C214
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
J45
L10
M1
GND
DCUL_YU
DCUL_XL
DCUL_YD
DCUL_XR
1500PF
GND
2
0.1UF
1
2
3
4
270UH
M2
GND
GND1
GND
1
2
3
4
Decoupling for U25
FCP: ___
FIUO:
X
PUBI: ___
Page Title:
Displays
GND2
GND
3
ICAP Classification:
Drawing Title:
MPC5645S-DEMO-V2
CON 1X4
4
TX1+
TX1-
25
24
CON FPC/FFC 4
100uF
5
TX0+
TX0-
S2
TXCTXC+
TXC Shld
TX5+
TX5TX0/5 Shld
TX0+
TX0HP detect
GND
+5V
TX3+
TX3TX1/3 Shld
TX1+
TX1analog V-SYNC
DDC DATA
DDC CLK
TX4+
TX4TX2/4 Shld
TX2+
TX2-
GND
TCAP
4
C33
C37
8
7
6
1.5 OHM
C201
+
3
SWC
SWE
1
VDD_30V_TCAP
180
COMP
3.3V_SR
C216
J41
GND
A
R30
C215
+
U17
5
GND
A VDD_30V_SWC
1N5819
R107
2.21K
R31
DSK_EN
C
R106
56
57
(DE)
PM2
PN0 (HSYNC)
PN1 (VSYNC)
GND
3.3V_SR
D13
VDD_30V_FB
GND
U25
63
62
61
60
59
58
55
54
53
52
51
50
47
46
45
44
43
42
41
40
39
38
37
36
PP2
PP3
PP4
PP5
PP6
PP7
PJ0
PM12
PN10
PN11
PN12
PN13
PN14
PN15
PP0
PP1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DVI-I
B
(DE)
(PCLK)
TP28
TP29
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
PN10
PN11
PN12
PN13
PN14
PN15
DCULITE
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
7
of
12
5
4
3
2
1
D[0..31]
A[0..12]
U14A
Ensure length of
each address and
control line is the
same after the
trace split
Place all resistors close to MCU
MPC5645S
416BGA
DDR
SIGNALS
Place all resistors close to MCU
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
C
RN1A
RN1B
RN1C
RN1D
RN1E
RN1F
RN1G
RN1H
RN2A
RN2B
RN2C
RN2D
RN2E
RN2F
RN2G
RN2H
RN3A
RN3B
RN3C
RN3D
RN3E
RN3F
RN3G
RN3H
RN4A
RN4B
RN4C
RN4D
RN4E
RN4F
RN4G
RN4H
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
R1
P1
P4
N1
N4
M1
M4
L4
L1
K1
K4
J1
H4
H1
G4
G1
F1
E1
E4
D1
D2
D3
D4
C1
C4
B1
A1
A2
A3
A4
A5
A6
R_D0
R_D1
R_D2
R_D3
R_D4
R_D5
R_D6
R_D7
R_D8
R_D9
R_D10
R_D11
R_D12
R_D13
R_D14
R_D15
R_D16
R_D17
R_D18
R_D19
R_D20
R_D21
R_D22
R_D23
R_D24
R_D25
R_D26
R_D27
R_D28
R_D29
R_D30
R_D31
A10
B10
C10
D10
A11
D11
A12
B12
A13
B13
C13
D13
A14
D14
D15
B15
DDR_ADDRESS[0]
DDR_ADDRESS[1]
DDR_ADDRESS[2]
DDR_ADDRESS[3]
DDR_ADDRESS[4]
DDR_ADDRESS[5]
DDR_ADDRESS[6]
DDR_ADDRESS[7]
DDR_ADDRESS[8]
DDR_ADDRESS[9]
DDR_ADDRESS[10]
DDR_ADDRESS[11]
DDR_ADDRESS[12]
DDR_ADDRESS[13]
DDR_ADDRESS[14]
DDR_ADDRESS[15]
D
DDR_DQ[0]
DDR_DQ[1]
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[4]
DDR_DQ[5]
DDR_DQ[6]
DDR_DQ[7]
DDR_DQ[8]
DDR_DQ[9]
DDR_DQ[10]
DDR_DQ[11]
DDR_DQ[12]
DDR_DQ[13]
DDR_DQ[14]
DDR_DQ[15]
DDR_DQ[16]
DDR_DQ[17]
DDR_DQ[18]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[21]
DDR_DQ[22]
DDR_DQ[23]
DDR_DQ[24]
DDR_DQ[25]
DDR_DQ[26]
DDR_DQ[27]
DDR_DQ[28]
DDR_DQ[29]
DDR_DQ[30]
DDR_DQ[31]
R_A0
R_A1
R_A2
R_A3
R_A4
R_A5
R_A6
R_A7
R_A8
R_A9
R_A10
R_A11
R_A12
R118
R119
R120
R121
R122
R123
R124
R125
R126
R127
R128
R129
R130
U7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
22
22
22
22
22
22
22
22
22
22
22
22
22
Place all resistors close to MCU
DDR_BA[0]
DDR_BA[1]
DDR_BA[2]
DDR_DM[0]
DDR_DM[1]
DDR_DM[2]
DDR_DM[3]
DDR_DQS[0]
DDR_DQS[1]
DDR_DQS[2]
DDR_DQS[3]
A7
A8
A9
R71
R70
20
20
BA0
BA1
P3
K3
G3
B4
R11
R12
R13
R14
20
20
20
20
DR_DM0
DR_DM1
DR_DM2
DR_DM3
N2
K2
G2
B3
R16
R17
R18
R19
20
20
20
20
DR_DQ0
DR_DQ1
DR_DQ2
DR_DQ3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
J8
J9
K7
K8
K2
K3
J1
J2
J3
H1
J7
H2
H3
BA0
BA1
H8
H9
DR_CLK_P G2
DR_CLK_N G3
H7
G9
G8
G7
G1
F2
F8
E2
E8
DR_CS
DR_RAS
DR_CAS
DR_WEB
DR_CKE
DR_DM1
DR_DM0
DR_DQ1
DR_DQ0
DR_CLK_P
F3
F7
D9
R20
C7
D7
DDR_DRAM_CLK
DDR_DRAM_CLK
D8
D9
D5
DDR_CKE
DDR_CS
DDR_ODT
R74
R75
20
20
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA1
CK
CK
DR_CLK_N
NC_1
NC_2
TEST
R73
R72
R69
20
20
20
J4
2
4
R80
1% 0.5 BCP68_BASE
1
C
B
C83
3
AA3 VRC_CTRL
J24
D24
AA2
AC1
VPP
E
VDD12
Q1
BCP68
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
J8
J9
K7
K8
K2
K3
J1
J2
J3
H1
J7
H2
H3
BA0
BA1
H8
H9
3300PF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
R62
R82
0
R81
0
GND
3.3V_SR
GND
Pull down
recommended for
1st silicon
DR_CLK_P G2
DR_CLK_N G3
10.0K
GND
R105
PJ[0..15]
PF[0..15]
{6,7,11,12}
PK[0..11]
C185
+
9
Vddq
PVin
Vref
C195
0.047UF
0.047UF
4
DM_VTT_DDR2
Vsense
Vtt
3
8
LP2997MR
GND
C183
+
C198
F3
F7
D9
GND
C197
47UF
220uF
0.01uF
0.1UF
C77
C73
C80
C81
C75
C69
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
GND
A9
F9
K9
1.8V_SR
A3
B9
C1
E1
C70
C62
0.1UF
0.1UF
A1
F1
K1
GND
C
BA0
BA1
CK
CK
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
CS
RAS
CAS VDD_1
WE
VDD_2
CKE VDD_3
UDM
LDM VSSQ_1
UDQSVSSQ_2
LDQS VSSQ_3
VSSQ_4
NC_1
NC_2
TEST
VSS_1
VSS_2
VSS_3
A8
B7
B8
C7
C8
D7
D8
E7
E3
D2
D3
C2
C3
B2
B3
A2
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
1.8V_SR
1.8V_SR
A7
B1
C9
D1
E9
C76
C72
C78
C79
C74
C68
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
A9
F9
K9
GND
1.8V_SR
A3
B9
C1
E1
B
A1
F1
K1
C66
C63
0.1UF
0.1UF
GND
DM_VTT_DDR2
GND
PJ13
PJ14
PJ15
PK1
(CS)
(CLK)
(IO3)
(IO2)
PF5
PF6
(IO1)
(IO0)
GND
GND
GND
GND
C217
C218
C219
C220
0.1UF
0.1UF
0.1UF
0.1UF
GND
To QuadSPI1
3.3V_SR
A
7
16
CS
SCK
3
4
5
6
11
12
13
14
C91
PF6
PF5
PK1
PJ15
15
8
9
1
PJ13
PJ14
7
16
VCC
DNC3
DNC4
DNC5
DNC6
DNC11
DNC12
DNC13
DNC14
2
U18
SI/IO0
SO/IO1
W/ACC/IO2
HOLD/IO3
10
PF10
PF15
15
8
9
1
SI/IO0
SO/IO1
W/ACC/IO2
HOLD/IO3
0.1UF
S25FL064P
CS
SCK
10
PF13
PF14
PF11
PF12
VCC
2
To QuadSPI0
GND
(CS)
(IO2)
(IO3)
(IO0)
(IO1)
(CLK)
GND
GND
3.3V_SR
PF10
PF11
PF12
PF13
PF14
PF15
1.8V_SR
A7
B1
C9
D1
E9
MT46H16M16LFBF-6
GND
{6,9,11,12}
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
PJ10
PJ11
PJ12
SD
AVin
GND1GND2
5
7
1
{6,7,11,12}
2
6
DM_VREF
C194
H7
G9
G8
G7
G1
F2
F8
E2
E8
DR_CS
DR_RAS
DR_CAS
DR_WEB
DR_CKE
DR_DM3
DR_DM2
DR_DQ3
DR_DQ2
GND
1.8V_SR
1.8V_SR
U8
V_REG
DM_VREF
MPC5645S-416PKG
B
D
Place capacitors close to corners of DRAM
DR_CAS
DR_RAS
DR_WEB
DM_VTT_DDR2
R2
M2
J2
F2
MVTT0
MVTT1
MVTT2
MVTT3
GND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
MT46H16M16LFBF-6
GND
B6
B7
B9
DDR_CAS
DDR_RAS
DDR_WE
VRC_CTRL
VREF_RSDS1
VREF_RSDS2
VREG_BYPASS
VSUP_TEST
U23
VSS_1
VSS_2
VSS_3
A8
B7
B8
C7
C8
D7
D8
E7
E3
D2
D3
C2
C3
B2
B3
A2
GND
MVREF
10.0K
DM_VTT_SD_B
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
CS
RAS
CAS VDD_1
WE
VDD_2
CKE VDD_3
UDM
LDM VSSQ_1
UDQSVSSQ_2
LDQS VSSQ_3
VSSQ_4
100
DR_CKE
DR_CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U21
DNC3
DNC4
DNC5
DNC6
DNC11
DNC12
DNC13
DNC14
3
4
5
6
11
12
13
14
C139
A
0.1UF
S25FL064P
ICAP Classification:
Drawing Title:
FCP: ___
FIUO:
PUBI: ___
X
MPC5645S-DEMO-V2
Page Title:
Memory
GND
GND
5
4
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
8
of
12
5
4
{6,7,12}
{6}
3
2
1
PC[0..13]
PD[0..15]
(M0C0M)
(M0C0P)
(M0C1M)
(M0C1P)
(M1C0M)
(M1C0P)
(M1C1M)
(M1C1P)
(M2C0M)
(M2C0P)
(M2C1M)
(M2C1P)
(M3C0M)
(M3C0P)
(M3C1M)
(M3C1P)
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
D
{6,11,12}
PC10
PC11
PC12
PC13
5.0V_SR
P6
1
3
5
7
9
11
13
PC10
PL0
GND
PD3
PD2
PD1
PD0
(M0C1P)
(M0C1M)
(M0C0P)
(M0C0M)
2
4
6
8
10
12
14
(M1C0M)
(M1C0P)
(M1C1M)
(M1C1P)
PD4
PD5
PD6
PD7
{6,9,10,12}
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB12
PB13
PL1
PC11
5.0V_SR
CON_2X7
P5
PD11
PD10
PD9
PD8
(M2C1P)
(M2C1M)
(M2C0P)
(M2C0M)
PL[0..13]
PL0
PL1
PL2
PL3
PC12
PL2
1
3
5
7
9
11
13
Decap
for U20
2
4
6
8
10
12
14
D
PL3
PC13
PD12
PD13
PD14
PD15
{6,8,9,11,12}
(M3C0M)
(M3C0P)
(M3C1M)
(M3C1P)
PF[0..15]
PF[0..15]
PF1
PF2
PF3
PF5
PF6
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
CON_2X7
GND
V_AN
V_AN
C223
V_AN
Decap
for U22
Place jack connectors
beside each other
0.1UF
V_AN
C222
C146
0.1UF
1000PF
C156
LMH6645MF
1.0K
C157
-IN
43K
1000PF
1
C181
10nF
C133
R104
U11
1.0K
19.6K
C131
0.1UF
LMH6645MF
GND
1000PF
R92
LINE OUT
GND
R97
14
R101
12.1K
0.1UF
5
4
VDDA
VOUT
15.4K
30
+IN
5
U22
3
R99
R98
VDDD
C147
15.4K
32.4K
C
3.3V_SR
20
R95
R90
V+
R100
1
R91
-IN
V-
+IN
VOUT
4
3.3V_SR
GND
2
3
5
27K
15.8K
GND
1000PF
V+
R94
U20
V-
27K
2
R93
VDDIO
C
R96
PB[0..13]
LINEIN_L
LINEOUT_L
12
C167
1UF
GND
4
2
10.0K
13
1.62K
LINEIN_R
LINEOUT_R
11
C142
J34
1
3
1UF
R
L
AUD 4
External amplifier connection
GND
GND
C148
{6,9,10,12}
PB[0..13]
10nF
PB[0..13]
PB7 (SCK)
PB8 (DO)
PB9 (FS)
PB10 (DO)
15
MIC
HP_L
MIC_BIAS
HP_R
AUDIO OUT
6
B
16
3.3V_SR
4
2
{6,8,9,11,12}
PF[0..15]
R117
4.70K DNP
R116
4.70K DNP
HP_VGND
PF4
(SDA_1)
27
PF7
(SCL_1)
29
4
J30
1
3
2
HP_VGND
B
R
L
AUD 4
Headphone connection
CTRL_DATA
CTRL_CLK
VAG
10
C143
GND GND
AGND
GND1
GND2
28
22
19
17
9
8
7
1
3
GND3-PAD
SYS_MCLK
SGTL5000 32QFN
A
NC6
NC5
NC4
NC3
NC2
NC1
I2S_SCLK
CTRL_MODE
21
PB11
GND
I2S_LRCLK
33
24
32
23
0.1UF
CPFILT
18
I2S_DIN
CTRL_ADR0_CS
26
I2S_DIN
I2S_DOUT
31
25
GND GND GND GND
A
Star wire grounds to single
then connect to plane
ICAP Classification:
Drawing Title:
FCP: ___
FIUO:
PUBI: ___
X
MPC5645S-DEMO-V2
Page Title:
Audio and Motors
5
4
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
9
of
12
5
4
2
1
CAN, LIN, UART, USB/SPI
UART PK7, PK8
{6,9,12}
3
PB[0..13]
D
D
PB0
PB1
PB12
PB13
PB3
PB2
(CANTX_0)
(CANRX_0)
(RXD_1)
(TXD_1)
J17
USB_RXD_0 1
3
5
(RXD_0)
(TXD_0)
2
4
6
USB_TXD_0
HDR 2X3
{12}
DBG_RXD_0
DBG_RXD_0
{12}
DBG_TXD_0
DBG_TXD_0
PM3
PM4
PM3
PM4
5.0V_SR
J20
1
4
C39
47PF
DNP
47PF
DNP
27
8
7
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
31
14
42
3
46
USBDM
USBDP
5
1.5K
4
ACBUS0
ACBUS1
ACBUS2
ACBUS3
SI/WUA
CLK_XTIN_6M
43
CLK_XTOUT_6M
44
R46
10.0K
48
1
2
47
TEST
BCBUS0
BCBUS1
BCBUS2
BCBUS3
SI/WUB
45
B
EECS
EESK
EEDATA
GND1
GND2
GND3
GND4
GND
XTOUT
R9
10.0K GND
3
5.0V_SR
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
XTIN
AGND
X1
6 MHZ
2
RESET#
9
18
25
34
R1
1
GND
1.0M
4.70K
RSTOUT#
PWREN#
1000PF
0.1UF
1000PF
3.3V_SR
GND
GND
1
3
5
BUS0
BUS1
BUS2
BUS3
BUS4
BUS5
2
4
6
HDR 2X3
C49
C45
0.1UF
1000PF
3.3V_SR
U2
R49
15
13
12
11
10
GND
J16
2
1
HDR 1X2
7
8
C0_INH
C0_ERR_B
9
10.0K
40
39
38
37
36
35
33
32
1
4
(CANTX_0)
(CANRX_0)
PB0
PB1
USB_RXD_0
USB_TXD_0
14
6
C0_WAKE
C0_STB
3.3V_SR
3.3V_SR
INH
ERR
3.3V_SR
1
3
5
2
4
6
CAN_0
CANH
WAKE
CANL
TXD
RXD
STB
EN
TJA1041T
J13
R15
30
29
28
27
26
41
C43
0.1UF
C
GND
24
23
22
21
20
19
17
16
C41
GND
J6
VCCIOB
VCCIOA
VCC2
3V3OUT
GND
R2
USB_TYPE_B
GND
GND
C56
J5
M1
13
1
6
2
7
3
8
4
9
5
CAN0-CANH
12
CAN0-CANL
R42
R45
60.4
60.4
11
SPLIT
1
R8
USB_RN
USB_RP
R47
C38
0.1UF
C48
5
10
3
27
6
VCC1
3
2
3
2
R7
0.033UF
AVCC
U5
C55
GND
USB_N
USB_P
CAN-12V
CAN_12V
GND
C54
0.1UF
S2
2
3
4
1
S1
HDR 1X2
P12V
10UF
BGX50A
GND
J1
-D
+D
G
V
0.1UF
470
0.1UF
L1
470OHM
DNP
C58
C57
0.1UF
VI/O
VBAT
VCC
D3
C64
C59
GND
D4
4
C44
+
L3
470OHM
DNP
2
One cap per power pin
GND
M2
GND
2
D2
DB9
C36
C0_EN
PM4
GND
0.01uF
5.0V_SR
HDR 2X3
10.0K
R10
GND
B
10.0K
C51
LIN_1
FT2232D
C50
1000PF
GND
PM3
2
(TXD_1)
PB13
4
(RXD_1)
PB12
1
10.0K
0.1UF
J3
INH
8
1
2
3
4
GND
SLP
TXD
RXD
5
GND
WAKE
GND
R48
BAT
U4
3
LIN
6
CON PLUG 4
D1
A
C
R40
1.0K
GND
LIN Molex Connector
TJA1020T
1
2
1
2
3.3V_SR
R50
D3
D1
7
1
C
GND
5.0V_SR
CAN0
USB/Serial Interface
1
2
{6}
{6}
HDR 1X2
GF1A
Master Mode Pullup
J7
GND
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO:
PUBI: ___
X
MPC5645S-DEMO-V2
Page Title:
Serial Interface
5
4
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
10
of
12
5
4
3
2
1
VIDEO IN
PJ[0..15]
D
TP12
{6,7,8,12}
D
TP11
J24
2
R61
2
1_1
1_2
1_3
36
C85
0.1UF
PK[0..11]
{6,7,8,12}
PL[0..13]
{6,9,12}
PF[0..15]
{6,8,9,12}
R67
TVS1
0402ESDA-MLP
CONN RCA 4
39.0
1
U9
GND
GND
GND
GND
GND
GND
GND
1.8V_SR
C11
C12
0.082UF
10nF
R63
R64
R65
R66
R68
PF8
PF9
(SDA_0)
(SCL_0)
R76
R79
33
33
GND
COMP_IN
10.0K
10.0K
10.0K
10.0K
10.0K
35
36
46
47
48
49
PF8_R
PF9_R
53
54
52
PM1
PM0
PWRDWN_B
RESET_B
30
9
20
22
21
V_CLK PJ3
47PF
ELPF
SFL
LLC
XTAL1
XTAL2
1
4
1.69K
C
GND2
GND1
2
3
KEEP CLOSE TO THE
ADV7180 AND ONTHE SAME
SIDE OF PCB AS THE
ADV7180.
C108
GND
Y1
28.63636MHZ
27
28
33
41
42
44
45
50
R22
1.0M
47PF
{6}
{6}
PM0
PM1
R77
R78
10.0K
10.0K
GPO0
GPO1
GPO2
GPO3
26
25
19
18
17
16
15
14
8
7
6
5
62
61
60
59
PVDD
AVDD
DVDD1
DVDD2
TEST_0
DGND1
DGND2
DGND3
DGND4
DVDDIO1
DVDDIO2
PJ3
PK4
PK5
PK6
PL4
PL5
PL6
PL7
PL8
V_CLK
HDR TH 1X3
2
64
63
1
3
2
1
VIN_HS
VIN_VS
VIN_F
PF2
DNP
KEEP VREFN AND VREFP CAPACITORS AS CLOSE
ASPOSSIBLE TO THE ADV7180 AND ON THE SAMESIDE
OF THE PCB AS THE ADV7180
PF2
PF8
PF9
J31
13
12
56
55
C
C10
1.8V_SR
0.1UF
C6
VREFP
VREFN
AGND1
AGND2
AGND3
34
3
10
24
57
V_RESET PM0
V_PWR
PM1
HS
VS
FIELD
INTRQ_B
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
32
37
43
GND
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
SDATA
SCLK
ALSB
29
51
V_PWR
V_RESET
R21
C90
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
38
39
C7
0.1UF
31
40
0.1UF
GND
GND
23
58
3.3V_SR
4
11
C16
C14
C9
C8
C15
0.1UF
10nF
0.1UF
10nF
0.1UF
GND
GND
GND
GND
C13
10nF
GND
GND
ADV7180
C18
C20
C17
0.1UF
10nF
0.1UF
C19
GND
GND
10nF
GND
GND
GND
GND
GND
B
B
Camera input port
P4
(VIU0)
(VIU1)
(VIU2)
(VIU3)
(VIU4)
(VIU5)
(VIU6)
(VIU7)
(VIU8)
(VIU9)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
PK2
PK3
PK4
PK5
PK6
PL4
PL5
PL6
PL7
PL8
(VIU CLK) PJ3
P12V
39
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
G1
G2
G3
G4
G5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
PJ10
PJ11
(PDI0)
(PDI1)
(PDI2)
(PDI3)
(PDI4)
(PDI5)
(PDI6)
(PDI7)
Place close to MCU
3.3V_SR
3.3V_SR
3.3V_SR
(PDI VSYNC/VIU8)
PJ2
(PDI HSYNC/VIU9)
PJ1
PG12 (PDI DE)
PL9 (PDI_CLK)
5.0V_SR
5.0V_SR
PG[0..12]
R83
R85
33
33
(SDA_0)
(SCL_0)
{6,7}
R44
4.70K DNP
R25
4.70K DNP
PF8
PF9
P12V
41
42
43
HDR_2X19_F
GND
GND
A
A
ICAP Classification:
Drawing Title:
FCP: ___
FIUO:
PUBI: ___
X
MPC5645S-DEMO-V2
Page Title:
Video Input
5
4
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
11
of
12
5
4
3.3V_SR
3
3.3V_SR
2
C34
USB Debug Interface
3.3V_SR
C221
Decap
for U19
0.1UF
C35
U19
1
2
3
4
5
6
7
8
9
10
PH2
JM_TDI
JM_TMS
D
JM_TCK1
JM_TCK2
R87
47PF
4.70K
JM_RSTOUT
RESET_B
VCC
OE
B0
B1
B2
B3
B4
B5
B6
B7
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
20
19
18
17
16
15
14
13
12
11
External Debugger Interface
Place CAPS as close to
connector pins
DNP
R88
GND
1
J12
10.0K
1
3
5
JM_TDO
PH1
PH3
PH0
2
4
6
47PF
DNP
JM_EN
JM_RST_B
JM_RSTIN
GND
3.3V_SR
JM_RST_B {6}
{6,12}
PH[0..4]
P1
PH1
PH2
PH0
HDR 2X3
{6}
RESET_B
RESET_B
3.3V_SR
J8
MC74HC245ADT
2
1 R51
GND
D
1
3
5
7
9
11
13
TDI
TDO
TCK
EVTI_B
(RDY)
2
4
6
8
10
12
14
CON_2X7
10.0K
(VSS)
(VSS)
(VSS)
(N/C)
TMS
(VSS)
JCOMP
GND
JTAG
{10}
DBG_RXD_0
DBG_RXD_0
{10}
DBG_TXD_0
DBG_TXD_0
HDR 1X2
TDO pull up
3.3V_SR
3.3V_SR
3.3V_SR 3.3V_SR
PH3
Driver MUST keep USBVREN bit OFF
10nF
0.1UF
0.1UF
DBG_RXD_0
DBG_TXD_0
GND
JM_TCK1
JM_TDO
JM_TDI
JM_TCK2
JM_EN
5.0V_SR
D2
D1
2
18pF
C88
18pF
R4
R3
1
4
R6
C40
PTB0/MISO2/ADP0
PTB1/MOSI2/ADP1
PTB2/SPSCK2/ADP2
PTB3/SS2/ADP3
PTB4/KBIP4/ADP4
PTB5/KBIP5/ADP5
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF4/TPM2CH0
PTF5/TPM2CH1
JM60_EXTAL
20
18
19
GND
JM_USB_RN
JM_USB_RP
27
27
21
22
34
35
37
38
PTG0/KBIP0
PTG1/KBIP1
PTG2/KBIP6
PTG3/KBIP7
PTG4/XTAL
PTG5/EXTAL
PTD0/ADP8/ACMP+
PTD1/ADP9/ACMPPTD2/KBIP2/ACMPO
VUSB33
USBDN
USBDP
10.0K
C42
47PF
DNP
{6,8,9,11,12}
10.0K
10.0K
10.0K
3.3V_SR
23
24
25
26
27
28
R5
47PF
DNP
IRQ/TPMCLK
RESET
BKGD/MS
NEXUS
R55
BRD_ID0
JM_TMS
BRD_ID1
P3
R134
40
41
42
43
1
44
BRD_REV0
BRD_REV1
BRD_REV2
JM_RSTOUT
18K
R57
GND
R54
29
30
33
0
3.3V_SR
R56
GND
10.0K
10.0K
JM_RSTIN
2
3
36
R52
TP8
TP7
TP6
10.0K
TP5
GND
J10
1
3
5
2
4
6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
R133
TP4
10.0K GND
USB_TYPE_B
USB_OSBDM
PF[0..15]
(PF15 CLKOUT)
3.3V_SR
PTC0/SCL
PTC1/SDA
PTC2
PTC3/TxD2
PTC4
PTC5/RxD2
39
17
32
3
2
G
V
JM_USB_N
JM_USB_P
JM60_XTAL
R60
10M
GND
Y4
XTAL 4MHZ HCM49
J2
S2
2
3
4
1
S1
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
PTE4/MISO1
PTE5/MOSI1
PTE6/SPSCK1
PTE7/SS1
R131
P12V_R
VSSOSC
VSS1
VSSAD/VREFL
3
C87
GND
-D
+D
U6
R132
D3
BGX50A
2
D4
L2
470OHM
DNP
GND
4
1
1
2
4
5
6
7
1
D4
8
9
10
11
12
13
14
15
R58
GND
MDO9
(Vendor I/O 2)
RESET_B
TDO
MDO10
TCK
TMS
TDI
JCOMP (TRST)
MDO11
(Tool I/O 3)
(Tool I/O 2)
(Tool I/O 1)
UBATT
UBATT
(Tool I/O 0)
VALTREF
39
40
3.3V_SR
HDR 2X3
GND
JM60_BDM
MC9S08JM60CLD
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
G1
G2
NEXUS Conenctor (MICTOR)
C
TMS
LINFlex3 to USB
C71
16
31
C60
VDD1
VDDAD/VREFH
C61
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
G3
G4
G5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
10.0K
(CLKOUT)
MDO8
PF15
EVTI_B
VREF
(RDY)
MDO7
MDO6
MDO5
MDO4
MDO3
MDO2
MDO1
MDO0
EVTO_B
MCKO
MSEO[1]
MSEO[0]
C
TP10
EVTI_B {6}
EVTO_B {6}
MCKO {6}
MSEO2_B {6}
MSEO_B {6}
41
42
43
HDR_2X19_F
G1..G5 = MICTOR
Centre Ground Pins
MDO[0..11]
{6}
GND
15.4K
GND
GND
GND
{6,7,9}
B
PC[0..13]
J48
PC8
GND
PC9
B
1
2
3
General Purpose I/O Interfaces
HDR TH 1X3
PE[0..7]
J47
(M4C0M)
(M4C0P)
(M4C1M)
(M4C1P)
(M5C0M)
(M5C0P)
(M5C1M)
(M5C1P)
1
3
5
7
9
11
13
15
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
2
4
6
8
10
12
14
16
3.3V_SR
HDR_2X8
PF[0..15]
{6,7,8,11}
PK[0..11]
R86
100
100
A
{6,8,9,11,12}
3.3V_SR
R84
A
{6}
D6
D7
LED GREEN
LED RED
{6,9,11}
PF0
PF1
PF3
PL[0..13]
PL10
PL11
PL12
PL13
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
SW_PK0
SW_PF0
SW_PF1
SW_PF3
SW_PL10
SW_PL11
SW_PL12
SW_PL13
C
eMIOS1[18]
J32
C
PK0
EVQ-WKA001
1
2
3
4
5
6
7
8
HDR_2X8
A
{6,9,10}
{6,12}
{6,7,8,11}
PB[0..13]
PH[0..4]
PJ[0..15]
SW4
J23
1
3
5
7
9
11
13
15
PK7
PK8
PK9
PB4
PB5
PB6
PH4
PJ12
2
4
6
8
10
12
14
16
SW_PK7
SW_PK8
SW_PK9
3.3V_SR
GND
eMIOS1[19]
1
2
3
4
8
7
6
5
GND
NC1
B
SW1
SW2
SW1_5
COM
A
NC2
SW8
Jog Encoder
EVQ-WKA001
1
2
3
4
5
6
7
8
WKUP10
GND
NC1
B
SW1
SW2
SW1_5
COM
A
NC2
EIF8
A
SW9
Jog Encoder
ICAP Classification:
Drawing Title:
SW_PJ12
GND
4
FIUO:
PUBI: ___
X
Page Title:
Debug
HDR_2X8
5
FCP: ___
MPC5645S-DEMO-V2
SW_DIP-4/SM
3
2
Size
C
Document Number
Date:
Friday, January 11, 2013
Rev
B
SCH-27293 PDF: SPF-27293
Sheet
1
12
of
12
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Document Number: MPC5645SDEMOUG
Rev. 0,09/2012
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