PHILIPS TEA0679

INTEGRATED CIRCUITS
DATA SHEET
TEA0679T
I2C-bus controlled dual Dolby*
B-type noise reduction circuit for
playback applications
Product specification
Supersedes data of 1998 Jun 24
File under Integrated Circuits, IC01
1998 Nov 12
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
FEATURES
• Dual Noise Reduction (NR) channels
• Head preamplifiers
• Reverse head switching
• Automatic Music Search (AMS)
• Blank skip
For both modes the delay time can be fixed by using an
external resistor. In the blank skip mode the IC can detect
pauses of music during playback and allows a
microcontroller to react on this situation.
• Mute position
• Equalization with electronically switched time constants
• Switch functions and level adjustment controlled via
I2C-bus
The equalization amplifier gain adjustment, the output
offset adjustment and all switching functions are I2C-bus
controlled. Head switching and equalization time constant
switching can be controlled via separate pins (optional).
The device operates with power supplies from 7.6 to 12 V.
The output overload level increases with increases in
supply voltage.
• Optional switch inputs TTL compatible
• Dolby reference level = 387.5 mV
• Contained in a 32-pin small outline package
• Improved EMC behaviour.
Current drain varies with the following variables:
GENERAL DESCRIPTION
• Supply voltage
The TEA0679T is a bipolar integrated circuit that provides
two channels of Dolby B noise reduction for playback
applications in car radios. It includes head and
equalization amplifiers with electronically switchable time
constants. The device also includes electronically
switchable inputs for tape drivers with reverse heads.
• Noise reduction on/off
• AMS on/off.
Because of this current drain variation it is advisable to use
a regulated power supply or a supply with a long time
constant.
This device detects pauses of music in the Automatic
Music Search (AMS) scan mode (for applications with an
intelligent controlled tape driver) or AMS latch mode (for
applications with a simple controlled tape driver).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC
supply voltage
7.6
−
12
V
ICC
supply current
−
35
40
mA
S+N
-------------N
signal plus noise-to-noise ratio
78
84
−
dB
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
TEA0679T
SO32
DESCRIPTION
plastic small outline package; 32 leads; body width 7.5 mm
VERSION
SOT287-1
Remark Dolby*: Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111,
USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby
Laboratories Licensing Corporation.
1998 Nov 12
2
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390 kΩ
100 nF
(±10%)
330 nF
(±10%)
270 kΩ
(±10%)
15 nF
(±5%)
4.7 nF
(±5%)
24 kΩ
(±2%)
180 kΩ
(±10%)
470
pF
8.2
nF
5.6
kΩ
HS
(opt)
BEN
SDA
SCL
DGND AMS
OUTB
INTB
CONTRB
HPB
SCB
EQB
EQFB
AGND
32
31
30
29
27
26
25
24
23
22
21
20
28
LATCH
AND
RISE TIME
MUTE
3
LEVEL
DETECTOR
PRE
AMP
EQ
AMP
1
2
3
4
5
6
7
8
9
10
11
12
13
MAD
BSC
TD
BTC
EQS
OUTA
INTA
CONTRA
HPA
SCA
EQA
EQFA
VCC
220 nF
47 nF
(±10%)
330 nF
(±10%)
100 nF
(±10%)
15 nF
(±5%)
8.2
nF
4.7 nF
(±5%)
15
16
Vref
INA2
100
µF
5.6
kΩ
24 kΩ
(±2%)
180 kΩ
(±10%)
14
INA1
470
pF
2.7 kΩ
10 µF
output A
MHB117
Fig.1 Block and application diagram.
Product specification
390 kΩ
470
pF
TEA0679T
10 µF
270 kΩ
17
POWER
SUPPLY
LOGIC
DOLBY B
EQS
(opt)
INB2
18
TEA0679T
BLANK
SKIP
Rt
(ref)
HS
PRE
AMP
AMS
PROCESSOR
I2C-BUS
DELAY
TIME
INB1
19
EQ
AMP
DOLBY B
470
pF
Philips Semiconductors
10 µF
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
2.7 kΩ
BLOCK DIAGRAM
handbook, full pagewidth
1998 Nov 12
10 µF
output B
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
PINNING
SYMBOL
PIN
DESCRIPTION
MAD
1
programmable address bit
BSC
2
blank skip reference capacitance
TD
3
delay time constant
BTC
4
blank skip integration capacitance
EQS
5
equalization switch input (optional)
OUTA
6
output channel A
INTA
7
integrating filter channel A
CONTRA
8
control voltage channel A
HPA
9
high-pass filter channel A
SCA
10
side chain channel A
BTC 4
29 DGND
EQA
11
equalizing output channel A
EQS 5
28 AMS
EQFA
12
equalizing input channel A
VCC
13
supply voltage
INA1
14
input channel A1 (forward or reverse)
Vref
15
reference voltage
INA2
16
input channel A2 (reverse or forward)
INB2
17
HS
handbook, halfpage
MAD 1
32 BEN
BSC 2
31 SDA
TD 3
30 SCL
OUTA 6
27 OUTB
INTA 7
26 INTB
CONTRA 8
25 CONTRB
TEA0679T
HPA 9
24 HPB
input channel B2 (reverse or forward)
SCA 10
23 SCB
18
head switch input (optional)
EQA 11
22 EQB
INB1
19
input channel B1 (forward or reverse)
AGND
20
EQFB
21
EQB
22
equalizing output channel B
SCB
23
side chain channel B
HPB
24
high-pass filter channel B
CONTRB
25
control voltage channel B
INTB
26
integrating filter channel B
OUTB
27
output channel B
28
Automatic Music Search (AMS)
output
DGND
29
digital ground
SCL
30
serial clock input
SDA
31
serial data input/output
BEN
32
bus enable
AMS
1998 Nov 12
EQFA 12
21 EQFB
analog ground
VCC 13
20 AGND
equalizing input channel B
INA1 14
19 INB1
Vref 15
18 HS
INA2 16
17 INB2
MHB118
Fig.2 Pin configuration.
4
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
For further information on music search see Figs 4 to 8.
FUNCTIONAL DESCRIPTION
The following functions can be controlled via the
TEA0679T
I2C-bus:
If blank skip is active (SMOD1 = 0 and SMOD0 = 1)
periods of music can be detected in the playback mode
using the AMS pin as the detector output. It is possible to
defeat this function via the I2C-bus (SMOD1 = 0 and
SMOD0 = 0). For further information on blank skip
see Figs 9 and 10.
• Equalization time constant switching
• Head switching
• Automatic Music Search (AMS) modes and blank skip
• Noise Reduction (NR) on/off switching
• Mute switching
Offset adjustment procedure
• Equalization amplifier gain adjustment
The offset adjustment is performed using two bits in the
I2C-bus write byte 0. The offset monitor bit OMOR enables
the AMS output to indicate whether the selected offset
value is positive or negative. The channel select bit OFCH
selects the channel (A or B) which is currently monitored
by the output at pin AMS. The monitoring needs a few
microseconds until the output result is valid. A complete
offset adjustment is performed in the following way:
• Output offset adjustment.
Dolby B noise reduction only operates correctly if the 0 dB
Dolby level is adjusted at 387.5 mV. The gain adjustment
can also be used to change the AMS level detector
threshold. The IC is able to generate an internal power-on
reset to guarantee a proper start-up behaviour.
Two of the above functions can be controlled via separate
pins (optional), if required.
• Adjust the output to Dolby level using the I2C-bus
controlled equalization gain adjustment
Head switching is achieved when pin HS is connected to a
LOW level (input IN2 active) or connected to a HIGH level
(input IN1 active).
• Enable the offset monitor and select the channel to be
monitored by transmitting the bits OMOR = 1 and OFCH
(0 = Channel A, 1 = Channel B) to the IC
Equalization time constant switching (70 or 120 µs) is
achieved when pin EQS is connected to a LOW level
(70 µs) or connected to a HIGH level (120 µs).
• If the monitor output (pin AMS) is LOW send the next
offset value OFFCHA or OFFCHB one offset step below
the last valid value. If the monitor output (pin AMS) is
HIGH send the next offset value OFFCHA or OFFCHB
one offset step above the last valid value
If I2C-bus control is used the respective external function
control pin has to be left open-circuit. When open-circuit
the current state of the function can be observed at these
pins.
• Repeat the last two steps until the monitor output
changes its polarity
• If necessary store the transmitted digital offset value for
the selected channel.
Automatic Music Search (AMS) modes and blank skip
If AMS is active (search mode bits SMOD1 = 1 and
SMOD0 = 0 or 1) the NR function is internally switched off
and the equalization time constant is internally forced to
70 µs. The signals of both channels are full-wave rectified
and then added. This means that even if one channel
appears inverted to the other channel the normal AMS
function is ensured.
The start value is either set by the power-on reset or the
last I2C-bus transmission. The offset adjustment can be
performed during the power-on reset condition and also
each time the tape driver is not active. A complete digital
offset data set consists of four values: one for each head
(head 1 and head 2) in each channel. After an offset value
transmission the IC stores one value for channel A and
one value for channel B. If a head switch is performed
these values have to be updated via the I2C-bus for the
alternative head.
It is possible to choose between the AMS scan and the
AMS latch mode via the I2C-bus. Due to the usage of an
internal flip-flop the switching from one mode to the other
must be done via the AMS off state. This guarantees an
appropriate flip-flop reset:
• Start from the initial AMS off state (SMOD1 = 0 and
SMOD0 = 0 or 1)
• Enable the desired AMS operation mode: AMS latch
mode (SMOD1 = 1 and SMOD0 = 0) or AMS scan mode
(SMOD1 = 1 and SMOD0 = 1).
1998 Nov 12
5
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
I2C-bus operation mode
The IC is capable of operating with I2C-bus systems that provide either 5 V or digital supply voltage related logic levels
below 5 V. This is achieved using the bus enable (pin 32) with different input voltages. An open pin or input voltages
above 5 V enable 5 V related I2C-bus logic levels. If input voltages between 3 and 5 V are used the IC operates with
I2C-bus logic levels related to these input voltages. To disable the I2C-bus receiver it is necessary to use pin voltages
below the specified LOW level.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
0
14
V
Vi
input voltage (pins 1 to 32) except pin 5 (EQS),
pin 15 (Vref), pin 18 (HS), pin 30 (SCL) and pin 31
(SDA) to VCC
−0.3
VCC
V
Vi(n1)
input voltage at pin 30 (SCL) and pin 31 (SDA)
−0.3
+12
V
Vi(n2)
input voltage at pin 5 (EQS) and pin 18 (HS)
−0.3
+6.5
V
Vi(stb)
standby input voltage at pin 1 (MAD), pin 32 (BEN),
pin 5 (EQS) and pin 18 (HS)
−0.3
+6.5
V
tsc
pin 15 (Vref) to VCC short-circuiting duration
−
5
s
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
−40
+85
°C
Ves
electrostatic handling voltage for all pins
note 2
−2
+2
kV
note 3
−500
+500
V
note 1
Notes
1. The TEA0679T allows a HIGH level at switching pins without voltage (VCC = 0; standby mode). This means a
maximum input voltage of 6.5 V for the switching pins.
2. Human body model (1.5 kΩ; 100 pF).
3. Machine model (0 Ω; 200 pF).
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1998 Nov 12
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
6
in free air
VALUE
UNIT
62
K/W
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
CHARACTERISTICS
VCC = 10 V; f = 20 Hz to 20 kHz; Tamb = 25 °C; all levels are referenced to Vo = 387.5 mV (RMS) (0 dB) at test point
(TP) pin OUTA or OUTB; see Fig.1; NR on/AMS off; EQ switch in the 70 µs position; unless otherwise specified.
SYMBOL
PARAMETER
VCC
supply voltage
CONDITIONS
MIN.
TYP.
MAX.
UNIT
7.6
10
12
V
ICC
supply current
−
35
40
mA
αm
channel matching
f = 1 kHz; Vo = 0 dB; NR off
−0.5
−
+0.5
dB
THD
total harmonic distortion
(2nd and 3rd harmonic)
f = 1 kHz; Vo = 0 dB
−
0.08
0.15
%
f = 10 kHz; Vo = 10 dB
−
0.15
0.3
%
HR
headroom at output
VCC = 7.6 V; THD = 1%;
f = 1 kHz
12
−
−
dB
S+N
-------------N
signal plus noise-to-noise ratio
internal gain 40 dB, linear;
CCIR/ARM weighted;
decode mode; see Fig.41
78
84
−
dB
PSRR
power supply ripple rejection
Vi(rms) = 0.25 V; f = 1 kHz;
see Fig.38
52
57
−
dB
Vo
output voltage frequency
response; referenced to TP
encode mode; see Fig.41
−25 dB; f = 0.2 kHz
−25.9
−24.4
−22.9
dB
0 dB; f = 1 kHz
−1.5
0
+1.5
dB
−25 dB; f = 1 kHz
−20.8
−19.3
−17.8
dB
−25 dB; f = 5 kHz
−21.1
−19.6
−18.1
dB
−35 dB; f = 10 kHz
−27.4
−25.9
−24.4
dB
αcs
channel separation
Vo = 10 dB; f = 1 kHz;
see Fig.39
57
63
−
dB
αct
crosstalk between active and
inactive input
f = 1 kHz; Vo = 10 dB; NR off;
see Fig.39
70
77
−
dB
RL
load resistance at output
AC-coupled; f = 1 kHz;
Vo = 12 dB; THD = 1%
10
−
−
kΩ
Gv
voltage gain of preamplifier
pin INA1/INA2 to pin EQFA;
pin INB1/INB2 to pin EQFB;
f = 1 kHz
29
30
31
dB
Vi(offset)(DC)
DC input offset voltage
−
2
−
mV
Ii(bias)
input bias current
−
0.1
0.4
µA
REQ
internal equalization resistor
4.7
5.8
6.9
kΩ
Ri
input resistance of head inputs
60
100
−
kΩ
Gv(ol)
open-loop gain
f = 10 kHz
80
86
−
dB
f = 400 Hz
104
110
−
dB
−20
−
+20
mV
Vref − VOUT
1998 Nov 12
DC output offset voltage at
pins OUTA and OUTB after
adjustment
pin EQA/EQB to EQ amplifier
A/B output
pin INA1 or INA2 to pin EQA;
pin INB1 or INB2 to pin EQB;
additional gain = 0 dB
NR off; pins INA1, INA2, INB1
and INB2 connected to Vref
7
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
SYMBOL
IO
PARAMETER
DC output current
TEA0679T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
pins OUTA and OUTB
connected to ground
−2
−
−
mA
pins OUTA and OUTB
connected to VCC
0.3
−
−
mA
−
80
100
Ω
−
0.7
1.4
µV
Zo
output impedance
Vno(rms)
equivalent input noise voltage
(RMS value)
VTD
AMS timing (DC level)
resistor Rt connected to pin TD VCC − 3 −
Voffset(DC)
DC offset voltage at pins OUTA
and OUTB
f = 900 MHz; Vi(rms) = 6 V
Voffset(AD)
overall offset voltage between
AGND (pin 20) and DGND
(pin 29)
NR off; unweighted;
f = 20 Hz to 20 kHz;
Rsource = 0 Ω
VCC
V
−
40
−
mV
−0.4
−
+0.4
V
24.2
25.2
26.2
dB
Level adjustment
GCR
gain control range
Gstep
step size
−
0.4
−
dB
GE
step error between any
adjacent step
−
−
0.4
dB
note 1
Switching thresholds
OPTIONAL EQUALIZATION TIME CONSTANT SWITCH (pin EQS)
VIL
LOW-level input voltage
70 µs; IL ≥ −200 µA
−0.3
−
+0.8
V
VOL
LOW-level output voltage
70 µs; IL ≤ 1 mA
−
−
0.4
V
VIH
HIGH-level input voltage
120 µs
2
−
−
V
VOH
HIGH-level output voltage
120 µs; IL ≥ −50 µA
2.8
−
3.3
V
OPTIONAL HEAD SWITCH (pin HS)
VIL
LOW-level input voltage
INPUT 2 on; IL ≥ −150 µA
−0.3
−
+0.8
V
VOL
LOW-level output voltage
INPUT 2 on; IL ≤ 10 µA
−
−
0.4
V
VIH
HIGH-level input voltage
INPUT 1 on
2
−
−
V
VOH
HIGH-level output voltage
INPUT 1 on; IL ≥ −50 µA
2.8
−
3.3
V
Search modes
BLANK SKIP
BSth(M-P)
dynamic level threshold
blank skip mode; f = 10 kHz
−30
−27
−24
dB
tsw(P-M)
switching time pause-to-music
blank skip mode; f = 10 kHz;
signal on channel A and B;
note 2
2.1
4.15
6.3
ms
blank skip mode; f = 10 kHz;
signal on one channel; note 2
4.1
8.3
12.5
ms
blank skip mode; f = 10 kHz;
note 2
10
19
30
ms
tsw(M-P)
1998 Nov 12
switching time music-to-pause
8
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
SYMBOL
PARAMETER
TEA0679T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
AUTOMATIC MUSIC SEARCH (AMS)
tW(min)(r)
minimum pulse width rise time
AMS scan mode
2
−
10
ms
AMS latch mode
130
−
170
ms
AMS(P-M)
signal level at output for AMS
switching pause-to-music
AMS mode; f = 10 kHz;
notes 3 and 4; see Fig.40
−23.7
−21
−18
dB
AMS(M-P)
AMS switching hysteresis
music-to-pause
AMS mode; f = 10 kHz
−0.7
−1
−1.3
dB
OUTPUT (pin AMS)
VOH
HIGH-level output voltage
IL ≥ −1 mA
2.8
−
3.3
V
VOL
LOW-level output voltage
IL ≤ 1 mA
−
−
0.4
V
Digital part (pins MAD and BEN)
VIH
HIGH-level input voltage
3
−
VCC
V
VIL
LOW-level input voltage
−0.3
−
+1.5
V
IIH
HIGH-level input current
−10
−
+10
µA
IIL
LOW-level input current
−10
−
+10
µA
3
−
VCC
V
5 V ≤ VBEN ≤ VCC
3
−
VCC
V
3 V ≤ VBEN < 5 V
0.7VBEN −
VCC
V
BEN (pin 32) open-circuit
−0.3
−
+1.5
V
5 V ≤ VBEN ≤ VCC
−0.3
−
+1.5
V
3 V ≤ VBEN < 5 V
−0.3
−
0.3VBEN V
VCC = 0 to 12 V
−10
−
+10
µA
−10
−
+10
µA
−
−
0.4
V
Digital part (pins SDA and SCL); note 4
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
IIH
HIGH-level input current
IIL
LOW-level input current
VOL
LOW-level output voltage SDA
BEN (pin 32) open-circuit
IL = 3 mA
Notes
1. For Dolby NR level adjust and AMS pause detection level setting.
2. All blank skip timing characteristics are based on the assumption that a signal level change from −33 to −21 dB
pause-to-music or −21 to −33 dB music-to-pause occurs in the specified channels.
3. The high speed of the tape (FF and REW) at the tape head during AMS mode causes a transformation of level and
frequency of the originally recorded signal. It means a boost of signal level of approximately 10 dB and more for
recorded frequencies from 500 Hz to 4 kHz. So the threshold level of −22 dB corresponds to signal levels in PlayBack
(PB) mode of approximately −32 dB. The AMS inputs for each channel are pins SCA and SCB. As the frequency
spectrum is transformed by a factor of approximately 10 to 30 due to the higher tape speed in FF and REW, the
high-pass filter (4.7 nF/24 kΩ) removes the effect of offset voltages but does not affect the music search function.
In the block and application diagram (see Fig.1) the frequency response of the system between tape heads input,
e.g. pins INA2 and INB2, to the AMS input pins SCA and SCB is constant over the whole frequency range (see
Fig.3).
4. These levels correspond to a gain setting of Dolby level at TP (for TP see Fig.41). The gain adjustment can be used
to change the threshold level during AMS operation.
5. The characteristics are in accordance with the I2C-bus specification. Information about the I2C-bus can be found in
the brochure “The I2C-bus and how to use it” (order number 9398 393 40011).
1998 Nov 12
9
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
General note
It is recommended to switch off VCC with a gradient of 400 V/s at maximum to avoid plops on tape in the event of contact
between tape and tape head while switching off.
AMS delay time
Table 1
AMS delay time set by resistor Rt at pin TD
RESISTOR VALUE Rt (kΩ)
DELAY TIME td TYP. (ms)
TOLERANCE (%)
68
23
20
150
42
15
180
48
15
220
56
15
270
65
10
330
76
10
470
98
10
560
112
10
680
126
10
820
142
10
1000
160
10
AMS threshold level
MHB119
−20
handbook, halfpage
(1)
AMS(P-M)
(dB)
(2)
−30
−40
−50
−60
102
103
104
f (Hz)
(1) AMS threshold level for application circuit (see Fig.1).
(2) AMS threshold level for test circuit (see Fig.40).
Fig.3 AMS threshold level.
1998 Nov 12
10
105
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
If the pause level of the input signal remains for a certain
time period, the voltage at the capacitor reaches a certain
value, which corresponds to an equivalent time value.
The voltage at the capacitor will be compared to a
predefined time-equivalent voltage by the second
comparator (F), the time detector. If the pause level of the
input signal remains for this predefined time, the time
detector changes its output level to pause found status.
Short description of music search
A system for music search consists mainly of a level and a
time detection circuit (see Fig.4). For adapting and
decoupling the input signal is amplified (A), then rectified
(B) and smoothed with a time constant (C). Thus the
voltage at (C) corresponds to the signal level and will be
compared to the predefined pause level at the first
comparator (D), the level detector. If the signal level
becomes smaller than the pause level, the level detector
changes its output signal. Due to the output level of the
level detector the capacitor of the second time constant (E)
will be charged, respectively discharged.
handbook, full pagewidth
(A)
(B)
TEA0679T
(C)
(D)
(E)
(F)
COMPARATOR 1
t1
INPUT
AMPLIFIER
RECTIFIER
VI
COMPARATOR 2
t2
LEVEL DETECTOR
Vt
OUTPUT
TIME DETECTOR
MED624
Fig.4 Integrated music search function.
1998 Nov 12
11
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
When Vt exceeds the upper threshold level after the rise
time tr (at t4) the AMS output changes to HIGH. If the signal
burst ends at t5 the level detector input VI falls to its LOW
level. Discharging of the second time constant begins
when the level threshold is exceeded at t6. The circuit then
measures the delay time td, which is externally fixed by a
resistor and defines the length of a pause to be detected.
If no signal appears at Vin within the time interval td, the
time detector output switches the AMS output to a LOW
level at t7.
Description of the principle timing diagram for AMS
scan mode without initial input signal (see Fig.5)
By activating the AMS scan mode the AMS output level
directly indicates whether the input level corresponds to a
pause level (VAMSEQ = LOW) or not (VAMSEQ = HIGH).
At t0 the AMS scan mode is activated. Without a signal at
Vin, the following initial procedure runs until the AMS
output changes to a LOW level: due to no signal at Vin the
voltage at the level detector input VI (CONTRA) remains
below the level threshold and the second time constant will
be discharged (time detector input Vt). When Vt exceeds
the time threshold level, the time detector output changes
to LOW level. Now the initial procedure is completed.
If a plop noise pulse appears at Vin (t8) with a pulse width
less than the rise time tr > tb, the plop noise will not be
detected as music. The AMS output remains LOW.
Similarly the system handles no music pulses tp: when
music appears at t11 with a small interruption at t13, this
interruption will not affect the AMS output for tp < td.
If a signal burst appears at t3, the level detector input
voltage rises immediately and causes its output to charge
the second time constant, which supplies the input voltage
Vt for the time detector.
AMS on
handbook, full pagewidth
tr
TEA0679T
tb < tr
td
tp < td
tf
Vin
t
Vl
Vl: voltage at
level detector
input
pin 8 (CONTRA)
level threshold
Vref
t
Vt
upper threshold
(hysteresis)
Vt: voltage at
time detector
input
pin 25 (CONTRB)
time threshold
t
VAMSEQ
4.5 V
output signal
to microprocessor
t
t0
t3 t4
t5 t6
t7
t8 t9 t10
t11 t12
t13 t14
tr = rise time; td = delay time; tb = burst time; tp = pause time; tf = fall time.
Fig.5 AMS scan mode without initial input signal.
1998 Nov 12
12
t15
MHB120
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
Description of the principle timing diagram for AMS scan mode with initial input signal (see Fig.6)
The AMS scan mode is activated at t0. With an input signal at Vin, the following initial procedure runs until the circuit gets
a steady state status.
Due to the signal at Vin the voltage at the level detector input VI (CONTRA) slides to a value which is defined by a limiter.
This voltage causes the level detector output to charge the second time constant (time detector input Vt) to its maximum
voltage level at t1. The initial procedure is now completed.
The following behaviour does not differ from the description in Section “Description of the principle timing diagram for
AMS scan mode without initial input signal (see Fig.5)”.
handbook, full pagewidth
AMS on
td
tf
Vin
tb < tr
tp < tr
t
Vl
Vl: voltage at
level detector
input
pin 8 (CONTRA)
level threshold
Vref
t
Vt
Vt: voltage at
time detector
input
pin 25 (CONTRB)
upper threshold
(hysteresis)
time threshold
t
VAMSEQ
4.5 V
output signal
to microprocessor
t
t0 t1
t5 t6
t7 t8 t9 t10
t11 t12
t13 t14
t15
tr = rise time; td = delay time; tb = burst time; tp = pause time; tf = fall time.
Fig.6 AMS scan mode with initial input signal.
1998 Nov 12
13
MHB121
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
By activating the AMS latch mode the AMS output will not
change to a LOW level at t0 if there is no initial signal at Vin.
A latch forces the AMS output to remain HIGH until a
signal appears at Vin (t4). After t4 the latch will not affect the
output until the AMS latch mode is started again.
The existence of the latch appears necessary if the AMS
output, for example, drives a stop solenoid via a power
FET. The LOW output level will cause a drive of the stop
solenoid. This will happen after a maximum time of td
occurs without any input signal. If there is no music on tape
for a long time (e.g. at tape end), the AMS mode will be
activated repeatedly as long as there is no signal at Vin.
Thus the circuit waits until music appears before detecting
the pauses.
Description of the principle timing diagram for AMS
latch mode without initial input signal (see Fig.7)
This is similar to the description of the principle timing
diagram from AMS scan mode. It only differs in its initial
behaviour and its rise time tr (it should be noted that the
different tr does not occur in the principle timing diagrams
for latch and scan mode).
Running in AMS latch mode, the circuit may be simply
applied to drive a stop solenoid via a power FET. So a
further processing of the AMS output signal is not
necessary. Because there is no processor to make a
decision whether there is plop noise or not, for this mode
the rise time tr is extended to approximately 150 ms.
AMS on
handbook, full pagewidth
tr
TEA0679T
tb < tr
td
tp < td
tf
Vin
t
Vl
Vl: voltage at
level detector
input
pin 8 (CONTRA)
level threshold
Vref
t
Vt
upper threshold
(hysteresis)
Vt: voltage at
time detector
input
pin 25 (CONTRB)
time threshold
t
internal
latch status
H
L
t
VAMSEQ
4.5 V
output signal
to power FET
t
t0
t3 t4
t5 t6
t7
t8 t9 t10
t11 t12
t13 t14
tr = rise time; td = delay time; tb = burst time; tp = pause time; tf = fall time.
Fig.7 AMS latch mode without initial input signal.
1998 Nov 12
14
t15
MHB122
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
Description of the principle timing diagram for AMS latch mode with initial input signal (see Fig.8)
This is similar to the description in Section “Description of the principle timing diagram for AMS scan mode with initial
input signal (see Fig.6)”. It only differs in its rise time tr and a release of its internal latch when voltage Vt exceeds the
upper threshold between t0 and t1. The initial procedure is now completed.
The following behaviour does not differ from the description in Section “Description of the principle timing diagram for
AMS latch mode without initial input signal (see Fig.7)”.
AMS on
handbook, full pagewidth
td
tf
Vin
tb < tr
tp < td
t
Vl
Vl: voltage at
level detector
input
pin 8 (CONTRA)
level threshold
Vref
t
Vt
Vt: voltage at
time detector
input
pin 25 (CONTRB)
upper threshold
(hysteresis)
time threshold
t
internal
latch status
H
L
t
VAMSEQ
4.5 V
output signal
to power FET
t
t0 t1
t5 t6
t7 t8 t9 t10
t11 t12
t13 t14
t15
tr = rise time; td = delay time; tb = burst time; tp = pause time; tf = fall time.
Fig.8 AMS latch mode with initial input signal.
1998 Nov 12
15
MHB123
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
In the event that none of the two inputs A or B exceeds the
level threshold the integration capacitor is charged. After
its voltage has exceeded the upper threshold of the output
comparator the output changes its polarity to the pause
found status.
Short description of blank skip
The blank skip system is intended to detect pauses of
music during playback mode. It consists of two input signal
level comparators, an integration capacitor and an output
comparator with hysteresis. The DC voltage of the inputs
A and B, increased by the level threshold value, is used as
the reference voltage for the input comparators. If input
A or B exceeds this voltage the integration capacitor is
discharged. If this voltage falls below the lower threshold
the output comparator changes its polarity to the music
found status.
handbook, full pagewidth
TEA0679T
It is recommended to process the output signal with a
microcontroller to perform, for example, spike suppression
for a certain time.
COMPARATOR
INPUT A
COMPARATOR
REFERENCE
VOLTAGE
t1
VC(1)
OUTPUT
COMPARATOR
MHB124
INPUT B
(1) VC: integration capacitor voltage.
Fig.9 Integrated blank skip function.
1998 Nov 12
16
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
handbook, full pagewidth
INPUT
t
VC
upper threshold
lower threshold
t
OUTPUT
VHIGH
VLOW
t
tsw(P-M)
tsw(M-P)
tsw(P-M)
tsw(M-P)
MHB125
VC; integration capacitor voltage: tsw(P-M); switching time pause-to-music: tsw(M-P); switching time music-to-pause.
Fig.10 Blank skip timing diagram.
Soft head switching
In general the head switching procedure is recommended
to be performed in four steps:
pin 18
HS (optional)
handbook, halfpage
1. Activate the mute function
10 µF
2. Switch to the alternative head
3. Adjust the offset for the new head
MHB126
4. Deactivate the mute function.
In applications without a mute function a soft head switch
via the I2C-bus can be realized using a capacitor
connected to pin 18. A proposal for this switching
mechanism is shown in Fig.11. To guarantee the internal
timing for the head switching operation an externally
connected device to pin 18 should not modify the output
current significantly.
Fig.11 Soft head switching via the I2C-bus.
8 kΩ
An additional resistor is necessary if the head switching is
performed externally via the optional switching input
capability at pin 18. A proposal for this kind of switching is
shown in Fig.12.
IN1
10 µF
IN2
MHB127
In general soft head switching is only suitable if equal
offset values for head 1 and head 2 exist. A soft offset
value switching is not possible with the TEA0679T.
1998 Nov 12
pin 18
HS (optional)
handbook, halfpage
Fig.12 External soft head switching.
17
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
I2C-BUS PROTOCOL
I2C-bus format
S
Table 2
SLAVE ADDRESS
A
DATA
A
P
Explanation of I2C-bus format to read (slave transmits data)
NAME
DESCRIPTION
S
START condition
SLAVE ADDRESS
101 100 00 (MAD = LOW)
101 100 10 (MAD = HIGH)
A
acknowledge; generated by the slave
DATA
see Tables 3 to 10
P
STOP condition
Table 3
Write byte 0; SELECT
BITS OF DATA BYTE SELECT
FUNCTIONS
MSB
LSB
SMOD1
SMOD0
HSW
MUTE
NROF
OFCH
OMOR
EQT
70 µs
−
−
−
−
−
−
−
0
120 µs
−
−
−
−
−
−
−
1
AMS output
−
−
−
−
−
−
0
−
offset monitor
−
−
−
−
−
−
1
−
channel A
−
−
−
−
−
0
−
−
channel B
−
−
−
−
−
1
−
−
on
−
−
−
−
0
−
−
−
off
−
−
−
−
1
−
−
−
off
−
−
−
0
−
−
−
−
on
−
−
−
1
−
−
−
−
IN2
−
−
0
−
−
−
−
−
IN1
−
−
1
−
−
−
−
−
0
0
−
−
−
−
−
−
Equalization time constant
Offset monitor
Offset channel
NR on/off
Mute off/on
Head switch
Search mode
off
blank skip
0
1
−
−
−
−
−
−
AMS latch mode
1
0
−
−
−
−
−
−
AMS scan mode
1
1
−
−
−
−
−
−
1998 Nov 12
18
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
Table 4
TEA0679T
Write byte 1; EQADJA
BITS OF DATA BYTE EQADJA
ADDITIONAL GAIN
POSITIONS (dB)
MSB
LSB
NOT USED NOT USED
EQA5
EQA4
EQA3
EQA2
EQA1
EQA0
0
0
0
0
0
0
0
0
0
0.4
0
0
0
0
0
0
0
1
0.8
0
0
0
0
0
0
1
0
1.2
0
0
0
0
0
0
1
1
1.6
0
0
0
0
0
1
0
0
2.0
0
0
0
0
0
1
0
1
2.4
0
0
0
0
0
1
1
0
2.8
0
0
0
0
0
1
1
1
3.2
0
0
0
0
1
0
0
0
3.6
0
0
0
0
1
0
0
1
4.0
0
0
0
0
1
0
1
0
4.4
0
0
0
0
1
0
1
1
4.8
0
0
0
0
1
1
0
0
5.2
0
0
0
0
1
1
0
1
5.6
0
0
0
0
1
1
1
0
6.0
0
0
0
0
1
1
1
1
6.4
0
0
0
1
0
0
0
0
6.8
0
0
0
1
0
0
0
1
7.2
0
0
0
1
0
0
1
0
7.6
0
0
0
1
0
0
1
1
8.0
0
0
0
1
0
1
0
0
8.4
0
0
0
1
0
1
0
1
8.8
0
0
0
1
0
1
1
0
9.2
0
0
0
1
0
1
1
1
9.6
0
0
0
1
1
0
0
0
10.0
0
0
0
1
1
0
0
1
10.4
0
0
0
1
1
0
1
0
10.8
0
0
0
1
1
0
1
1
11.2
0
0
0
1
1
1
0
0
11.6
0
0
0
1
1
1
0
1
12.0
0
0
0
1
1
1
1
0
12.4
0
0
0
1
1
1
1
1
12.8
0
0
1
0
0
0
0
0
13.2
0
0
1
0
0
0
0
1
13.6
0
0
1
0
0
0
1
0
14.0
0
0
1
0
0
0
1
1
14.4
0
0
1
0
0
1
0
0
1998 Nov 12
19
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
BITS OF DATA BYTE EQADJA
ADDITIONAL GAIN
POSITIONS (dB)
MSB
LSB
NOT USED NOT USED
EQA5
EQA4
EQA3
EQA2
EQA1
EQA0
14.8
0
0
1
0
0
1
0
1
15.2
0
0
1
0
0
1
1
0
15.6
0
0
1
0
0
1
1
1
16.0
0
0
1
0
1
0
0
0
16.4
0
0
1
0
1
0
0
1
16.8
0
0
1
0
1
0
1
0
17.2
0
0
1
0
1
0
1
1
17.6
0
0
1
0
1
1
0
0
18.0
0
0
1
0
1
1
0
1
18.4
0
0
1
0
1
1
1
0
18.8
0
0
1
0
1
1
1
1
19.2
0
0
1
1
0
0
0
0
19.6
0
0
1
1
0
0
0
1
20.0
0
0
1
1
0
0
1
0
20.4
0
0
1
1
0
0
1
1
20.8
0
0
1
1
0
1
0
0
21.2
0
0
1
1
0
1
0
1
21.6
0
0
1
1
0
1
1
0
22.0
0
0
1
1
0
1
1
1
22.4
0
0
1
1
1
0
0
0
22.8
0
0
1
1
1
0
0
1
23.2
0
0
1
1
1
0
1
0
23.6
0
0
1
1
1
0
1
1
24.0
0
0
1
1
1
1
0
0
24.4
0
0
1
1
1
1
0
1
24.8
0
0
1
1
1
1
1
0
25.2
0
0
1
1
1
1
1
1
1998 Nov 12
20
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
Table 5
TEA0679T
Write byte 2; EQADJB
BITS OF DATA BYTE EQADJB
ADDITIONAL GAIN
POSITIONS (dB)
MSB
LSB
NOT USED NOT USED
EQB5
EQB4
EQB3
EQB2
EQB1
EQB0
0
0
0
0
0
0
0
0
0
0.4
0
0
0
0
0
0
0
1
0.8
0
0
0
0
0
0
1
0
1.2
0
0
0
0
0
0
1
1
1.6
0
0
0
0
0
1
0
0
2.0
0
0
0
0
0
1
0
1
2.4
0
0
0
0
0
1
1
0
2.8
0
0
0
0
0
1
1
1
3.2
0
0
0
0
1
0
0
0
3.6
0
0
0
0
1
0
0
1
4.0
0
0
0
0
1
0
1
0
4.4
0
0
0
0
1
0
1
1
4.8
0
0
0
0
1
1
0
0
5.2
0
0
0
0
1
1
0
1
5.6
0
0
0
0
1
1
1
0
6.0
0
0
0
0
1
1
1
1
6.4
0
0
0
1
0
0
0
0
6.8
0
0
0
1
0
0
0
1
7.2
0
0
0
1
0
0
1
0
7.6
0
0
0
1
0
0
1
1
8.0
0
0
0
1
0
1
0
0
8.4
0
0
0
1
0
1
0
1
8.8
0
0
0
1
0
1
1
0
9.2
0
0
0
1
0
1
1
1
9.6
0
0
0
1
1
0
0
0
10.0
0
0
0
1
1
0
0
1
10.4
0
0
0
1
1
0
1
0
10.8
0
0
0
1
1
0
1
1
11.2
0
0
0
1
1
1
0
0
11.6
0
0
0
1
1
1
0
1
12.0
0
0
0
1
1
1
1
0
12.4
0
0
0
1
1
1
1
1
12.8
0
0
1
0
0
0
0
0
13.2
0
0
1
0
0
0
0
1
13.6
0
0
1
0
0
0
1
0
14.0
0
0
1
0
0
0
1
1
14.4
0
0
1
0
0
1
0
0
1998 Nov 12
21
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
BITS OF DATA BYTE EQADJB
ADDITIONAL GAIN
POSITIONS (dB)
MSB
LSB
NOT USED NOT USED
EQB5
EQB4
EQB3
EQB2
EQB1
EQB0
14.8
0
0
1
0
0
1
0
1
15.2
0
0
1
0
0
1
1
0
15.6
0
0
1
0
0
1
1
1
16.0
0
0
1
0
1
0
0
0
16.4
0
0
1
0
1
0
0
1
16.8
0
0
1
0
1
0
1
0
17.2
0
0
1
0
1
0
1
1
17.6
0
0
1
0
1
1
0
0
18.0
0
0
1
0
1
1
0
1
18.4
0
0
1
0
1
1
1
0
18.8
0
0
1
0
1
1
1
1
19.2
0
0
1
1
0
0
0
0
19.6
0
0
1
1
0
0
0
1
20.0
0
0
1
1
0
0
1
0
20.4
0
0
1
1
0
0
1
1
20.8
0
0
1
1
0
1
0
0
21.2
0
0
1
1
0
1
0
1
21.6
0
0
1
1
0
1
1
0
22.0
0
0
1
1
0
1
1
1
22.4
0
0
1
1
1
0
0
0
22.8
0
0
1
1
1
0
0
1
23.2
0
0
1
1
1
0
1
0
23.6
0
0
1
1
1
0
1
1
24.0
0
0
1
1
1
1
0
0
24.4
0
0
1
1
1
1
0
1
24.8
0
0
1
1
1
1
1
0
25.2
0
0
1
1
1
1
1
1
Table 6
Write byte 3; OFFCHA
BITS OF DATA BYTE OFFCHA
OFFSET CHANNEL A
POSITIONS
Maximum positive
Maximum negative
1998 Nov 12
MSB
LSB
OFA7
OFA6
OFA5
OFA4
OFA3
OFA2
OFA1
OFA0
0
0
0
0
0
0
0
0
...
...
...
...
...
...
...
...
1
1
1
1
1
1
1
1
22
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
Table 7
TEA0679T
Write byte 4; OFFCHB
BITS OF DATA BYTE OFFCHB
OFFSET CHANNEL B
POSITIONS
MSB
OFB7
OFB6
OFB5
OFB4
OFB3
OFB2
OFB1
OFB0
0
0
0
0
0
0
0
0
...
...
...
...
...
...
...
...
1
1
1
1
1
1
1
1
Maximum positive
Maximum negative
Table 8
LSB
Optionally pin controlled switch functions
HS (PIN 18)
FUNCTIONS
EQS (PIN 5)
PIN STATE
OUTPUT
INPUT
DATA BIT
HSW
70 µs
−
−
120 µs
−
−
70 µs
−
IN2
PIN STATE
OUTPUT
INPUT
DATA BIT
EQT
−
LOW
open-circuit
0
−
HIGH
open-circuit
1
−
−
LOW
LOW
−
LOW
open-circuit
0
−
−
−
IN1
HIGH
open-circuit
1
−
−
−
IN2
LOW
LOW
−
−
−
−
Equalization time constant
Head switch
Table 9
MAD switch
MODULE ADDRESS
MAD (PIN 1)
101 100 10
open-circuit
101 100 10
HIGH
101 100 00
LOW
I2C-BUS OPERATION MODE
BEN (PIN 32)
Active; 5 V thresholds
open-circuit
Active; 5 V thresholds
HIGH (5 V to VCC)
Active; VBEN related thresholds
HIGH (3 to 5 V)
Inactive
LOW
Table 10 BEN switch
1998 Nov 12
23
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
If the OMOR bit is set to logic 1 and the OFCH bit is set to
logic 0 the transmission type for an offset adjust in
channel A is selected. The byte sequence is shown in
Fig.14. During this kind of transmission the pin AMS is
used as the offset monitor output for channel A.
I2C-bus transmission types
The I2C-bus format depends on the kind of data which
should be transmitted. To speed up the offset adjustment
procedure three types of transmissions from master to
slave are possible. The transmission type is controlled by
bits OFCH and OMOR in write byte 0.
If the OMOR bit is set to logic 1 and the OFCH bit is set to
logic 1 the transmission type for an offset adjust in
channel B is selected. The byte sequence is shown in
Fig.15. During this kind of transmission the pin AMS is
used as the offset monitor output for channel B.
If the OMOR bit is set to logic 0 the standard transmission
type is used. The corresponding byte sequence is shown
in Fig.13. This kind of transmission should by used for
changes in the IC settings during normal operation.
handbook, full pagewidth S
CHIP ADDRESS
R/W
A
ADDRESS
TEA0679T
X
0
A
BYTE 0
BYTE 1
A
BYTE 2
A
A
A
BYTE 3
P
BYTE 4
MHB128
Fig.13 Standard transmission.
handbook, full pagewidth S
CHIP ADDRESS
R/W
A
ADDRESS
0
1
A
BYTE 0
A
BYTE 3
A
A
A
BYTE 3
P
BYTE 3
MHB129
Fig.14 Offset adjust channel A transmission.
handbook, full pagewidth S
CHIP ADDRESS
R/W
A
ADDRESS
1
1
A
BYTE 0
A
A
BYTE 4
A
A
BYTE 4
P
BYTE 4
MHB130
Fig.15 Offset adjust channel B transmission.
1998 Nov 12
24
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
INTERNAL PIN CONFIGURATIONS
2
handbook, halfpage
+
+
handbook, halfpage
1
80 kΩ
80 kΩ
160 Ω
160 Ω
1.6 V
MHB131
MHB132
Fig.16 Pin 1: programmable address bit.
handbook, halfpage
+
Fig.17 Pin 2: blank skip reference capacitance.
3
handbook, halfpage
8V
+
4
1 kΩ
MHB134
MHB133
Fig.18 Pin 3: delay time constant.
1998 Nov 12
Fig.19 Pin 4: blank skip integration capacitance.
25
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
handbook, halfpage
handbook, halfpage
5
+
TEA0679T
6
+
5V
85 Ω
85 Ω
3V
47 Ω
MHB136
MHB135
Fig.20 Pin 5: EQ switch input.
Fig.21 Pins 6 and 27: output channel.
handbook, halfpage
+
8
5V
handbook, halfpage
7
+
Vref ± 0.23 V
1.2 kΩ
3.4 kΩ
3.6 kΩ
3.6 kΩ
40 kΩ
MHB137
5V
MHB138
Fig.22 Pin 7: integrating filter channel A.
1998 Nov 12
Fig.23 Pin 8: control voltage channel A.
26
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
handbook, halfpage
handbook, halfpage
10
9
+
5V
+
5V
+
670 Ω
9 kΩ
9 kΩ
5V
MHB139
MHB140
Fig.24 Pins 9 and 24: high-pass filter.
handbook, halfpage
Fig.25 Pins 10 and 23: side chain.
11
+
handbook, halfpage
5V
+
12
5V
20 kΩ
10 kΩ
20 kΩ
160 Ω
5.8 kΩ
2.7 pF
MHB142
MHB141
Fig.26 Pins 11 and 22: equalizing output.
1998 Nov 12
Fig.27 Pins 12 and 21: equalizing input.
27
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
handbook, halfpage
14
+
5V
handbook, halfpage
13
10 V
240 Ω
100 kΩ
MHB143
6.25
pF
5V
MHB144
Fig.28 Pin 13: supply voltage.
Fig.29 Pins 14, 16, 17 and 19: input channel.
handbook, halfpage
+
18
+
handbook, halfpage
2.55 kΩ
15
5V
2.55 kΩ
MHB145
MHB146
Fig.30 Pin 15: reference voltage.
1998 Nov 12
Fig.31 Pin 18: head switch input.
28
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
handbook, halfpage
+
TEA0679T
handbook, halfpage
25
5V
26
Vref ± 0.23 V
+
3.6 kΩ
1.2 kΩ
3.4 kΩ
3.6 kΩ
+
MHB147
MHB148
Fig.32 Pin 25: control voltage channel B.
Fig.33 Pin 26: integrating filter channel B.
handbook, halfpage +
handbook, halfpage
+
30
28
1.9 kΩ
3V
MHB149
MHB150
Fig.34 Pin 28: AMS output.
1998 Nov 12
Fig.35 Pin 30: serial clock input.
29
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
handbook, halfpage +
TEA0679T
31
handbook, halfpage
32
+
1.9 kΩ
MHB152
MHB151
Fig.36 Pin 31: serial data input/output.
1998 Nov 12
Fig.37 Pin 32: bus enable.
30
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15 nF
4.7 nF
10 kΩ
270 kΩ
180 kΩ
24 kΩ
20 kΩ
HS
(opt)
BEN
SDA
SCL
DGND AMS
OUTB
INTB
CONTRB
HPB
SCB
EQB
EQFB
AGND
32
31
30
29
27
26
25
24
23
22
21
20
28
MUTE
LATCH
AND
RISE TIME
AMS
PROCESSOR
31
BLANK
SKIP
INB2
18
17
POWER
SUPPLY
LOGIC
LEVEL
DETECTOR
PRE
AMP
EQ
AMP
DOLBY B
1
2
3
4
5
6
7
8
9
10
11
12
13
MAD
BSC
TD
BTC
EQS
OUTA
INTA
CONTRA
HPA
SCA
EQA
EQFA
VCC = 10 V
14
INA1
15
16
Vref
INA2
20 kΩ
Rt
(ref)
220 nF
HS
TEA0679T
I2C-BUS
DELAY
TIME
19
PRE
AMP
EQ
AMP
DOLBY B
INB1
Philips Semiconductors
100 nF
10 µF
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
330 nF
TEST AND APPLICATION INFORMATION
handbook, full pagewidth
1998 Nov 12
10 µF
output B
EQS
(opt)
47 nF
330 nF
100 nF
10 kΩ
24 kΩ
180 kΩ
15 nF
4.7 nF
10 kΩ
100
nF
100
µF
1000
µF
0.25 V (RMS)
1 kHz
MHB153
Fig.38 Test circuit for power supply ripple rejection.
Product specification
10 µF
output A
TEA0679T
10 µF
270 kΩ
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100 nF
15 nF
10 µF
4.7 nF
10 kΩ
270 kΩ
180 kΩ
24 kΩ
20 kΩ
HS
(opt)
BEN
SDA
SCL
DGND AMS
OUTB
INTB
CONTRB
HPB
SCB
EQB
EQFB
AGND
32
31
30
29
27
26
25
24
23
22
21
20
28
MUTE
LATCH
AND
RISE TIME
INB2
18
17
TEA0679T
BLANK
SKIP
POWER
SUPPLY
LOGIC
32
LEVEL
DETECTOR
PRE
AMP
EQ
AMP
DOLBY B
1
2
3
4
5
6
7
8
9
10
11
12
13
MAD
BSC
TD
BTC
EQS
OUTA
INTA
CONTRA
HPA
SCA
EQA
EQFA
VCC
14
INA1
15
16
Vref
INA2
20 kΩ
Rt
(ref)
220 nF
HS
PRE
AMP
AMS
PROCESSOR
I2C-BUS
DELAY
TIME
19
EQ
AMP
DOLBY B
INB1
Philips Semiconductors
330 nF
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
andbook, full pagewidth
1998 Nov 12
10 µF
output B
EQS
(opt)
47 nF
330 nF
100 nF
10 V
24 kΩ
180 kΩ
15 nF
4.7 nF
200 Ω
10 kΩ
100
nF
100
µF
10 µF
10 µF
MHB154
Fig.39 Test circuit for channel separation.
TEA0679T
output A
Product specification
10 µF
270 kΩ
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330 nF
100 nF
15 nF
4.7 nF
10 kΩ
270 kΩ
180 kΩ
24 kΩ
20 kΩ
HS
(opt)
BEN
SDA
SCL
DGND AMS
OUTB
INTB
CONTRB
HPB
SCB
EQB
EQFB
AGND
32
31
30
29
27
26
25
24
23
22
21
20
28
MUTE
LATCH
AND
RISE TIME
AMS
PROCESSOR
INB2
18
17
BLANK
SKIP
POWER
SUPPLY
LOGIC
33
voltage
input
LEVEL
DETECTOR
PRE
AMP
EQ
AMP
DOLBY B
1
2
3
4
5
6
7
8
9
10
11
12
13
MAD
BSC
TD
BTC
EQS
OUTA
INTA
CONTRA
HPA
SCA
EQA
EQFA
VCC
14
INA1
15
16
Vref
INA2
20 kΩ
Rt
(ref)
220 nF
HS
TEA0679T
I2C-BUS
DELAY
TIME
19
PRE
AMP
EQ
AMP
DOLBY B
INB1
Philips Semiconductors
10 µF
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
andbook, full pagewidth
1998 Nov 12
10 µF
output B
EQS
(opt)
47 nF
10 µF
270 kΩ
330 nF
100 nF
100
µF
24 kΩ
180 kΩ
15 nF
4.7 nF
10 kΩ
100
nF
10 V
10 µF
Fig.40 Test circuit for AMS threshold level.
TEA0679T
MHB155
Product specification
output A
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VCC
25 kΩ
10 µF
330 nF
100 nF
15 nF
4.7 nF
270 kΩ
180 kΩ
10 µF
10 kΩ
24 kΩ
25 kΩ
20 kΩ
HS
(opt)
BEN
SDA
SCL
DGND AMS
OUTB
INTB
CONTRB
HPB
SCB
EQB
EQFB
AGND
32
31
30
29
27
26
25
24
23
22
21
20
28
LATCH
AND
RISE TIME
INB2
18
17
TEA0679T
BLANK
SKIP
POWER
SUPPLY
LOGIC
34
LEVEL
DETECTOR
PRE
AMP
EQ
AMP
DOLBY B
1
2
3
4
5
6
7
8
9
10
11
12
13
MAD
BSC
TD
BTC
EQS
OUTA
INTA
CONTRA
HPA
SCA
EQA
EQFA
VCC
14
INA1
15
16
Vref
INA2
20 kΩ
Rt
(ref)
220 nF
HS
PRE
AMP
AMS
PROCESSOR
I2C-BUS
DELAY
TIME
INB1
19
EQ
AMP
DOLBY B
MUTE
Vi
Philips Semiconductors
TP
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
dbook, full pagewidth
1998 Nov 12
10 µF
output B
EQS
(opt)
47 nF
270 kΩ
330 nF
100 nF
10 V
24 kΩ
180 kΩ
15 nF
4.7 nF
10 kΩ
100
nF
10 µF
10 µF
100
µF
10
µF
470
pF
200
Ω
Vi
Channel A: Decode mode: pre-amplifier 30 dB and EQ amplifier 10 dB linear.
Channel B: Encode mode.
Fig.41 Test circuit for frequency response (channel B).
TEA0679T
MHB156
TP
Product specification
output A
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100 nF
15 nF
4.7 nF
470
pF
10 kΩ
270 kΩ
180 kΩ
24 kΩ
20 kΩ
SDA
SCL
DGND AMS
OUTB
INTB
CONTRB
HPB
SCB
EQB
EQFB
AGND
32
31
30
29
27
26
25
24
23
22
21
20
MUTE
LATCH
AND
RISE TIME
470
pF
HS
INB2
18
17
PRE
AMP
AMS
PROCESSOR
TEA0679T
I2C-BUS
BLANK
SKIP
DELAY
TIME
INB1
19
EQ
AMP
DOLBY B
200
Ω
HS
(opt)
BEN
28
200
Ω
POWER
SUPPLY
LOGIC
LEVEL
DETECTOR
35
PRE
AMP
EQ
AMP
DOLBY B
1
2
3
4
5
6
7
8
9
10
11
12
13
MAD
BSC
TD
BTC
EQS
OUTA
INTA
CONTRA
HPA
SCA
EQA
EQFA
VCC
20 kΩ
Rt
(ref)
220 nF
14
INA1
EQS
(opt)
47 nF
330 nF
100 nF
24 kΩ
15 nF
4.7 nF
10 kΩ
16
Vref
INA2
100
µF
270 kΩ
180 kΩ
15
Philips Semiconductors
330 nF
10 µF
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
andbook, full pagewidth
1998 Nov 12
10 µF
output B
100
nF
10 V
470
pF
200
Ω
200
Ω
470
pF
10 µF
10 µF
output A
Fig.42 EMC test circuit.
Product specification
40 Ω
TEA0679T
MHB157
10 Ω
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
PACKAGE OUTLINE
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
HE
v M A
Z
17
32
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
16
1
0
detail X
w M
bp
e
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.27
0.18
20.7
20.3
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.2
1.0
0.25
0.25
0.1
0.95
0.55
inches
0.10
0.012 0.096
0.004 0.086
0.01
0.02
0.01
0.011
0.007
0.81
0.80
0.30
0.29
0.050
0.419
0.394
0.055
0.043
0.016
0.047
0.039
0.01
0.01
0.004
0.037
0.022
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-01-25
97-05-22
SOT287-1
1998 Nov 12
EUROPEAN
PROJECTION
36
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
SOLDERING
Wave soldering
Introduction
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1998 Nov 12
37
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
TEA0679T
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Nov 12
38
Philips Semiconductors
Product specification
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
NOTES
1998 Nov 12
39
TEA0679T
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
Fax. +43 160 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/750/02/pp40
Date of release: 1998 Nov 12
Document order number:
9397 750 04298