INTEGRATED CIRCUITS DATA SHEET TEA0675 Dual Dolby* B-type noise reduction circuit for playback applications Preliminary specification Supersedes data of July 1993 File under Integrated Circuits, IC01 1996 Jun 07 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 This device also detects pauses of music in the Automatic Music Search (AMS) scan mode, for applications with an intelligent controlled tape driver, or AMS-latch mode, for applications with a simple controlled tape driver. For both modes, the delay time can be fixed externally by a resistor. The device operates with power supplies in the range of 7.6 to 12 V, output overload level increasing with increase in supply voltage. Current drain varies with the following variables: FEATURES • Dual noise reduction (NR) channels • Head pre-amplifiers • Reverse head switching • Automatic Music Search (AMS) • Music scan • Equalization with electronically switched time constants • Dolby reference level = 387.5 mV supply voltage • 24 pins noise reduction on/off • Improved EMC behaviour. AMS on/off. Because of this current drain variation it is advisable to use a regulated power supply or a supply with a long time constant. GENERAL DESCRIPTION The TEA0675 is a bipolar integrated circuit that provides two channels of Dolby B noise reduction for playback applications in car radios. It includes head and equalization amplifiers with electronically switchable time constants. Furthermore it includes electronically switchable inputs for tape drivers with reverse heads. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC supply voltage 7.6 − 12 V ICC supply current − 26 31 mA S+N -------------N signal plus noise-to-noise ratio 78 84 − dB ORDERING INFORMATION TYPE NUMBER TEA0675 TEA0675T PACKAGE NAME SDIP24 SO24 DESCRIPTION VERSION plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 Remark Dolby*: Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby Laboratories Licensing Corporation. 1996 Jun 07 2 1996 Jun 07 3 270 kΩ DOLBY B 180 kΩ 15 nF DOLBY B 100 nF 3 21 4 ON 1.5 kΩ 20 4.7 nF 4.7 nF 24 kΩ 24 kΩ Rt 6 19 120 µs 18 kΩ 70 µs EQ AMP. 330 kΩ 7 10 nF 8.2 kΩ EQ AMP. LOGIC 18 8.2 kΩ 10 nF 9 16 180 Ω VCC 1 kΩ 8 17 1 kΩ Fig.1 Block and application diagram. (1) OFF AMS 1.5 kΩ 5 AMS PROCESSOR ON DELAY TIME LATCH AND RISE TIME 22 LEVEL DETECTOR 330 nF 2 23 180 kΩ 15 nF OFF 330 kΩ 180 Ω 470 pF PRE AMP. 10 µF PRE AMP. POWER SUPPLY 10 µF 470 pF 15 10 11 100 µF 10 µF TEA0675 14 27 kΩ 2 1 headswitch input 470 pF 12 13 470 pF MED621 Dual Dolby* B-type noise reduction circuit for playback applications (1) Switched to VCC for AMS-scan mode. output A 10 µF 1 24 270 kΩ 100 nF EQ handbook, full pagewidth output B 10 µF 330 nF NR AMS output Philips Semiconductors Preliminary specification TEA0675 BLOCK DIAGRAM Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 PINNING SYMBOL PIN DESCRIPTION OUTA 1 output channel A INTA 2 integrating filter channel A CONTRA 3 control voltage channel A HPA 4 high-pass filter channel A SCA 5 side chain channel A TD 6 delay time constant EQA 7 equalizing output channel A EQFA 8 equalizing input channel A VCC 9 INA1 10 OUTA 1 24 OUTB INTA 2 23 INTB CONTRA 3 22 CONTRB supply voltage HPA 4 21 HPB input channel A1 (forward or reverse) SCA 5 20 SCB TD 6 Vref 11 reference voltage INA2 12 input channel A2 (reverse or forward) INB2 13 input channel B2 (reverse or forward) HS 14 head switch input INB1 15 input channel B1 (forward or reverse) GND 16 ground EQFB 17 equalizing input channel B EQB 18 equalizing output channel B AMSEQ 19 AMS output and EQ switch input SCB 20 side chain channel B HPB 21 high-pass filter channel B CONTRB 22 control voltage channel B INTB 23 integrating filter channel B OUTB 24 output channel B 1996 Jun 07 handbook, halfpage 19 AMSEQ TEA0675 EQA 7 18 EQB EQFA 8 17 EQFB VCC 9 16 GND INA1 10 15 INB1 Vref 11 14 HS INA2 12 13 INB2 MED622 Fig.2 Pin configuration. 4 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 Equalization time constant switching (70 µs or 120 µs) is achieved when pin AMSEQ is connected to GND via an 18 kΩ resistor (120 µs), or left open-circuit (70 µs). This does not affect the AMS output signal during AMS mode (see Fig.1). FUNCTIONAL DESCRIPTION Noise Reduction (NR) is enabled when pin HPB is open-circuit and disabled when connected to GND via an 1.5 kΩ resistor. Dolby B noise reduction only operates correctly if 0 dB Dolby level is adjusted at 387.5 mV. Head switching is achieved when pin HS is connected (input IN2 active) to GND via a 27 kΩ resistor, or left open-circuit (input IN1 active). The 10 µF capacitor at pin HS sets the time constants for smooth switching. Automatic Music Search (AMS) scan mode is enabled when pin HPA is connected to VCC via an 1.5 kΩ resistor and disabled when pin HPA is open-circuit. Switching AMS on, internally NR is switched OFF simultaneously (see Figs 5 and 6 for principle timing in AMS-scan mode). In AMS mode the signals of both channels are rectified and then added. This means, even if one channel signal appears inverted to the other channel, the normal AMS function is ensured. Pins HPB and HPA perform the function of a logic input for AMS, respectively NR mode switching in both channels and provide the frequency dependent feedback of the control chain amplifier in the corresponding channel. Thus it is important that no voltage is applied to pins HPB and HPA during NR on/AMS off mode, otherwise this will cause irregular NR characteristics. AMS-latch mode is enabled when pin HPA is connected to GND via an 1.5 kΩ resistor and disabled when pin HPA is open-circuit. Switching AMS on, NR is switched off internally. In this mode the device detects a pause level signal, when a music level signal has appeared first (see Figs 7 and 8 for principle timing). Furthermore a longer rise time constant is supplied for suppressing the detection of plops on tape. The output signal at pin AMSEQ in this mode may be applied to drive a tape driver logic circuit. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 0 Vi input voltage (except pin 11) −0.3 +VCC V tshort pin 11 (Vref) to VCC short-circuiting duration − 5 s Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −40 +85 °C Ves electrostatic handling voltage for all pins note 1 −2 +2 kV note 2 −500 +500 V Notes 1. Human body model (1.5 kΩ, 100 pF). 2. Machine model (0 Ω, 200 pF). 1996 Jun 07 5 14 V Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 CHARACTERISTICS VCC = 10 V; f = 20 Hz to 20 kHz; Tamb = 25 °C; all levels are referenced to 387.5 mV (RMS) (0 dB) at test point (TP) pin OUTA or OUTB; see Fig.1; NR on/AMS off; EQ switch in the 70 µs position; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage 7.6 10 12 V ICC supply current − 26 31 mA αm channel matching f = 1 kHz; Vo = 0 dB; NR off −0.5 − +0.5 dB THD total harmonic distortion (2nd and 3rd harmonic) f = 1 kHz; Vo = 0 dB − 0.08 0.15 % f = 10 kHz; Vo = 10 dB − 0.15 0.3 % HR headroom at output VCC = 7.6 V; THD = 1%; f = 1 kHz 12 − − dB S+N -------------N signal plus noise-to-noise ratio internal gain 40 dB, linear; CCIR/ARM weighted; decode mode; see Fig.25 78 84 − dB PSRR power supply ripple rejection Vi(rms) = 0.25 V; f = 1 kHz; see Fig.22 52 57 − dB fo frequency response; referenced to TP encode mode; see Fig.25 Vo = −25 dB; f = 0.2 kHz −22.9 −24.4 −25.9 dB Vo = 0 dB; f = 1 kHz −1.5 0 +1.5 dB Vo = −25 dB; f = 1 kHz −17.8 −19.3 −20.8 dB Vo = −25 dB; f = 5 kHz −18.1 −19.6 −21.1 dB Vo = −35 dB; f = 10 kHz −24.4 −25.9 −27.4 dB αcs channel separation Vo = 10 dB; f = 1 kHz; see Fig.23 57 63 − dB αcc crosstalk between active and inactive input f = 1 kHz; Vo = 10 dB; NR off; see Fig.23 70 77 − dB RL load resistance at output AC-coupled; f = 1 kHz; Vo = 12 dB; THD = 1% 10 − − kΩ Gv voltage gain of pre-amplifier from pin INA1 or INA2 to pin EQFA and from pin INB1 or INB2 to pin EQFB; f = 1 kHz 29 30 31 dB VI(offset)(DC) DC input offset voltage − 2 − mV Ii(bias) input bias current − 0.1 0.4 µA REQ equalization resistor 4.7 5.8 6.9 kΩ Ri input resistance head inputs 60 100 − kΩ Av open-loop amplification 1996 Jun 07 pin INA1 or INA2 to pin EQA and pin INB1 or INB2 to pin EQB f = 10 kHz 80 86 − dB f = 400 Hz 104 110 − dB 6 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications SYMBOL PARAMETER Vref − VOUT DC output offset voltage at pins OUTA and OUTB IO DC output current TEA0675 CONDITIONS MIN. NR off; pins INA1, INA2, INB1 and INB2 connected to Vref −0.15 pin OUTA to ground −2 pin OUTB to VCC 0.3 − TYP. − MAX. UNIT +0.15 V − − mA − − mA 80 100 Ω Zo output impedance Vno(rms) equivalent input noise voltage (RMS value) NR off; unweighted; f = 20 Hz to 20 kHz; Rsource = 0 Ω − 0.7 1.4 µV VTD AMS timing (DC level) resistor Rt connected to pin TD VCC − 3 − VCC V EMC DC offset voltage at pins OUTA and OUTB f = 900 MHz; Vi(rms)= 6 V; see Figs 26, 27 and 28 − 40 − mV Switching thresholds VNROFF voltage at HPB (pin 21) NR off 0.19VCC 0.23VCC 0.25VCC V INROFF output current NR off − −0.7 −1 mA INRON input current NR on − open 200 nA VHPB(max) maximum voltage − − 0.75VCC V 0.19VCC 0.23VCC 0.25VCC V − −0.7 −1 mA HPA (PIN 4) VAMSlON pin voltage IAMSlON output current VAMSsON pin voltage IAMSsON input current IAMSOFF pin current VHPA(max) maximum voltage AMS-latch on AMS-scan on AMS off 0.75VCC 0.77VCC 0.81VCC V − 0.8 1 mA − open 200 nA − − 0.75VCC V AMSEQ (PIN 19) AMS output (AMS mode) VOH HIGH level output voltage 4 4.6 5 V IOH1 HIGH level output current note 1 +10 − −150 µA IOH2 HIGH level output current note 1 +0.01 − −1 mA td minimum pulse width; delay time range see Table 1 − 23 to 160 − ms VOL LOW level output voltage − 0.1 0.7 V IOL LOW level output current −0.02 − +1 mA tr minimum pulse width rise time AMS-scan mode 2 6 10 ms AMS-latch mode 130 150 170 ms signal level at output for AMS switching music to pause AMS mode; f = 10 kHz; note 2; see Fig.24 −25 −22 −19 dB AM/P 1996 Jun 07 7 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications SYMBOL AP/M PARAMETER signal level at output for AMS switching pause to music TEA0675 CONDITIONS MIN. TYP. MAX. UNIT AMS mode; f = 10 kHz; −24 −21 −18 dB −150 − − µA − −250 µA − −200 − µA EQ switch input (not AMS mode) IEQ70 input current time constant 70 µs active IEQ120 input voltage time constant 120 µs active −1000 IEQth threshold current note 1 HEAD SWITCHING VHSW pin voltage load current +90 to −90 µA − 0.8VCC − V IHSW input current VHSW = 0 to VCC −170 − +170 µA − VCC V − 1⁄ VHSW(HIGH) HIGH level pin voltage inputs INA1 and INB1 active; note 3 1⁄ VHSW(LOW) LOW level pin voltage inputs INA2 and INB2 active 0 2VCC + 0.5 2VCC − 0.5 V Notes 1. In AMS off mode, pin AMSEQ is HIGH level, the equalization time constant will be switched by pulling approximately 200 µA out of pin AMSEQ. This means for the device connected to pin AMSEQ, a restriction of input current at HIGH level less than 200 µA during AMS off; otherwise the selection of the equalization time constant is disabled and fixed at 120 µs. If the connected devices consume more than 200 µA, this input has to be disconnected in AMS off mode. (To ensure switching, the currents for the different switched modes are specified with a tolerance of ±50 µA in Chapter “Characteristics”.) For an application with a fixed EQ time constant of 120 µs the equalizing network may be applied completely external. Change 8.2 kΩ resistor to 14 kΩ the internal resistor REQ = 5.8 kΩ is short-circuited by fixing the EQ switch input at the 70 µs position (IEQ70). 2. The high speed of the tape (FF, REW) at the tape head during AMS mode causes a transformation of level and frequency of the originally recorded signal. It means a boost of signal level of approximately 10 dB and more for recorded frequencies from 500 Hz up to 4 kHz. So the threshold level of −22 dB corresponds to signal levels in Play Back (PB) mode of approximately −32 dB. The AMS inputs for each channel are pin SCA and pin SCB. As the frequency spectrum is transformed by a factor of approximately 10 to 30 due to the higher tape speed in FF, REW, the high-pass filter (4.7 nF/24 kΩ) removes the effect of offset voltages but does not affect the music search function. In the application circuit (Fig.1) the frequency response of the system between tape heads input, e.g. pins INA2 and INB2, to the AMS input pins SCA and SCB is constant over the whole frequency range (see Fig.3). 3. To activate the inputs IN1, pin HS might be left open-circuit. In this event the DC level at pin HS is 0.775VCC. 1996 Jun 07 8 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications Table 1 TEA0675 Blank delay time set by resistor Rt at pin TD RESISTOR VALUE Rt (kΩ) DELAY TIME td TYP. (ms) TOLERANCE (%) 68 23 20 150 42 15 180 48 15 220 56 15 270 65 10 330 76 10 470 98 10 560 112 10 680 126 10 820 142 10 1000 160 10 General note It is recommended to switch off VCC with a gradient of 400 V/s at maximum to avoid plops on tape in the event of contact between tape and tape head while switching off. MED623 −20 handbook, full pagewidth (1) (dB) −30 −40 (2) −50 −60 102 103 104 (1) AMS threshold level for application circuit (Fig.1). (2) AMS threshold level for test circuit (Fig.24). Fig.3 AMS threshold level. 1996 Jun 07 9 (Hz) 105 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications respectively discharged. If the pause level of the input signal remains for a certain time, the voltage at the capacitor reaches a certain value, which corresponds to an equivalent time value. The voltage at the capacitor will be compared to a predefined time-equivalent voltage by the second comparator (F), the time detector. If the pause level of the input signal remains for this predefined time, the time detector changes its output level for ‘pause found’ status. Short description ‘music search’ A system for ‘music search’ mainly consists of a level and a time detection (see Fig.4). For adapting and decoupling the input signal will be amplified (A), then rectified (B) and smoothed with a time constant (C). So the voltage at (C) corresponds to the signal level and will be compared to the predefined pause level at the first comparator (D), the level detector. If the signal level becomes smaller than the pause level, the level detector changes its output signal. Due to the output level of the level detector the capacitor of the second time constant (E) will be charged, handbook, full pagewidth (A) (B) TEA0675 (C) (D) (E) (F) COMPARATOR 1 t1 INPUT AMPLIFIER RECTIFIER VI COMPARATOR 2 t2 LEVEL DETECTOR Vt OUTPUT TIME DETECTOR MED624 Fig.4 Integrated ‘music search’ function. 1996 Jun 07 10 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 Description of the principle timing diagram for AMS-scan mode without initial input signal (see Fig.5) tr: rise handbook, fulltime pagewidth td: delay time tb: burst time tp: pause time tf: fall time AMS on tr tb<tr td tp<td tf Vin t Vl Vl: voltage at level detector input pin 3 (CONTRA) level threshold VREF t Vt upper threshold (hysteresis) Vt: voltage at time detector input pin 22 (CONTRB) time threshold t VAMSEQ 4.5 V output signal to microprocessor t t0 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 MED625 Fig.5 AMS-scan mode without initial input signal. By activating AMS-scan mode, the AMS output level directly indicates whether the input level corresponds to a pause level (VAMSEQ = LOW) or not (VAMSEQ = HIGH). At t0 the AMS-scan mode is activated. Without a signal at Vin, the following initial procedure runs until the AMS output changes to LOW level: due to no signal at Vin the voltage at the level detector input VI (pin 3, CONTRA) remains below the level threshold and the second time constant will be discharged (time detector input Vt). When Vt passes the time threshold level, the time detector output changes to LOW level. Now the initial procedure is completed. threshold level after the rise time tr (at t4), the AMS output changes to HIGH. If the signal burst ends at t5 the level detector input VI falls to its LOW level. When passing the level threshold at t6, the discharging of the second time constant begins. Now the circuit measures the delay time td, which is externally fixed by a resistor and defines the length of a pause to be detected. If no signal appears at Vin within the time interval td, the time detector output switches the AMS output to LOW level at t7. If a plop noise pulse appears at Vin (t8) with a pulse width less than the rise time tr > tb, the plop noise will not be detected as music. The AMS output remains LOW. If a signal burst appears at t3, the level detector input voltage rises immediately and causes its output to charge the second time constant, which supplies the input voltage Vt for the time detector. When Vt passes the upper 1996 Jun 07 Similarly the system handles ‘no music pulses’ tp: when music appears at t11 with a small interruption at t13, this interruption will not affect the AMS output for tp < td. 11 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 Description of the principle timing diagram for AMS-scan mode with initial input signal (see Fig.6) tr: rise handbook, fulltime pagewidth td: delay time tb: burst time tp: pause time tf: fall time AMS on td tf Vin tb<tr tp<tr t Vl Vl: voltage at level detector input pin 3 (CONTRA) level threshold VREF t Vt: voltage at time detector input pin 22 (CONTRB) Vt upper threshold (hysteresis) time threshold t VAMSEQ 4.5 V output signal to microprocessor t t0 t1 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 MED626 Fig.6 AMS-scan mode with initial input signal. At t0 the AMS-scan mode is activated. With an input signal at Vin, the following initial procedure runs until the circuit gets a steady state status. to its maximum voltage level at t1. Now the initial procedure is completed. The following behaviour does not differ from the description in Section “Description of the principle timing diagram for AMS-scan mode without initial input signal (see Fig.5)”. Due to the signal at Vin the voltage at the level detector input VI (pin 3, CONTRA) slides to a value which is defined by a limiter. This voltage causes the level detector output charging the second time constant (time detector input Vt) 1996 Jun 07 12 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 Description of the principle timing diagram for AMS-latch mode without initial input signal (see Fig.7) tr: rise handbook, fulltime pagewidth td: delay time tb: burst time tp: pause time tf: fall time AMS on tr tb<tr td tp<td tf Vin t Vl Vl: voltage at level detector input pin 3 (CONTRA) level threshold VREF t Vt upper threshold (hysteresis) Vt: voltage at time detector input pin 22 (CONTRB) time threshold t internal latch status H L t VAMSEQ 4.5 V output signal to power FET t t0 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 MED627 Fig.7 AMS-latch mode without initial input signal. This is similar to the description of the principle timing diagram from AMS-scan mode. It only differs in its initial behaviour and its rise time tr. (Please notice that the different tr does not occur in the principle timing diagrams for latch and scan mode). A latch forces the AMS output to be HIGH until a signal appears at Vin (t4). After t4 the latch will not affect the output any more until AMS-latch mode is started again. The existence of the latch appears necessary if the AMS output for example drives a stop solenoid via a power FET. The LOW output level will cause a drive of the stop solenoid. This would happen after a maximum time of td occurred without any input signal. If there is no music on tape for a long time (e.g. at tape end), the AMS mode would be activated repeatedly as long as there is no signal at Vin. Thus the circuit waits until first music appears before detecting the pauses. Running in AMS-latch mode, the circuit may be simply applied to drive a stop solenoid via a power FET. So the AMS output signal has not to be processed by a controller. Because there is no processor to make a decision whether there is a plop noise or not, for this mode the rise time tr is extended to approximately 150 ms. By activating AMS-latch mode the AMS output will not change to LOW level at t2 if there is no initial signal at Vin. 1996 Jun 07 13 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 Description of the principle timing diagram for AMS-latch mode with initial input signal (see Fig.8) t : rise time td: delay time tb: burst time tp: pause time tf: fall time AMS on r handbook, full pagewidth td tf Vin tb<tr tp<td t Vl Vl: voltage at level detector input pin 3 (CONTRA) level threshold VREF t Vt: voltage at time detector input pin 22 (CONTRB) Vt upper threshold (hysteresis) time threshold t internal latch status H L t VAMSEQ 4.5 V output signal to power FET t t0 t1 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 MED628 Fig.8 AMS-latch mode with initial input signal. This is similar to the description in Section “Description of the principle timing diagram for AMS-scan mode with initial input signal (see Fig.6)”. It only differs in its rise time tr and a release of its internal latch when voltage Vt passes the upper threshold between t0 and t1. Now the initial procedure is completed. 1996 Jun 07 The following behaviour does not differ from the description in Section “Description of the principle timing diagram for AMS-latch mode without initial input signal (see Fig.7)”. 14 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 INTERNAL PIN CONFIGURATIONS 2 handbook, halfpage + handbook, halfpage + Vref ±0.23 V 1 5V 65 Ω 65 Ω MBH506 MBH507 Fig.9 Pins 1 and 24: output channel. handbook, halfpage + Fig.10 Pins 2 and 23: integrating filter. 3 5V 1.2 kΩ 3.4 kΩ 3.6 kΩ handbook, halfpage + + 4 5V + 675 Ω 10 kΩ MBH509 MBH508 Fig.11 Pins 3 and 22: control voltage. 1996 Jun 07 Fig.12 Pins 4 and 21: high-pass filter. 15 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications handbook, halfpage TEA0675 5 + handbook, halfpage 5V 6 8V + 1 KΩ MBH511 MBD510 Fig.13 Pins 5 and 20: side chain. handbook, halfpage Fig.14 Pin 6: delay time constant. 7 + 5V handbook, halfpage + 8 5V 10 kΩ 100 Ω 5.8 kΩ 1 pF MBH513 MBH512 Fig.15 Pins 7 and 18: equalizing output. 1996 Jun 07 Fig.16 Pins 8 and 17: equalizing input. 16 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 handbook, halfpage 10 5V + 9 handbook, halfpage 10 V 220 Ω 100 kΩ 12 pF 5V MBH514 MBH515 Fig.17 Pin 9: supply voltage. Fig.18 Pins 10, 12, 13 and 15: input channel. + handbook, halfpage handbook, halfpage 14 8V + 2.5 kΩ 11 5V 2.5 kΩ MBH516 MBH517 Fig.19 Pin 11: reference voltage. 1996 Jun 07 Fig.20 Pin 14: head switch input. 17 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications handbook, halfpage + 19 4.6 V MBH518 Fig.21 Pin 19: AMS output and EQ switch input. 1996 Jun 07 18 TEA0675 1996 Jun 07 19 270 kΩ DOLBY B 180 kΩ DOLBY B 100 nF 3 21 1.5 kΩ ON NR 20 4.7 nF 4.7 nF 24 kΩ 24 kΩ Rt 6 19 EQ 18 kΩ 20 kΩ 7 EQ AMP. LOGIC EQ AMP. 20 kΩ 18 70 µs 10 µF 10 kΩ 8 17 10 kΩ 10 µF 9 PRE AMP. POWER SUPPLY PRE AMP. 0.25 V RMS 1 kHz 1000 µF 10 kΩ VCC = 10 V 100 nF 16 Fig.22 Test circuit for power supply ripple rejection. (1) OFF 1.5 kΩ 5 AMS PROCESSOR ON 15 nF 4 DELAY TIME LATCH AND RISE TIME 22 LEVEL DETECTOR 330 nF 2 23 180 kΩ 15 nF OFF 15 10 11 TEA0675 14 27 kΩ 100 µF 10 µF 13 12 MED629 Dual Dolby* B-type noise reduction circuit for playback applications (1) Switched to VCC for AMS-scan mode. output A 10 µF 1 24 270 kΩ 100 nF ndbook, full pagewidth output B 10 µF 330 nF AMS output Philips Semiconductors Preliminary specification TEA0675 TEST AND APPLICATION INFORMATION 1996 Jun 07 20 output A 10 µF 1 24 270 kΩ DOLBY B 180 kΩ 180 kΩ DOLBY B 100 nF 3 21 15 nF 4 1.5 kΩ ON NR 20 4.7 nF 24 kΩ 24 kΩ Rt 6 19 18 kΩ EQ AMP. 20 kΩ 7 LOGIC EQ AMP. 20 kΩ 18 EQ 70 µs 10 µF 10 kΩ 8 17 10 kΩ 10 µF 9 100 nF 16 10 V PRE AMP. POWER SUPPLY PRE AMP. 10 µF 15 200 Ω 10 11 TEA0675 14 27 kΩ 100 µF 10 µF 12 13 MED630 Dual Dolby* B-type noise reduction circuit for playback applications Fig.23 Test circuit for channel separation. 4.7 nF 5 AMS PROCESSOR 15 nF OFF DELAY TIME LATCH AND RISE TIME 22 LEVEL DETECTOR 330 nF 2 23 270 kΩ 100 nF handbook, full pagewidth output B 10 µF 330 nF AMS output Philips Semiconductors Preliminary specification TEA0675 1996 Jun 07 21 270 kΩ DOLBY B 180 kΩ DOLBY B 100 nF 3 21 15 nF 4 DELAY TIME LATCH AND RISE TIME 22 LEVEL DETECTOR 330 nF 2 23 180 kΩ 15 nF 20 (1) 1.5 kΩ 24 kΩ 24 kΩ Rt 6 19 18 kΩ 10 µF 10 kΩ 20 kΩ 7 EQ AMP. LOGIC EQ AMP. 20 kΩ 18 EQ 70 µs 8 17 10 kΩ 10 µF 100 nF 9 16 PRE AMP. 10 V PRE AMP. POWER SUPPLY Fig.24 Test circuit for AMS threshold level. 4.7 nF 5 AMS PROCESSOR 1.5 kΩ 4.7 nF 15 10 11 TEA0675 14 27 kΩ 100 µF 10 µF 12 13 MED631 voltage input Dual Dolby* B-type noise reduction circuit for playback applications (1) Switched to VCC for AMS-scan mode. output A 10 µF 1 24 270 kΩ 100 nF handbook, full pagewidth output B 10 µF 330 nF AMS output Philips Semiconductors Preliminary specification TEA0675 1996 Jun 07 22 1 24 270 kΩ DOLBY B 180 kΩ 180 kΩ DOLBY B 100 nF 3 21 15 nF 20 24 kΩ TP 5 4.7 nF 24 kΩ TP Rt 6 19 18 kΩ 18 EQ AMP. 20 kΩ 10 µF 20 kΩ 7 EQ AMP. LOGIC EQ 70 µs 10 kΩ 8 17 10 kΩ 10 µF 100 nF VCC 9 16 + 10 µF 25 kΩ 10 V Vi 10 µF PRE AMP. POWER SUPPLY PRE AMP. 25 kΩ Fig.25 Test circuit for frequency response (channel B). 4.7 nF AMS OFF 4 1.5 kΩ ON NR AMS PROCESSOR 15 nF OFF DELAY TIME LATCH AND RISE TIME 22 LEVEL DETECTOR 330 nF 2 23 270 kΩ 100 nF − VCC Vi 470 pF 15 14 200 Ω 10 11 TEA0675 27 kΩ 10 µF 100 µF 12 13 MED632 Dual Dolby* B-type noise reduction circuit for playback applications Decode mode: pre-amplifier 30 dB and EQ amplifier 10 dB linear. output A 10 µF output B 330 nF AMS output ndbook, full pagewidth 10 µF Encode mode Philips Semiconductors Preliminary specification TEA0675 1996 Jun 07 23 1 24 270 kΩ DOLBY B 180 kΩ 180 kΩ DOLBY B 100 nF 3 21 15 nF 4 20 4.7 nF Rt 6 19 handbook, full pagewidth EQ AMP. 20 kΩ 7 EQ AMP. LOGIC 18 20 kΩ Fig.26 EMC test circuit. 24 kΩ 5 AMS PROCESSOR 15 nF DELAY TIME LATCH AND RISE TIME 22 LEVEL DETECTOR 330 nF 2 23 270 kΩ 100 nF 10 µF 10 kΩ 8 17 10 kΩ 10 µF 9 470 pF MBH497 PRE AMP. POWER SUPPLY PRE AMP. VCC = 10 V 100 nF 16 470 pF 14 27 kΩ 11 12 13 40 Ω 10 Ω 100 µF 200 Ω 10 µF 200 Ω TEA0675 200 Ω 10 15 200 Ω haed-switch input 470 pF 470 pF Dual Dolby* B-type noise reduction circuit for playback applications Decode mode: pre-amplifier 30 dB and EQ amplifier 10 dB linear. output A 10 µF output B 10 µF 330 nF 4.7 nF 24 kΩ Philips Semiconductors Preliminary specification TEA0675 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 LAYOUT OF PRINTED-CIRCUIT BOARD FOR EMC TEST CIRCUIT (FOR TEA0675T) 63 handbook, full pagewidth 52 470 pF 200 Ω 200 Ω 470 pF 10 kΩ 20 kΩ 24 kΩ 15 nF 100 nF 180 kΩ 27 kΩ 0Ω 0Ω 270 kΩ 4.7 nF 100 nF 40 Ω 10 Ω 0Ω 0Ω TEA0675T 100 nF 4.7 nF 270 kΩ Rt 180 kΩ 470 pF 200 Ω 200 Ω 470 pF 20 kΩ 10 kΩ 100 nF 15 nF 24 kΩ MBH460 Dimensions in mm. Fig.27 Top side with components. 1996 Jun 07 24 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 ook, full pagewidth 63 52 10 µF 10 µF 10 µF S1 330 nF 100 µF MP 100 µF X2 X4 X3 MP X1 HFDR. 330 nF 10 µF MP 10 µF MBH459 Dimensions in mm. Fig.28 Bottom side with components. 1996 Jun 07 25 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 PACKAGE OUTLINES SDIP24: plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1 ME seating plane D A2 A A1 L c e Z b1 (e 1) w M MH b 13 24 pin 1 index E 1 12 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.8 1.3 0.8 0.53 0.40 0.32 0.23 22.3 21.4 9.1 8.7 1.778 10.16 3.2 2.8 10.7 10.2 12.2 10.5 0.18 1.6 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT234-1 1996 Jun 07 EUROPEAN PROJECTION 26 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.050 0.42 0.39 inches 0.043 0.055 0.016 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013AD 1996 Jun 07 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-24 27 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. SDIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1996 Jun 07 TEA0675 28 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications TEA0675 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Jun 07 29 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications NOTES 1996 Jun 07 30 TEA0675 Philips Semiconductors Preliminary specification Dual Dolby* B-type noise reduction circuit for playback applications NOTES 1996 Jun 07 31 TEA0675 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 805 4455, Fax. +61 2 805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com/ps/ (1) ADDRESS CONTENT SOURCE August 6, 1996 © Philips Electronics N.V. 1996 SCA49 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 517021/50/04/pp32 Date of release: 1996 Jun 07 Document order number: 9397 750 00898