NXP Semiconductors User’s guide Document Number: KTFS4500-FS6500UG Rev. 1.0, 5/2016 KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards Figure 1. FS45xx/FS65xx evaluation board © 2016 NXP B.V. Contents 1 Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Kit contents/packing list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Jump start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Required equipment and software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Getting to know the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Board overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Board features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 Board overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.6 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 Jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 Test point definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.9 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.10 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 Configuring the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 Evaluation board settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 VCCA and VAUX setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 VCORE settings and related configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 MCU settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 Installing the FlexGUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 Creating and using a register configuration file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Using the FlexGUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 Use case example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 Assembly layer top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 Assembly layer bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Board bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 Accessory item bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 2 NXP Semiconductors Getting started 1 Getting started 1.1 Kit contents/packing list The KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM kit contents include: • Assembled and tested evaluation boards/modules in anti-static bag • Connector, terminal block plug, 2 pos., str. 3.81 mm • Connector, terminal block plug, 10 pos., str. 3.81 mm • Cable, assy, USB-STD A to USB-B-mini 3.0 ft. • Quick start guide 1.2 Jump start NXP’s analog product development boards provide an easy-to-use platform for evaluating NXP products. The boards support a range of analog, mixed-signal and power solutions. They incorporate monolithic ICs and system-in-package devices that use proven high-volume SMARTMOS technology. NXP products offer longer battery life, a smaller form factor, reduced component counts, lower cost and improved performance in powering state of the art systems. 1. Go to the tool summary page: www.nxp.com/KITFS6522LAEEVM www.nxp.com/KITFS6523CAEEVM www.nxp.com/KITFS4503CAEEVM 2. Review the tool summary page 3. Look for Jump Start Your Design 4. Download the documents, software, and other information 5. Once the files are downloaded, review the user guide in the bundle. The user guide includes setup instructions, BOM, and schematics. Jump start bundles are available on each tool summary page with the most relevant and current information. The information includes everything needed for design. 1.3 Required equipment and software This kit requires the following items: • Power supply with a range of 8.0 V to 40 V and a current limit set initially to 2.0 A • Standard A plug to Mini-B plug USB cable • FlexGUI graphical user interface • FlexGUI register definition XML file KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 3 Getting to know the hardware 2 Getting to know the hardware 2.1 Board overview The KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM are hardware evaluation tools supporting system designs based on NXP’s FS4500 and FS6500 product families. The kits allow testing the devices as an integral part of the overall system being developed. They provide access to all FS45xx and FS65xx functions (SPI, IOs) and support functional modes such as debug, normal, buck, and boost. Table 1. Kits supporting the FS45xx/FS65xx family KIT name KITFS6522LAEEVM Supported silicon (1) KITFS6523CAEEVM KITFS4503CAEEVM (1) Options MC33FS6522LAE CAN, LIN, No FS1b, VCORE DC/DC 2.2 A MC33FS6523CAE CAN, FS1b, No LIN, VCORE DC/DC 2.2 A MC33FS4503CAE CAN, FS1b, No LIN, VCORE LDO 500 mA Notes 1. Prototype only. Contact sales for availability. 2.2 Board features The main features of the KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards are: • VBAT power supply either through power jack (2.0 mm) or phoenix connector • VCORE configuration:1.23 V, 3.3 V, and 5.0 V • VCCA configuration: – 3.3 V or 5.0 V – Internal transistor or external PNP • VAUX configuration: 3.3 V or 5.0 V • Buck or boost setting • DFS configuration • Ignition key switch • LIN bus (optional) • CAN bus • FS0B • FS1B (Option) • IO connector (IO_0 to IO_5) • Debug connector (SPI bus, CAN digital, LIN digital, RSTB, FS0B, INTB, Debug, MUX_OUT) • Signalling LED to give state of signals or regulators • KL25Z MCU installed on board for easy connection to host computer on USB link KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 4 NXP Semiconductors Getting to know the hardware 2.3 Block diagram J4 JP1 VPRE (switching) SW2 VBAT PI Filter J8 SW4 KEY VSUP VPRE VCORE VCORE (switching) VCCA VCCA PMOS or ext. PNP VAUX VAUX PNP IO0 Power Supply Connector J36 IO1_to_5 I/O KL25 MCU FS54XX FS65XX IOs ADC Regulators J37 J33 USB USB to SPI J23 LIN (Option) SPI Interface TXL LIN Transceiver RST FS0/1 MUX_OUT CAN Transceiver RXL LIN/Vpu_fs TXC Debug J30 RXC CANH CAN CANL Figure 2. Block diagram 2.4 Device features The FS65xx/FS45xx are multi-output power-regulating SMARTMOS devices aimed at the automotive market. They include CAN flexible data (FD) and/or LIN transceivers. Multiple switching and linear voltage regulators—including low-power mode (32 μA) — provide a variety of wake-up capabilities. An advanced power management scheme maintains high efficiency over a wide range of input voltages (down to 2.7 V) and output current ranges (up to 2.2 A). The FS45xx/FS65xx family includes enhanced safety features with multiple fail-safe outputs. The devices are capable of fully supporting safety-oriented system partitioning with a high integrity safety level (up to ASIL D). The built-in CAN FD (flexible data-rate) interface meets all ISO11898-2 and -5 standards. The LIN interface is compliant with LIN protocol specifications 2.0, 2.1, 2.2, and SAEJ2602-2. KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 5 Getting to know the hardware Table 2. FS45xx/FS65xx features Device Description Features • Battery voltage sensing and MUX output pin • Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost and standard buck • Switching mode power supply (SMPS) dedicated to MCU core supply, from 1.0 V to 5.0 V, delivering up to 2.2 A FS4500/ FS6500 Automotive control devices • Linear voltage regulator dedicated to auxiliary functions, or to sensor supply (VCCA tracker or independent), 5.0 V or 3.3 V • Linear voltage regulator dedicated to MCU A/D reference voltage or I/Os supply (VCCA), 5.0 V or 3.3 V • 3.3 V keep alive memory supply available in low-power mode • Long duration timer available in low-power mode (1.0 s resolution) • Multiple wake-up sources in low-power mode: CAN, LIN, IOs, LDT • Five configurable I/Os • Regulator voltage read back (via ADC) MKL25Z Kinetis L 32-bit MCU USB controller • SPI command and control • IO checking • CAN and LIN TX signal support • MCU disconnect capability KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 6 NXP Semiconductors Getting to know the hardware 2.5 Board overview The primary components of the evaluation boards are the onboard MCUs. The boards include an FS45xx or FS65xx and provide full access to all the device’s features. An MKL25Z MCU USB controller enables access to the FS45xx/FS65xx through a USB connection. In normal operation, configuration and monitoring applies to the on-board FS45xx/FS65xx device. However, the board can be totally isolated from the on-board MCU. This allows connection to an off-board MCU without interference from the on-board device functions. 18 17 16 15 1 14 13 2 12 3 4 11 5 6 8 7 9 10 Figure 3. Board description Table 3. Board description Number Description 1 VBAT connectors — Use either jack connector or Phoenix connector to supply board 2 VBAT switch — Select VBAT from jack or from Phoenix connector 3 Ignition key — Ignition key from car 4 LIN bus — LIN bus connector 5 CAN bus — CAN bus connector 6 I/Os — Input and Output from FS45XX/FS65XX (IO0, IO2, IO3, IO4, IO5, GND, VKAM, VDDIO, VBAT) 7 DBG mode select 8 Debug connector — Could be used for debug purpose (CAN TX/RX, LIN TX/RX, SPI, Debug, FS0B, FS1B, INTB) 9 VCCA & VAUX selection — Select 3.3 V/5.5 V configuration for VCCA & VAUX 10 MCU to FS65/FS45 connection — Connects part or totality of signals between the KL25Z MCU and FS65XX/FS45XX. 11 KL25 MCU — Location of MCU and USB connector for control through FlexGUI 12 DFS mode select — Enables or disables the deep fail-safe function KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 7 Getting to know the hardware Table 3. Board description (continued) Number Description 13 VCORE selection — Selects either 1.23, 3.3, or 5.0 V on VCORE DC/DC 14 Compensation network — Selects either Network 1 or 2 15 Power supplies LED — Visualizes regulator state (on or off). The switches can disconnect LEDs 16 Power supplies — Connector for power supplies (CAN_5V/VPRE/VCORE/VCCA/VAUX) 17 Buck/buck or boost selection — These jumpers select VPRE mode as a buck or buck or boost. 18 FS45xx/FS65xx KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 8 NXP Semiconductors Getting to know the hardware 2.6 LEDs The LEDs are located on the board as shown in Figure 4. Vpre Vaux Vcca VCor e Vbat CAN_5 V IO_ RST0 b KEY FS0 b Green LED INT b P3V3_KL2 5 FS1 b Red LED Figure 4. LEDs The LEDs can be switched on or off through jumpers or switches. Table 4 shows the function of all LEDs. Table 4. LEDs Schematic label Name Color LED activation Description D1 VPRE Green D1/SW1-1 VPRE on D3 VAUX Green D3/SW1-2 VAUX on D4 VCCA Green D4/SW1-3 VCCA on D5 VCORE Green D5/SW1-4 VCORE on D10 IO_4 Green D10/J21-2/3 D11 KEY Green D11/J16 D13 RSTB Red D13/J25 RSTB asserted (logic level = 0) D14 INTB Red D14/J28 INTB asserted (logic level = 0) D15 P3V3_KL25 Green D15/NA MCU KL25 power supply ON D17 CAN_5V Green D17/J27 CAN_5V ON D18 VBAT Green D18/J28 VBAT ON D20 FS0B Red D20/J39 FS0B asserted (logic level = 0) D21 FS1B Red D21/J40 FS1B asserted (logic level = 0) IO_4 high level Ignition key switch to VSUP3 (tied to IO_0) KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 9 Getting to know the hardware 2.7 Jumper settings Figure 5 shows the location of all jumpers on the board. Table 5 provides the name and function of each jumper. SW5 SW3 SW6 Jumper Figure 5. Jumpers Table 5. Jumper settings Schematic label Function Pin Number JI VCORE load 1-2 Connect 30 Ω resistor load on VCORE J2 VPRE mode 1-2 3-4 Both jumper plugged: VPRE Buck configuration Both jumper unplugged: VPRE Boost configuration J3 VPRE load 1-2 Connect 60 Ω resistor load on VPRE J5 VDDIO selection J6 J7 J9 J10 J11 J12 Jumper/pin function 1-2 VDDIO referenced to VCCA 2-3 VDDIO referenced to VCORE or P3V3_KL25Z. Configuration is selected with R106 or R107, respectively VCORE or P3V3_KL25Z VCORE output capacitor 1-2 VCORE output capacitance. When set, adds 20 µF on VCORE. Comp. network1 1-2 Select compensation network1. Used in conjunction with J10:1-2 Comp. network2 3-4 Select compensation network2. Used in conjunction with J10:3-4 VCCA PNP External PNP used Used in conjunction with J11:1-2 VCCA MOS 1-2 Internal MOS used Used in conjunction with J11:2-3 Comp. network1 1-2 Select compensation network1. Used in conjunction with J7:1-2 Comp. network2 3-4 Select compensation network2. Used in conjunction with J7:3-4 VCCA PNP 1-2 External PNP used in conjunction with J11:1-2 VCCA MOS 2-3 Internal MOS used in conjunction with J11:2-3 VSUP1-2 1-2 Connect VSUP1 and VSUP2 to the power supply on the output of PI filter VSUP3 3-4 Connect VSUP3 to the power supply (before PI filter) KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 10 NXP Semiconductors Getting to know the hardware Table 5. Jumper settings (continued) Schematic label Function J13 VCORE setting Pin Number Jumper/pin function 1-2 VCORE = 1.23 V 3-4 VCORE = 3.3 V 5-6 VCORE = 5.0 V J14 VSENSE 1-2 Connect VSENSE to VBAT J15 Debug mode 1-2 ON: Debug mode off: normal mode J16 KEY LED 1-2 Enable KEY signaling LED J18 DFS 1-2 DFS enabled 2-3 DFS disabled J21 IO_4 1-2 IO_4 tied to GND through 510 k 2-3 IO_4wired on LED signaling works in conjunction with J19:1-2 IO_5 1-2 Connect IO_5 to KL25Z and I/O connector (J36-5) VKAM 2-3 Connect VKAM to I/O connector(J36-8) and 220 nF capacitor. J25 RSTB 1-2 Enable RSTB signaling LED J26 INTB 1-2 Enable INTB signaling LED J27 CAN_5V 1-2 Enable CAN_5V signaling LED J28 VBAT 1-2 Enable VBAT signaling LED 1-2 VCORE = 1.23 V 3-4 VCORE = 3.3 V 5-6 VCORE = 5.0 V 1-2 Connect FB_Core to FCRBM 2-3 Connect potentiometer R40 to FCRBM 1-2 Connect IO_0 to ground through 510 k 1-2 FS0b pull-up connected to VSUP3 2-3 FS0b pull-up connected to VDDIO J22 VCORE drift J31 J32 FCRBM J35 IO-0 J38 FS0B Pull-up J39 FS0B LED 1-2 Enable FS0B signaling LED J40 FS1B LED 1-2 Enable VPU FS signaling LED (FS1B) J41 VCORE 1 SMB connector on VCORE J42 VPRE 1 SMB connector on VPRE J43 IO_5 1-2 Connect IO_5 to ground through 5.1 k KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 11 Getting to know the hardware 2.8 Test point definitions Figure 6 shows the location of the test points on the board. CAN_5V PGND Vcca Vaux Vcore Vpre GND GND VSW_Pre VSW_Core FCRBM Vsup3 TC_USB_ID_TP P5V0_USB_VBUS FS1b RSTb FS0b MUX_OUT CANH INTb LIN GND GND SELECT GND CANL Figure 6. Test points The following test points provide access to various signals to and from the board. Table 6. Test points Schematic label Signal name Schematic label/description TP1 GND Ground TP2 GND Ground TP3 VPRE TP3/VPRE regulator output voltage TP4 GND Ground TP5 CAN_5V TP6 GND Ground TP7 VAUX TP7/VAUX output voltage TP8 GND Ground TP9 VCCA TP9/VCCA output voltage TP10 PGND TP10/power ground TP11 VCORE TP11/VCORE output voltage TP12 GND TP5/CAN power supply Ground TP13 GND TP14 PGND Ground TP15 VSW_PRE TP16 VSUP3 TP16/VSUP3 voltage TP17 GND Ground Power ground TP15/VPRE switcher signal KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 12 NXP Semiconductors Getting to know the hardware Table 6. Test points (continued) 2.9 Schematic label Signal name TP18 VSW_Core Schematic label/description TP18/Vcore switcher TP19 SELECT TP19/SELECT pin voltage TP20 TC_USB_ID_TP TP20/USB Identification pin TP21 LIN TP22 GND TP23 FCRBM TP24 CANH TP24/CAN high TP25 CANL TP25/CAN low TP26 MUX_OUT TP21/LIN bus signal Ground TP23/feedback core resistor bridge monitoring TP26/MUX_OUT signal TP27 INTB TP27/INTB/interrupt pin level. Active low TP28 RSTB TP28/Reset. Active low TP29 FS1B TP29/fail-safe 1 signal. Active low TP30 FS0B TP30/fail-safe 0 signal. Active low TP31 GND TP32 P5V_USB_CONN_VBUS TP33 GND Ground TP32/USB power supply level Ground Connectors Figure 7 shows the location of connectors on the board. Table 7 and Table 8 list the pin-outs for each connector. Power Supply Vbat (Jack) Vbat (Phoenix) CAN USB LIN I/Os Debug SWD Figure 7. Connectors KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 13 Getting to know the hardware 2.9.1 VBAT connectors (J4 and J8) VBAT connects to the board either through jack connector (J4) or Phoenix connector (J8) at the user’s discretion. Switch SW2 switches from one source to the other. Table 7. VBAT jack connector (J4) Pin number Connection 1 VBAT 2 Ground Description Connects to VBAT when switch SW2 is set to VBAT Connects to ground when switch SW2 is set to ground Table 8. VBAT Phoenix connector (J8) Pin number Connection 1 VBAT 2 Ground Description Connects to VBAT when switch SW2 is set to VBAT Connects to ground when switch SW2 is set to ground 2.9.2 Debug connector (J37) The Debug connector (J37) gives access to the FS65xx main signal for debug or experimentation purposes. Table 9. Debug connector (J37) Pin number Connection Description 1 FSOB Fail-safe 0. 2 VDDIO Reference voltage for IOs. 3 MISO SPI, Master Input Slave Output 4 RSTB Reset, active low 5 MOSI SPI Master Output Slave Input 6 GND Ground 7 SCLK SPI serial clock 8 GND Ground 9 NCSB SPI chip select, active low. 10 GND Ground 11 MUX_OUT 12 INTB 13 RXD_L LIN receiver data. Logic level. 14 TXD_L LIN transmit data. Logic level. 15 GND Ground 16 FS1B Fail-safe 1 17 RXD CAN receiver data. Logic level 18 TXD CAN transmit data. Logic Level 19 DBG Debug pin selection 20 GND Ground Multiplexer output Interrupt output. Active low. KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 14 NXP Semiconductors Getting to know the hardware 2.9.3 LIN connector (J23) The LIN connector is mounted on all three kits, but LIN is supported only on the KITFS6522LAEEVM. Table 10. LIN connector (J23) Pin number Connection 1 LIN 2 GND Description Connects to the LIN bus Connects to ground. 2.9.4 CAN connector (J30) Table 11. CAN connector (J30) Pin number Connection Description 1 CANH Connects to the CANH bus line 2 CANL Connects to CANL bus line 2.9.5 USB connector (J33) The USB connector provides a communication link between the evaluation board’s MKL25Z device and a PC running the FlexGUI software. Table 12. USB connector (J33) Pin number Connection Description 1 P5V0_USB_CONN_VBUS 2 USB_CONN_DN Data– 3 USB_CONN_DP Data+ 4 TC_USB_ID_TP USB OTG ID 5 GND +5.0 V DC supply Ground 2.9.6 I/O connector (J36) The I/O connector accesses the device under test (DUT) IO and VKAM signals. Table 13. I/O connector (J36) Pin number Connection Description 1 Not connected Not connected 2 IO_0 Input/Output 0 3 IO_3 Input/Output 3 4 IO_2 Input/Output 2 5 IO_5 Input/Output 5 6 IO_4 Input/Output 4 7 VDDIO Reference voltage for IOs. 8 VKAM Keep alive memory voltage 9 VBAT Battery voltage 10 GND Ground KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 15 Getting to know the hardware 2.9.7 Power supply connector (JP1) The power supply connector (JP1) connects any of the SBC regulators to an external load or board for evaluation purposes. Table 14. Power supply connector (JP1) 2.10 Pin number Connection Description 1 CAN_5V 2 GND Ground 3 VCCA VCCA output voltage 4 GND Ground 5 VAUX VAUX auxiliary voltage regulator 6 GND Ground CAN voltage regulator 7 VCORE 8 GND Ground 9 VPRE VPRE regulator output regulator 10 GND Ground VCORE voltage output Switches SW5 SW3 SW6 OFF ON Switches Figure 8. Switches KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 16 NXP Semiconductors Getting to know the hardware 2.10.1 SW3 Table 15. SW3 Position Function 1 IO_O Description 2 NA 3 IO_2 Connection between IO_2 from product to MCU 4 IO_3 Connection between IO_3 from product to MCU 5 IO_4 Connection between IO_4 from product to MCU 6 IO_5 Connection between IO_5 from product to MCU Connection between IO_O from product to MCU Not used 2.10.2 SW5 Table 16. SW5 Switch VCCA VAUX 1–8 3.3 V 3.3 V 2–7 5.0 V 5.0 V 3–6 3.3 V 5.0 V 4–5 5.0 V 3.3 V 2.10.3 SW6 Table 17. SW6 Position Function Description 1 RSTB Connection between RSTB from product to MCU 2 FS0B Connection between FS0B from product to MCU 3 FS1B Connection between FS1B from product to MCU 4 DBG Connection between DBG from product to MCU KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 17 Configuring the hardware 3 Configuring the hardware 3.1 Connecting the hardware The KITFS6522LAEEVM/KITFS6523CAEEVM/KITFS4503CAEEVM must be connected to a PC through the USB port on the board. A 13.5 V power supply connects either to a jack connector (J4) or a Phoenix connector (J8). The evaluation board connects to an external load or another board through connector JP1. Caution: To avoid damaging the board, the VBAT voltage must not exceed 40 V. 1. With the power switched off, attach the DC power supply to either the Jack connector (J4) or the Phoenix connector (J8) on the evaluation board. (There is no difference between the two connectors other than plug compatibility.) 2. Attach a load or an external board through connector JP1. 3. Connect a USB cable from the evaluation board USB port (J33) to the USB port on a PC with the FlexGUI installed. 4. Turn on the DC power supply. Figure 9 illustrates the hardware configuration. 13.5 V Power Supply USB Cable USB Port J33 + - Connector J4 or J8 PC with FlexGUI software installed FS65XX / FS45XX regulator output KITFS4503CAEEVM/ KITFS6522LAEEVM/KITFS6523CAEEVM External Load/Board (Resistor Load or MCU power Supply) Figure 9. Evaluation board hardware configuration KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 18 NXP Semiconductors Evaluation board settings 4 Evaluation board settings 4.1 VCCA and VAUX setting To select various voltage levels on VCCA and VAUX, set the switch SW5 as shown in Table 18 and Figure 10 below: Table 18. SW5 VCCA/VAUX voltage configurations Switch VCCA VAUX 1–8 3.3 V 3.3 V 2–7 5.0 V 5.0 V 3–6 3.3 V 5.0 V 4–5 5.0 V 3.3 V Vpr e SELECT 1 2 3 4 SW5 8 7 6 5 R66 R65 R64 R63 5.1K 12K 24K 51K J18 3 2 1 G ND Figure 10. VCCA and VAUX voltage settings VCCA regulator can be configured to use the internal PMOS transistor at current levels up to 100 mA. To achieve higher current levels (up to 300 mA), use a PNP external transistor. Table 19 and Figure 11 show the jumper settings for both configurations. Table 19. J9/J11 VCCA PNP configurations Jumper J9 J11 Internal MOS OFF 2–3 External PNP ON 1–2 Vpre J11 VCCA_B 1 2 Vcca_E 1 2 3 J9 3 2 1 PHPT60603PY Q50 4 5 Vcc a Vcca [4] C53 4.7uF GND Figure 11. VCCA transistor setting The VCCA regulator is always tied to the external PNP transistor. Resistors R105 and R10 limit the power dissipation in the PNP transistor. KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 19 Evaluation board settings 1 2 3 Vaux_E PHPT60603PY Q 51 5 Vaux_B 4 Vaux R105 0 R109 Vaux [4] 2.4 C56 4.7uF R105 for Vau x = 5V R109 for Vau x = 3.3V GN D Figure 12. VAUX external transistor 4.2 VCORE settings and related configurations 4.2.1 VCORE and F45xx versus FS65xx The FS45xx family of devices only support VCORE LDO (low dropout) voltage regulators. The FS65xx family only supports VCORE DC/DC voltage regulators. The evaluation board circuitry accommodates this discrepancy by implementing a separate circuit network for each of the two device families. Populating or not populating resistors R7 and R8 depend on which device family is in use and determines which network is enabled. For the FS45xx family, R7 is populated and R8 is not populated. For the FS65xx family, R8 is populated and R7 is not populated. Because resistor R8 is not populated for FS45xx devices, the compensation network is also disabled for those devices. See Figure 13. V core Pr od uc t wi th V co re L DO o nl y (F S4 5X X) VSW _C ore R7 DN P 0 Vc ore [4] C1 10uF C2 10uF 4. 32K 24. 9K 43K Vcore Pr od uc t wi th V co re D C/ DC o nl y (F S6 5X X) C9 10nF C 15 180PF C5 22uF 0 J6 2 4 A 1 2 J7 PGN D D7 P MEG3030B EP R 10 200 R 51 15 J 13 1 3 PGN D H D R 1X2 R6 510 1 3 5 PGN D R 12 15 B oos t _c ore R 52 15 FB _C ore PGN D C4 220PF J 7/ J1 0 J1 1 2 R 15 R 13 R 58 R8 C C 19 0. 1UF 2. 2uH 2 2 4 6 L4 1 C3 680P F R9 8. 06K P GN D FB _C ore 1 - 2 C om p. N et wo rk 1 3 - 4 C om p. N et wo rk 2 R 56 18K R 57 39K J 10 C om p_core 1 3 2 C 52 4 1000PF C7 150pF J 13 1 - 2 GN D V co re = 1 .2 3V 3 - 4 V co re = 3 .3 V 5 - 6 V co re = 5 .0 V Figure 13. VCORE configuration KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 20 NXP Semiconductors Evaluation board settings 4.2.2 Compensation network Both LDO and DC/DC voltage regulators use VCORE voltage feedback to control the output voltage. For this reason, two separate external bridges enable feedback support for either FS45xx or FS65xx devices (see Figure 13). For FS45xx devices using static (steady-state) LDO regulators, a simple resistor bridge (resistors R15/R13/R58 and R9) in conjunction with jumper settings on jumper J13 determines the feedback voltage. For FS65xx devices using DC/DC voltage regulators, a selectable pair of RC voltage dividers control the dynamic behavior of the regulator. One RC divider --compensation network 1-- consists of the resistor-capacitor series R10/C4/R57/C52. The other RC divider --compensation network 2-- consists of the resistor-capacitor series R6/C3/R56/C7. Jumpers J7 and J10 select which of the two compensation networks is enabled. The default value for compensation network 1 is 1.23 V. For compensation network 2, the default value is 3.3 V. These values can be changed for other configurations. The compensation network tool referenced in Table 26 is useful in calculating the appropriate values. Table 20 illustrates the jumper settings for each feedback voltage level. Table 20. VCORE compensation network settings Jumper setting Static behavior Dynamic behavior VCORE J13 J7 J10 1.23 V 1–2 1–2 1–2 3.3 V 3–4 3–4 3–4 5.0 V 5–6 (2) (2) Notes 2. Use compensation network tool to calculate value 4.2.3 FCRBM resistor bridge The feedback core bridge monitoring (FCRBM) resistor bridge is an evaluation board safety feature. The bridge generates the same voltage as the bridge connected to the FB_core pin. If the difference between the two voltages is greater than the VCORE_FB_DRIFT value, the FS state machine is impacted (refer to data sheet). To implement this functionality, use jumper J31 to configure the second resistor bridge as shown in Figure 14. Then, set the potentiometer R40 to match the voltage of the first VCORE bridge. To disable the FCRBM function, place a jumper on position 1–2 of J32. This connects FB_CORE directly to the FCRBM bridge, causing the drift to be zero. 4.32K 24.9K 43K V cor e Vc ore = 1 .23V 3 - 4 5 - 6 Vc ore = 3 .3V Vc ore = 5 V J31 3 1 3 5 1 - 2 2 4 6 R 32 R 33 R60 J31 VcoreFB Drift J 32 2 R40 5. 0K FC RB M FB_C ore 1 3 2 1 R42 5. 6K GND Figure 14. FCRBM bridge resistor KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 21 Evaluation board settings 4.3 MCU settings 4.3.1 MCU jumper configuration Table 21. MCU Jumper configuration Schematic label Pin number Function Jumper/pin function 1–2 Connect MISO to KL25Z 3–4 J24 Connect MOSI to KL25Z SPI 5–6 Connect MSCLK to KL25Z 7–8 Connect NCSB to KL25Z 1–2 J29 3–4 1–2 J34 Connect RXD_L LIN to KL25Z LIN Connect TXD_L LIN to KL25Z Connect RXD CAN to KL25Z CAN 3–4 SPI Connect RXD CAN to KL25Z J24 [3] MISO [3] MOSI [3] SCLK [3] NCSb 1 3 5 7 2 4 6 8 MISO_SH MOSI_MCU SCLK_MCU NCSb_MCU HDR_2X4 CAN [3] RXD [3] TXD 1 3 2 4 RXD_SH TXD_MCU 2 4 RXD_L_SH TXD_L_SW J34 HDR 2X2 LIN [3] RXD_L [3] TXD_L 1 3 J29 HDR 2X2 Figure 15. MCU jumper configuration 4.3.2 MCU switch configuration 4.3.2.1 Switch SW3 Table 22. Switch SW3 Position Function 1 IO_O Description Connection between IO_O from product to MCU 2 NA 3 IO_2 Connection between IO_2 from product to MCU Not used 4 IO_3 Connection between IO_3 from product to MCU 5 IO_4 Connection between IO_4 from product to MCU 6 IO_5 Connection between IO_5 from product to MCU KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 22 NXP Semiconductors Evaluation board settings 1 2 3 4 5 6 [3] I O_0 [3] I O_2 [3] I O_3 [ 3] IO _4 [ 3] IO _5 SW3 12 11 10 9 8 7 IO_SW_0 IO_SW_2 IO_SW_3 IO_SW_4 IO_SW_5 SW_DIP-6_SM Figure 16. Switch SW3 4.3.2.2 Switch SW6 Table 23. Switch SW6 Position Function Description 1 RSTB Connection between RSTB from product to MCU 2 FS0B Connection between FS0B from product to MCU 3 FS1B Connection between FS1B from product to MCU 4 DBG Connection between DBG from product to MCU [3] R STb [3] F S0b [3] F S1b [3] D BG 1 2 3 4 SW6 8 7 6 5 RSTb_SW FS0b_SW FS1b_SW DBG_SW SW DI P-4/SM Figure 17. Switch SW6 4.3.3 MCU analog input To assure the complete isolation of analog signals connected from an external component to the MCU, remove input resistance as applicable for the following: • VPRE tied to MCU through R82 • VCORE tied to MCU through R89 • VAUX tied to MCU through R90 • VCCA tied to MCU through R82 • CAN_5V tied to MCU through R80 • MUX_OUT tied to MCU through R71 • VDDIO tied to MCU through R70 • VKAM tied to MCU through R79 KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 23 Software 5 Software The KITFS6522LAEEVM/KITFS6523CAEEVM/KITFS4503CAEEVM is bundled with software allowing the user to interact directly with the onboard MCU during the development process. The boards contain an MKL25Z Kinetis processor pre-loaded with firmware controlling communication with the FS45xx/FS65xx MCU. A graphical user interface installed on a PC serves as the user interface to the evaluation board. When connecting the evaluation board to a PC through a USB cable, the following data exchanges are available: • SPI access (read and write) to FS45xx/FS65xx • ADC readout, connected to regulators – VPRE – VCORE – VAUX – VCCA – CAN_5V – MUX_OUT – VDDIO – VKAM • I/O readout, connected to IO_0 to IO_5 • FS0B/FS1B readout • RSTB readout • CAN generated TX signal • LIN generated TX signal with loopback checking Note that MCU connections to FS45XX/FS65XX can be fully isolated by removing related jumpers and switching off the related switch. The software bundle also includes an XML file containing register descriptions for the FS45xx or FS65XX (depending on the evaluation board). This file must be installed for the GUI to work properly. In addition, an optional Excel file can be created to facilitate setting several registers at a click. FS45xx/FS65xx Pre-loaded firmware USB MyRegs.xls FlexGUI MKL25Z FSxxxx.xml KITxxx evaluation board Windows Laptop Figure 18. Software overview 5.1 Installing the FlexGUI The FlexGUI graphical user interface provides a PC-based interface for accessing the evaluation board and exercising FS45xx/FS65xx functions. The GUI runs on any Windows 8, Windows 7, Vista, or XP-based operating system. To install the FlexGUI software: 1. Go to the evaluation board tool summary page 2. Under Jump Start Your Design, click on the Get Started with the KITFS65xx link. 3. From the list of files that appear, click on the FlexGUI link. The software downloads to the PC and initiates the installation. An installation wizard guides the user through the process. Upon completion, the GUI executable (FlexGUI.exe), and the relevant register description XML file are installed on the system. 4. To simplify launching the FlexGUI, create a .bat file with the following commands: C:\Program Files (x86)\FlexGUI\bin\FlexGUI.exe C:\Program Files (x86)\FlexGUI\Sequences&Config\FSxxxx.xml KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 24 NXP Semiconductors Software 5.2 Creating and using a register configuration file Creating an Excel register configuration file allows the user to initialize the evaluation board MCU with a predefined set of register values. To create a register configuration file, do the following: 1. Open a new Excel spreadsheet file and label the first three columns in row 1 hex, registers and comment. Notice that the first two columns —hex and registers— are mandatory. The comment column is optional. 2. In the hex column (column A), enter the data or address to be assigned to each register. The address and data must be contained in two bytes and must be expressed as a hexadecimal value. Enter one row per register. 3. In the registers column (column B), enter the register name associated with the value in the hex column. 4. In the comments column (column C), enter any comments desired. Data in this column is not processed by the FlexGUI. Figure 19 illustrates a typical register configuration file. Mandatory Optional Figure 19. Register configuration Excel file 5. Launch FlexGUI. When FlexGUI opens, click the load sequence button to load the register configuration file (see Figure 20). 1 2 Figure 20. Loading the register configuration example file KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 25 Software 6. Send the resister configuration file to the FS45xx/FS65xx by clicking the send sequence button (see Figure 20). 5.3 Using the FlexGUI To start the FlexGUI, do the following: 1. Configure the hardware as described in Section 3.1, Connecting the hardware. 2. To launch the FlexGUI, execute the .bat file created in Section 5.1, Installing the FlexGUI. 5.4 Use case example This example assumes the user has configured the hardware as shown in Figure 9 and put the evaluation board into debug mode by placing a connector on jumper J15 (see Table 5). After launching the FlexGUI, the example configures registers to disable IO_23_FS safety mode, disable the watchdog and release the FSx pins. 1. Create an Excel file configured as shown in Table 24. For details on creating an Excel register configuration file, see Section 5.2, Creating and using a register configuration file. Table 24. Use case register configuration Excel file example HEX Registers Comment C424 BIST CB0C INIT_FSSM 8900 INIT_INT D34D WD_refresh_0 1st Watchdog refresh answer D29B WD_refresh_1 2nd Watchdog refresh answer ABIST2_VAUX enabled => Start VAUX ABIST IO_23_FS Disabled Close main machine initialization sequence D237 WD_refresh_2 3rd Watchdog refresh answer D26E WD_refresh_3 4th Watchdog refresh answer D2DC WD_refresh_4 5th Watchdog refresh answer D2B9 WD_refresh_5 6th Watchdog refresh answer D372 WD_refresh_6 7th Watchdog refresh answer D4A7 RELEASE_FSxB Release FS0B & FS1B pins 2. To use the register configuration file, open FlexGUI, then load the register configuration file and send it to the evaluation board (see Figure 20). Now read or write any bit from the FS45xx/FS65xx on-board MCU as shown in Table 21. Figure 21. FlexGUI register window Register values display in the register value window as shown in Figure 22. KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 26 NXP Semiconductors Software Figure 22. FlexGUI register value window KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 27 A B C D GND S1 1 2 GND INTb RSTb J25 1 2 2 1 RED D13 R24 2K J32 2 1 LIN A R42 5.6K Vsup3 J31 C58 10nF DNP L2 LIN 1uH Vsup3 5 PGND NX3008NBK Q2 1 LED/GRN D10 R19 1.5K Vpre Vsup R104 J35 GND C21 2.2UF R23 510K R27 5.1K R74 J30 C27 10nF Vpre FS_PU GND R14 10K 1 2 CANH Vcore Vcca CANL R36 120 R22 510K GND IO_4 NORMAL OFF CAN DEBUG ON DBG C93 0.47UF IO_5 KEY Vbat 4 J16 J28 J27 Vpre CAN_5V Vaux R11 15 C8 470PF PGND PGND C18 0.1UF VSW_Pre Vpre 1 2 3 4 SW1 5.1K 8 7 6 5 R20 R39 1.2K 1.2K 560 Vpre 1 R108 16.2K D5 LED/GRN C D4 LED/GRN C C C A C D11 LED/GRN A D18 LED/GRN A D17 LED/GRN A C69 1000PF R76 C24 3.3uF GND R29 R98 DNP R5 GND R4 Vkam 560 560 1.5K R110 510K GND 1 J22 PGND C25 0.22UF Vcca 3 C20 1000PF GND R55 30 R54 30 HDR 1X2 1 2 PGND Vpre J3 C14 10nF DNP PGND INTb C13 22uF Vpre [4] Vpre Q53 GND IO_5 [4] FS0b J39 2 1 FS_PU D55 BZT52H-B18 R26 5.1K GND 1 2 NX3008NBK J43 IO_5 0 PGND 0 R50 J5 R101 5.6K GND R107 DNP 0 0 3 2 1 R53 R106 VDDIO Vcore P3V3_KL25Z J5 - VDDIO Voltage Selection TXD_L[4] FS1b [3,4] VDDIO Vddio [4] 5.1K 0 10K C63 1000PF DNP GND VDDIO Vkam_IO5 GND 1.5K IO_0 IO_2 IO_4 R93 10K GND R3 [4] Vkam 2 4 6 8 10 GND LED/GRN C A NCSb [4] SCLK [4] MOSI [4] MISO [4] Vcore RSTb [4] GND RXD_L [4] Boost_core VSW_Core Vcore_sense Comp_core FB_core SELECT GND LIN Product : - R29 : Populated - R98 / R108 / C24 DNP - R69 : DNP - R17 : Populated FS1b Products : - R29 : DNP. - R98 / R108 / C24 : Populated - R69 : Populated - R17 : DNP J36 2 4 PGND C6 22uF PGND Buck only J2 1 3 SS24T3G C 3 Buck or Boost R2 A D3 PGND A D2 Jumpers off D1 LED/GRN A C 1 3 5 7 9 1 BUK9832-55A Q1 22UH 1-2 & 3-4 I/O R94 5.1K VDDIO GND C28 10nF 2 L1 J2-Vpre mode MUX_OUT [4] RXD [4] TXD [4] IO_3 [4] IO_2 [4] TXDL_VpuFS1b VDDIO Vbat D57 BZT52H-C20 R95 R37 GND IO_3 0 RXD TXD 49 36 35 34 33 32 31 30 29 28 27 26 25 0 MC33FS6522LAE BOOT_CORE SW_CORE VCORE_SNS COMP_CORE FB_CORE SELECT VDDIO INT CS SCLK MOSI MISO EP D6 SS24T3G R1 PGND DBG [4] R28 R81 11.0K GND C66 10nF GND D57 & C93 as close as possible to the IC J15 [4] FS0b VSUP1 VSUP2 VSENSE VSUP3 LIN GND_COM CAN_5V CANH CANL IO_4 IO_5/VKAM IO_0 U55 4 FCRBM 1 2 3 4 5 6 7 8 9 10 11 12 C92 10nF DNP GND C26 10nF DNP GND CANH CANL 5.1K Vsense Vsup3 Vsup12 J15-DEBUG MODE GND C91 0.47UF 5.1K CAN_5V VDDIO R103 10K PLUG_1X2 J21 3 1 DNP GND R75 Vkam_IO5 J12 J38 0 0 4 2 C59 10nF DNP PGND C55 10nF GND INGNITION Contact KEY 1;3 GND 5.1K Vsup3 [4] IO_0 [4] IO_4 R69 DNP PGND PGND R17 2 IO_0 0 CAN_5V CAN_5V [4] FS0_b GND R43 510K [3,4] FS1b GND 1 1 2 KEY 3 R111 Populated on product with LIN Option only C29 1000PF J26 R31 1.5K C R25 2K Vsup3 R40 5.0K GND S1 GND Vsense GND Vcore D12 1N4148WS 2 GND C57 1uF GND GND GND + FCRBM FB_Core RED D14 GND 3 2 1 Vcore = 5V R30 1.5K VDDIO 5.1K R16 Vcore = 3.3V PLUG_1X2 J23 J14 Vbat Vcore = 1.23V LIN 5 - 6 3 - 4 1 - 2 J31 VcoreFB Drift Vbat J8 2 1 MPZ1608S101A L3 1 GND 2 3 S2 SW2 GND J4 10nF C17 1 3 2 PMEG10030ELP C A D8 SW4 500SSP3S1M6QEA S2 4.7uF C16 C A VCCA VCCA_B VCCA_E VAUX_E VAUX_B VAUX 2 4 3 GND 10nF C11 DNP L4 PGND Comp_core 3 - 4 Comp. Network 2 GND Vpre PGND J42 DNP 1 3 5 7 9 11 13 15 17 19 J37 2 4 6 8 10 12 14 16 18 20 GND INTb TXD_L FS1b TXD JP1 PGND PGND GND J10 D20 RED GND R96 10K FS1b J40 BSS84LT1 Q4 2 1 D56 BZT52H-B18 1 2 R99 10K BSS84LT1 Q3 GND R97 510K D21 RED R100 5.6K TXDL_VpuFS1b C7 R57 39K VCCA_B J9 Vcca 1000PF 4 3 2 1 Vpre R56 18K C53 4.7uF Vcca SELECT GND 5 3.3 5 2-7 3-6 4-5 BH4 BH1 3.3 1-8 MTG1 5 3.3 5 GND GND BH3 MTG1 1 1 Date: Size C FB_Core GND 2.4 0 R66 R65 R64 R63 5.1K 12K 24K 51K IUO: TP19 TP23 TP18 TP15 TP27 TP28 TP29 TP30 TP26 TP21 TP25 TP24 X FS6500 Wednesday, April 06, 2016 1 Sheet 3 of PUBI: ___ SELECT FCRBM VSW_Core VSW_Pre INTb RSTb FS1b FS0b Vaux [4] 3 2 1 GND Vpre GND Vaux MUX_OUT LIN CANL CANH SCH-29225 PDF: SPF-29225 KITFS6522LAEEVM CP: ___ GND PGND GND GND Vsup3 GND Vaux PGND Vcore DFS Disabled Regulator DFS Enabled 1-2 Jumper 2-3 J1 4 A Rev J18 C56 4.7uF R52 15 R51 15 J18 DEEP FAIL SAFE mode select 8 7 6 5 R105 for Vaux = 5V R109 for Vaux = 3.3V R109 R105 PHPT60603PY Q51 Vaux 5 - 6 Vcore = 5.0V 3 - 4 Vcore = 3.3V 1 2 Vcore [4] HDR 1X2 R9 8.06K PGND J13 Vcore 1 - 2 Vcore = 1.23V J13 Vaux_B 4 SW5 1 C2 10uF PGND 1 2 Vaux_E J6 C1 10uF Document Number Page Title: ICAP Classification: Drawing Title: TP1 GND TP13 MTG1 TP14 GND TP17 TP16 TP6 DNP TP31 GND CAN_5V GND TP10 DNP TP7 TP22 BH2 PGND Vcca TP11 GND 1 1 1 Vpre TP12 TP4 DNP TP5 TP8 DNP TP9 TP2 DNP TP3 MTG1 Vaux 3.3 1 2 3 4 Vcca [4] Test Points Vcca SWITCH Vcca_E 0 PHPT60603PY Q50 C3 680PF R6 510 R8 SW5 Vcca/Vaux Voltages config. J11 2-3 1-2 J9 Ext PNP ON Jumper Int MOS OFF J11 150pF 1 3 2 4 C4 220PF R10 200 J7 J9 / J11 Vcca PNP Config. 2 C52 4 C5 22uF PGND FB_Core C9 10nF PGND 2.2uH 2 PLUG_1X10 1 2 3 4 5 6 7 8 9 10 C51 0.22uF RSTb VDDIO DEBUG J41 DNP Vcore Vaux Vcca CAN_5V C50 0.1UF 0 Product with Vcore DC/DC only GND 1 3 R7 DNP Product with Vcore LDO only D7 PMEG3030BEP 1 LED Signalling R102 510K 1 R12 15 C15 180PF Power Supply FS0_b MISO MOSI SCLK NCSb MUX_OUT RXD_L RXD DBG C19 0.1UF 2 1 - 2 Comp. Network 1 J7/J10 Boost_core VSW_Core Vcore C A 4.32K 24.9K 43K R15 R13 R58 2 4 6 1 3 5 Vbat Jack A C 47uF 10nF C54 DNP 3 1 4.7uF C12 1 2 C10 DNP 4.32K 24.9K 43K R32 R33 R60 2 4 6 1 2 3 3 2 1 1 2 1 2 A C C 1 2 48 47 46 45 44 43 42 41 40 39 38 37 A 1 3 5 A 3 C 2 3 2 1 5 SW_PRE1 SW_PRE2 BOOT_PRE DGND GATE_LS VCCA VCCA_B VCCA_E VAUX_E VAUX_B VAUX VPRE 1 2 C 1 2 3 5 FCRBM FS0 DEBUG AGND MUX_OUT IO_2 IO_3 TXD RXD TXDL RXDL RST 1 2 C A 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 2 2 3 A C 2 3 A C A 1 28 1 2 3 A B C D 6 1 5 Schematic Schematic Figure 23. Evaluation board schematic KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors A B C D [3] CAN_5V [3] Vcca [3] Vaux [3] Vcore [3] Vpre 2 !2 8 7 6 5 2 4 6 8 2 4 2 4 HDR_2X4 J24 SW DIP-4/SM SW6 J29 HDR 2X2 1 3 12 11 10 9 8 7 RSTb_SW FS0b_SW FS1b_SW DBG_SW IO_SW_2 IO_SW_3 IO_SW_4 IO_SW_5 RXD_L_SH TXD_L_SW RXD_SH TXD_MCU GND GND GND GND GND R78 11K R80 9.09k R85 11K R82 9.09k R88 11K R90 9.09k R86 11K R89 9.09k R84 6.49K R83 13.3K C65 0.1UF C73 0.1UF C77 0.1UF C78 0.1UF C72 0.1UF 5 2 3 13 12 9 10 6 5 2 3 GND 8 14 - + GND VEE MCP6004-I/SL U50A VCC 1 P3V3_KL25Z MCP6004-I/SL - + U53D MCP6004-I/SL - + U53C MCP6004-I/SL - + 7 VEE MCP6004-I/SL U53A VCC 1 U53B - + P3V3_KL25Z AN_IN_4 AN_IN_3 AN_IN_2 [3] Vkam VDDIO [3] MUX_OUT AN_IN_1 AN_IN_0 R71 9.09k C64 0.1UF GND C60 0.1UF GND1 8MHZ GND2 C61 0.1UF GND GND R77 11K R79 9.09k R72 11K R70 9.09k R73 11K 4 1 GNDGND C86 22PF Y50 R67 R62 R61 R59 R91 DNP IO_SW_4 IO_SW_3 IO_SW_2 IO_SW_0 13 12 9 10 6 5 TXD_L_SW IO_SW_5 R34 R68 10K 10K R21 10K GND 7 8 14 4 MCP6004-I/SL - + U50D MCP6004-I/SL - + U50C MCP6004-I/SL - + U50B C79 22PF GND D53 PDZ36B TP50 GPIO_3 D52 PDZ36B AN_IN_7 AN_IN_6 AN_IN_5 GND GND C23 1.0UF P3V3_KL25Z GND C76 1.0UF P3V3_KL25Z C80 0.1UF RST_KL25Z R87 10K P3V3_KL25Z GND DBG_SW GND GPIO_2 D51 PDZ36B GND GPIO_1 D50 PDZ36B GPIO_0 GND GNDGND 3 2 1.0M 10K 10K 10K 10K Digital IOs C62 0.1UF C30 0.1UF TP54 GND D9 PDZ36B 4 3 13 14 15 16 7 8 24 25 26 17 18 19 20 21 1 P3V3_KL25Z GND 2 TC_USB_ID_TP 4 330 OHM L5 USB_CONN_DP 3 GND C70 1.0UF GND MISO_SH [3,4] Vddio 3 C87 1.0UF TP55 33 TP56 P3V3_KL25Z GND 0 USB_DP USB_DM U52 4 1 6 GND C75 1.0UF P3V3_KL25Z B VCCA VCCB SN74LVC1T45 A GND DIR C71 0.1UF 3 2 5 P3V3_KL25Z C74 0.1UF MISO_MCU GND VREGIN C88 1.0UF RXD_SH RSTb_SW 14 11 9 7 FS0b_SW FS1b_SW 5 RXD_L_SH 3 6A 5A 4A 3A 2A 1 VCC 6Y 5Y 4Y 3Y 2Y 1Y 13 16 15 12 10 6 4 2 2 74HC4050D GND 8 NC_13 GND NC_16 U51 1A P3V3_KL25Z RXD_MCU GPIO_8 GPIO_7 GPIO_6 RXD_L_MCU GND 1.0UF C68 P3V3_KL25Z MKL25Z128VFT4 2 GND C85 1.0UF P5V_KL25Z P5V_KL25Z C82 1.0UF C67 0.1UF TXD_MCU 41 42 43 44 45 46 47 48 GND GND 2 4 6 8 10 IUO: HDR 2X5 J20 X 1 Sheet 4 SCH-29225 PDF: SPF-29225 Wednesday, April 06, 2016 INTERFACE Document Number Date: of PUBI: ___ RST_KL25Z SWD_DIO SWD_CLK D15 LED/GRN R35 560 P3V3_KL25Z 4 C81 0.1UF !!"# $% &$ ' ()*)# KITFS6522LAEEVM CP: ___ GND 1 3 5 7 9 P3V3_KL25Z Size C Page Title: C83 0.1UF 1 !/ TP57 C90 0.1UF ICAP Classification: Drawing Title: SCLK_MCU MOSI_MCU MISO_MCU RXD_MCU NCSb_MCU AN_IN_5 AN_IN_6 AN_IN_7 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 AN_IN_1 AN_IN_2 AN_IN_3 AN_IN_4 TP52 C84 1.0UF +*,-$% 330 OHM L50 33 34 35 36 37 38 39 40 31 32 27 28 29 30 6 TP33 PTB16/TSI0_CH9/SPI1_MOSI/UART0_RX/TPM_CLKIN0/SPI1_MISO PTB17/TSI0_CH10/SPI1_MISO/UART0_TX/TPM_CLKIN1/SPI1_MOSI HIGH_to_LOW Level Shifter 1 D19 1SMB5919BT3G P3V3_KL25Z GND 001+*, 00# TP51 C31 2.2UF C89 0.1UF R92 U1 GSOT05C-GS08 33 R38 GND 2 MFU0805FF00500P100 F50 R41 1 2 PTB0/LLWU_P5/ADC0_SE8/TSI0_CH0/I2C0_SCL/TPM1_CH0 PTB1/ADC0_SE9/TSI0_CH6/I2C0_SDA/TPM1_CH1 PTB2/ADC0_SE12/TSI0_CH7/I2C0_SCL/TPM2_CH0 PTB3/ADC0_SE13/TSI0_CH8/I2C0_SDA/TPM2_CH1 C32 0.1UF P3V3_KL25Z VREFH GND 1 PTC0/ADC0_SE14/TSI0_CH13/EXTRG_IN/CMP0_OUT PTC1/LLWU_P6/RTC_CLKIN/ADC0_SE15/TSI0_CH14/I2C1_SCL/TPM0_CH0 PTC2/ADC0_SE11/TSI0_CH15/I2C1_SDA/TPM0_CH1 PTC3/LLWU_P7/UART1_RX/TPM0_CH2/CLKOUT PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/TPM0_CH3 PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT PTC6/LLWU_P10/CMP0_IN0/SPI0_MOSI/EXTRG_IN/SPI0_MISO PTE29/CMP0_IN5/ADC0_SE4B/TPM0_CH2/TPM_CLKIN0 PTC7/CMP0_IN1/SPI0_MISO/SPI0_MOSI PTE30/DAC0_OUT/ADC0_SE23/CMP0_IN4/TPM0_CH3/TPM_CLKIN1 PTD0/SPI0_PCS0/TPM0_CH0 PTD1/ADC0_SE5B/SPI0_SCK/TPM0_CH1 PTD2/SPI0_MOSI/UART2_RX/TPM0_CH2/SPI0_MISO PTD3/SPI0_MISO/UART2_TX/TPM0_CH3/SPI0_MOSI USB0_DM PTD4/LLWU_P14/SPI1_PCS0/UART2_RX/TPM0_CH4 USB0_DP PTD5/ADC0_SE6B/SPI1_SCK/UART2_TX/TPM0_CH5 PTD6/LLWU_P15/ADC0_SE7B/SPI1_MOSI/UART0_RX/SPI1_MISO PTD7/SPI1_MISO/UART0_TX/SPI1_MOSI PTE24/TPM0_CH0/I2C0_SCL PTE25/TPM0_CH1/I2C0_SDA PTE20/ADC0_DP0/ADC0_SE0/TPM1_CH0/UART0_TX PTE21/ADC0_DM0/ADC0_SE4A/TPM1_CH1/UART0_RX PTA18/EXTAL0/UART1_RX/TPM_CLKIN0 PTA19/XTAL0/UART1_TX/TPM_CLKIN1/LPTMR0_ALT1 PTA20/RESET TP32 TP20 USB_CONN_DN 2 5 P5V0_USB_CONN_VBUS 1 GND J33 CONN USB MINI-B PTA0/SWD_CLK/TSI0_CH1/TPM0_CH5 PTA1/TSI0_CH2/UART0_RX/TPM2_CH0 PTA2/TSI0_CH3/UART0_TX/TPM2_CH1 PTA3/SWD_DIO/TSI0_CH4/I2C1_SCL/TPM0_CH0 PTA4/NMI/TSI0_CH5/I2C1_SDA/TPM0_CH1 U54 SHIELD_K20USB FAST HIGH_to_LOW Level Shifter [3,4] Vddio USB_DM USB_DP PTE29 AN_IN_0 GPIO_5 GPIO_6 TXD_L_MCU RXD_L_MCU SWD_CLK GPIO_7 GPIO_8 SWD_DIO GPIO_5 D16 PDZ36B TXD_L_MCU D54 PDZ36B GPIO_4 +*,-!. 3 2 4 3 IO_SW_0 MISO_SH MOSI_MCU SCLK_MCU NCSb_MCU SW_DIP-6_SM SW3 J34 HDR 2X2 1 3 1 3 5 7 1 2 3 4 1 2 3 4 5 6 Analog Inputs [3] RXD_L [3] TXD_L [3] RXD [3] TXD [3] MISO [3] MOSI [3] SCLK [3] NCSb [3] RSTb [3] FS0b [3] FS1b [3] DBG !2 [3] IO_2 [3] IO_3 [3] IO_4 [3] IO_5 A C A C A [3] IO_0 C C A C A C A C A C A S1 S3 5V DD+ ID G S2 S4 2 4 VDD1 VDD2 9 VDDA 11 VREFL 1 22 VSS1 VSS2 2 23 EX_PAD 49 11 4 11 VREFH 5 VOUT33 10 VSSA 12 A NXP Semiconductors C 5 A Rev A B C D Schematic Figure 24. Evaluation board schematic KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 29 Board layout 7 Board layout 7.1 Assembly layer top Figure 25. Assembly layer top KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 30 NXP Semiconductors Board layout 7.2 Assembly layer bottom Figure 26. Assembly layer bottom KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 31 Board bill of materials 8 Board bill of materials Bill of materials for KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM are available in the download section of the Tool Summary page at the following URLs: www.nxp.com/KITFS6522LAEEVM, www.nxp.com/KITFS6523CAEEVM, or www.nxp.com/KITFS4503CAEEVM. 9 Accessory item bill of materials Table 25. Accessory Bill of Materials (3) Item Qty Part number Description 1 1 10U2-03103BK USB cable A plug to USB mini B 2 1 1803659 10 ways PCB screw connector 3 3 1803578 2 ways PCB screw connector Notes 3. NXP does not assume liability, endorse, or warrant components from external manufacturers are referenced in circuit drawings or tables. While NXP offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 32 NXP Semiconductors References 10 References Table 26. References NXP.com Support Pages Description URL FS6500-FS4500 Data sheet TBD AN4661 Designing the VCORE Compensation Network http://www.nxp.com/AN4661.pdf AN4388 Quad Flat Package (QFP) http://www.nxp.com/files/AN4388.pdf Power dissipation tool (Excel file) TBD VCORE compensation network simulation board (CNC) upon demand Non ISO pulses report upon demand FMEDA FS6500/FS4500 FMEDA upon demand FS4500-FS6500SMUG FS4500-FS6500SMUG safety manual – User Guide TBD KITFS6522LAEEVM, KITFS6523CAEEVM, KITFS4503CAEEVM Tool Summary Page www.nxp.com/KITFS6522LAEEVM www.nxp.com/KITFS6523CAEEVM www.nxp.com/KITFS4503CAEEVM FS6500 Product summary page http://www.nxp.com/FS6500 FS4500 Product summary page http://www.nxp.com/FS4500 Analog home page http://www.nxp.com/analog 10.1 Support Visit www.nxp.com/support for a list of phone numbers within your region. 10.2 Warranty Visit www.nxp.com/warranty to submit a request for tool warranty. KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 NXP Semiconductors 33 Revision history 11 Revision history Revision Date 1.0 5/2016 Description of Changes • Initial release KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0 34 NXP Semiconductors How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There Home Page: NXP.com are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on Web Support: http://www.nxp.com/support NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, the information in this document. NXP reserves the right to make changes without further notice to any products herein. nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2016 NXP B.V. Document Number: KTFS4500-FS6500UG Rev. 1.0 5/2016