Philips Semiconductors FAST Products Product specification Arithmetic logic unit 74F181 FEATURES PIN CONFIGURATION • Provides 16 arithmetic operation: add, subtract, compare, and double; plus 12 other arithmetic operations B0 1 • Provides all 16 logic operations of two variables: Exclusive-OR, 24 VCC A0 2 23 A1 Compare, AND, NAND, NOR, OR, plus 10 other logic operations S3 3 22 B1 • Full look-ahead carry for high speed arithmetic operation on long S2 4 21 A2 S1 5 20 B2 words • 40% faster than ’S181 with only 30% ’S181 power consumption • Available in 300mil-wide Slim 24-pin Dual In-Line package S0 6 19 A3 Cn 7 18 B3 M 8 17 G DESCRIPTION F0 9 16 C n+4 The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0–S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on active-High or active-Low operands. The Function Table lists these operations. F1 10 15 P F2 11 14 A=B GND 12 13 F3 SF00193 TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F181 7.0ns 43mA ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 24-Pin Plastic Slim DIP (300 mil) N74F181N 24-Pin Plastic SOL N74F181D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0–A3 PINS A operand inputs 1.0/3.0 20µA/1.8mA B0–B3 B operand inputs 1.0/3.0 20µA/1.8mA Mode control input 1.0/1.0 20µA/0.6mA Function select input 1.0/4.0 20µA/2.4mA Carry input 1.0/5.0 20µA/3.0mA M S0–S3 Cn Cn+4 Carry output 50/33 1.0mA/20mA P Carry Propagate output 50/33 1.0mA/20mA G Carry Generate output 50/33 1.0mA/20mA Compare output OC/33 OC/20mA Outputs 50/33 1.0mA/20mA A=B F0–F3 NOTE: DESCRIPTION One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. OC = Open Collector March 3, 1989 1 853–0351 95947 Philips Semiconductors FAST Products Product specification Arithmetic logic unit 74F181 LOGIC SYMBOL IEC/IEEE SYMBOL Active-High Operands 2 1 6 23 22 21 20 19 18 ALU [T] 0 5 4 M 3 A0 B0 A1 B1 A2 B2 A3 B3 7 8 Cn 7 CI 16 M 6 S0 A=B 14 2 P0 5 S1 G 17 1 Q0 4 S2 P 15 23 P1 3 S3 22 Q1 21 P2 20 Q2 19 P3 18 Q3 F0 F1 F2 F3 9 10 11 13 CG CO 4 8 Cn+4 CP 0 21 P=G 15 17 16 14 9 10 11 13 SF00197 Active-Low Operands 2 1 23 22 21 20 19 18 A0 B0 A1 B1 A2 B2 A3 B3 7 Cn 8 M 6 S0 A=B 14 5 S1 G 17 4 S2 P 15 3 S3 Cn+4 16 F0 F1 F2 F3 VCC = Pin 24 GND = Pin 12 March 3, 1989 9 10 11 13 SF00196 2 Philips Semiconductors FAST Products Product specification Arithmetic logic unit 74F181 LOGIC DIAGRAM S0 S1 S2 S3 B3 6 5 4 3 18 17 16 A3 B2 A2 A1 B0 15 20 M Cn P 21 F3 22 23 11 F2 1 14 10 A0 Cn+4 19 13 B1 G A=B F1 2 8 9 F0 7 VCC = Pin 24 GND = Pin 12 March 3, 1989 SF00194 3 Philips Semiconductors FAST Products Product specification Arithmetic logic unit 74F181 when the unit is in the subtract mode. The A=B output is open-collector and can be wired-AND with other A=B outputs to give a comparison for more than 4 bits. The A=B signal can also be used with the Cn+4 signal to indicate A>B and A<B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus select code LHHL generates A minus B minus 1 (two’s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (one’s complement), a carry out means borrow; thus, a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active-Low inputs producing active-Low outputs or with active-High inputs producing active-High outputs. For either case, the table lists the operations that are performed to the operands labeled inside the logic symbol. When the Mode Control input (M) is High, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode control input is Low, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry look-ahead and provides for either ripple carry between device using the Cn+4 output, or for carry look-ahead between packages using the signals P (Carry Propagate) and G (Carry Generate). P and G are not affected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the next unit. For high-speed operation, the device is used in conjunction with the 74F182 carry look-ahead circuit. One carry look-ahead package is required for each group of four 74F181 devices. Carry look-ahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A=B output from the device goes High when all four F outputs are High and can be used to indicate logic equivalence over 4-bits MODE-SELECT FUNCTION TABLE MODE SELECT INPUTS S3 S2 L L L L L L L L H L L L Arithmetic** (M=L) (Cn=H) Logic (M=H) Arithmetic** (M=L) (Cn=L) L A A A A minus 1 H A+B A+B AB AB minus 1 L AB A+B A+B AB minus 1 H H Logical 0 minus 1 Logical 1 minus 1 H L L AB A plus AB A+B A plus (A+B) L H L H B (A+B) plus AB B AB plus (A+B) L H H L A⊕B A minus B minus 1 A⊕B A minus B minus 1 L H H H AB AB minus 1 A+B A+B H L L L A+B A plus AB AB A plus (A+B) H L L H A⊕B A plus B A⊕B A plus B H L H L B (A+B) plus AB B AB plus (A+B) H L H H AB AB minus 1 A+B A+B H H L L Logical 1 A plus A* Logical 0 A plus A* H H L H A+B (A+B) plus A AB AB plus A H H H L A+B (A+B) plus A AB AB plus A H H H A A minus 1 A A = = = = S0 ACTIVE LOW INPUTS & OUTPUTS Logic (M=H) H H L * ** S1 ACTIVE HIGH INPUTS & OUTPUTS High voltage level Low voltage level Each bit is shifted to the next more significant position. Arithmetic operations expressed in two’s complement notation. March 3, 1989 4 Philips Semiconductors FAST Products Product specification Arithmetic logic unit 74F181 Table 1. Sum Mode Test Function Inputs: S0 = S3 = 4.5V, S1 = S2 = M = 0V OTHER INPUT, SAME BIT OTHER DATA INPUTS PARAMETER INPUT UNDER TEST Apply 4.5V Apply GND Apply 4.5V Apply GND OUTPUT UNDER TEST tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL Ai Bi Ai Bi Ai Bi Ai Bi Cn Bi Ai Bi Ai None None None None None None None None None Bi Ai Bi Ai None Remaining A and B Remaining A and B None None Remaining B Remaining B Remaining B Remaining B All A Cn Cn Remaining A, B, Cn Remaining A, B, Cn Remaining A, Cn Remaining A, Cn Remaining A, Cn Remaining A, Cn All B Fi Fi P P G G Cn+4 Cn+4 Any F or Cn+4 Table 2. Diff Mode Test Function Inputs: S1 = S2 = 4.5V, S0 = S3 = M = 0V OTHER INPUT, SAME BIT OTHER DATA INPUTS PARAMETER INPUT UNDER TEST Apply 4.5V Apply GND Apply 4.5V Apply GND OUTPUT UNDER TEST tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL Ai Bi Ai Bi Ai Bi Ai Bi Ai Bi Cn None Ai None Ai Bi None None Ai Bi None None Bi None Bi None None Ai Bi None None Ai None Remaining A Remaining A None None None None Remaining A Remaining A None None All A and B Remaining B, Cn Remaining B, Cn Remaining A, B, Cn Remaining A, B, Cn Remaining A, B, Cn Remaining A, B, Cn Remaining B, Cn Remaining B, Cn Remaining A, B, Cn Remaining A, B, Cn None Fi Fi P P G G A=B A=B Cn+4 Cn+4 Any F or Cn+4 Table 3. Logic Mode Test Function Inputs: S1 = S2 = 4.5V, S0 = S3 = 0V OTHER INPUT, SAME BIT OTHER DATA INPUTS PARAMETER INPUT UNDER TEST Apply 4.5V Apply GND Apply 4.5V Apply GND OUTPUT UNDER TEST tPLH, tPHL tPLH, tPHL Ai Bi Bi Ai None None None None Remaining A, B, Cn Remaining A, B, Cn Fi Fi ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C March 3, 1989 5 Philips Semiconductors FAST Products Product specification Arithmetic logic unit 74F181 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA VOH High level output voltage A=B only 4.5 V IOH High-level output current Any output except A=B –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range +70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL LIMITS TEST CONDITIONS1 PARAMETER MIN IOH High-level output current A=B only VCC = MIN, VIL = MAX; VIH = MIN, VOH = MAX VOH High-level output voltage Any output except A=B VCC = MIN, VIL = MAX, VIH = MIN IOH = MAX VOL Low-level output voltage VCC = MIN, VIL = MAX, VIH = MIN IOL = MAX VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V TYP2 250 ±10%VCC 2.5 ±5%VCC 2.7 S0–S3 ±10%VCC 0.30 0.50 ±5%VCC 0.30 0.50 –0.73 –1.2 V 100 µA V VCC = MAX, VI = 0.5V Cn IOS Short-circuit output current3 Any output except A=B VCC = MAX –60 ICCH ICC Supply current (total) VCC = MAX ICCL µA V A0–A3, B0–B3 Low-level input current UNIT 3.4 M IIL MAX 20 µA –0.6 mA –1.8 mA –2.4 mA –3.0 mA –150 mA S0–S3=M=A0–A3=4.5V, B0–B3=Cn=GND 43 65 mA S0–S3=M=4.5V, B0–B3=Cn=A0–A3=GND 43 65 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. March 3, 1989 6 Philips Semiconductors FAST Products Product specification Arithmetic logic unit 74F181 AC ELECTRICAL CHARACTERISTICS LIMITS VCC = +5.0V Tamb = +25°C CL = 50pF RL = 500Ω TEST CONDITIONS SYMBOL PARAMETER VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF RL = 500Ω Mode Table Waveform Condition MIN TYP MAX MIN MAX UNIT tPLH tPHL Propagation delay Cn to Cn+4 Sum Diff 1 2 1 M=0V 3.0 2.5 5.0 5.0 8.0 8.0 3.0 2.5 8.5 8.5 ns tPLH tPHL Propagation delay An or Bn to Cn+4 Sum 1 2 M=S1=S2=0V, S0=S3=4.5V 5.0 5.0 9.0 8.0 12.0 12.0 5.0 5.0 13.0 12.5 ns tPLH tPHL Propagation delay An or Bn to Cn+4 Diff 2 2 M=S0=S3=0V, S1=S2=4.5V 5.0 5.0 9.5 8.0 13.0 12.0 5.0 5.0 14.0 12.5 ns tPLH tPHL Propagation delay Cn to Fn Diff Sum 2 1 1 M=0V 3.0 3.0 5.0 5.0 8.0 8.0 3.0 2.5 9.0 9.0 ns tPLH tPHL Propagation delay An or Bn to G Sum 1 1 M=S1=S2=0V, S0=S3=4.5V 3.0 3.0 5.0 5.0 7.5 7.5 2.5 2.5 8.0 8.0 ns tPLH tPHL Propagation delay An or Bn to G Diff 2 2 M=S0=S3=0V, S1=S2=4.5V 3.0 3.0 4.5 5.0 8.0 8.5 2.5 2.5 9.0 9.5 ns tPLH tPHL Propagation delay An or Bn to P Sum 1 2 M=S1=S2=0V, S0=S3=4.5V 2.5 3.0 4.0 4.5 7.0 7.5 2.0 2.5 7.5 8.0 ns tPLH tPHL Propagation delay An or Bn to P Diff 2 1, 2 M=S0=S3=0V, S1=S2=4.5V 2.5 3.0 4.0 5.0 7.5 8.5 2.0 2.5 8.0 9.0 ns tPLH tPHL Propagation delay Ai or Bi to Fi Sum 1 1, 2 M=S1=S2=0V, S0=S3=4.5V 3.0 3.0 4.5 4.5 7.5 7.5 2.5 3.0 8.5 8.5 ns tPLH tPHL Propagation delay Ai or Bi to Fi Diff 2 1, 2 M=S0=S3=0V, S1=S2=4.5V 3.0 3.0 4.5 5.0 8.5 8.5 2.5 3.0 9.0 9.0 ns tPLH tPHL Propagation delay An or Bn to Fn Sum 1, 2 3.5 3.5 6.0 5.5 10.0 9.5 3.0 3.0 11.0 10.0 ns tPLH tPHL Propagation delay An or Bn to Fn Diff 1, 2 4.0 4.5 6.5 7.0 10.5 10.5 3.5 4.5 11.0 11.0 ns tPLH tPHL Propagation delay Ai or Bi to Fi Logic 3 1, 2 M=4.5V 3.5 3.5 5.5 5.5 9.0 10.0 3.0 3.0 9.5 10.5 ns tPLH tPHL Propagation delay An or Bn to A=B Diff 2 1, 2 M=S0=S3=0V, S1=S2=4.5V 10.0 6.0 14.0 8.5 19.0 12.5 9.5 5.5 20.5 12.5 ns NOTES: “An or Bn to Fn” means any A or any B to any F; “Ai or Bi to Fi” means A1, B1 to F1; A2, B2 to F2 (the identifying number must be the same). March 3, 1989 7 Philips Semiconductors FAST Products Product specification Arithmetic logic unit 74F181 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Mode VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF RL = 500Ω VCC = +5.0V Tamb = +25°C CL = 50pF RL = 500Ω TEST CONDITIONS Waveform MIN TYP MAX MIN MAX UNIT tPLH tPHL Propagation delay Si to Fi (Inverting) 1 3.5 3.5 5.5 5.0 8.0 8.0 3.0 3.0 9.0 9.0 ns tPLH tPHL Propagation delay Si to Fi (Non-Inverting) 2 3.0 3.0 5.5 5.5 8.5 8.5 3.0 3.0 9.5 9.5 ns tPLH tPHL Propagation delay Si to A=B (Inverting) 1 10.5 6.0 16.5 8.0 22.5 11.0 10.5 6.0 24.0 11.5 ns tPLH tPHL Propagation delay Si to A=B (Non-Inverting) 2 10.0 5.5 15.0 8.5 19.0 12.5 10.0 5.0 21.0 13.5 ns tPLH tPHL Propagation delay Si to Cn+4 (Inverting) 1 3.5 3.0 7.0 5.5 11.0 10.0 3.0 2.5 12.5 10.0 ns tPLH tPHL Propagation delay Si to G (Non-Inverting) 2 2.5 2.5 5.0 4.0 7.5 7.5 2.5 2.5 8.0 8.0 ns tPLH tPHL Propagation delay Si to P (Non-Inverting) 2 2.5 2.5 4.0 4.5 6.5 7.0 2.5 2.5 7.0 8.0 ns tPLH tPHL Propagation delay M to Fi (Inverting) Sum 1 3.5 3.5 6.0 6.0 8.5 8.5 3.5 3.5 9.5 9.5 ns tPLH tPHL Propagation delay M to Fi (Non-Inverting) Sum 2 4.5 4.0 7.0 6.0 10.0 9.5 4.5 4.0 11.0 10.0 ns tPLH tPHL Propagation delay M to Fi (Inverting) Diff 1 3.5 3.5 6.0 6.0 8.5 8.5 3.5 3.5 9.5 9.5 ns tPLH tPHL Propagation delay M to Fi (Non-Inverting) Diff 2 4.0 4.0 7.0 6.0 10.0 9.5 4.0 4.0 11.5 10.0 ns tPLH tPHL Propagation delay M to A=B (Inverting) Sum 1 12.0 6.5 16.0 8.0 20.0 11.0 11.0 6.0 22.0 11.0 ns tPLH tPHL Propagation delay M to A=B (Non-Inverting) Sum 2 13.0 6.5 17.0 8.0 21.0 10.5 12.0 6.0 24.0 11.5 ns tPLH tPHL Propagation delay M to A=B (Inverting) Diff 1 11.5 6.0 16.0 8.0 20.0 10.5 10.5 6.0 22.0 11.0 ns tPLH tPHL Propagation delay M to A=B (Non-Inverting) Diff 2 13.0 6.0 17.0 8.0 21.5 11.0 12.5 6.0 24.0 11.5 ns AC WAVEFORMS For all waveforms, VM = 1.5V. VIN VM tPLH VOUT VIN VM VM tPHL VM tPHL VM VOUT VM tPLH VM SF00093 SF00092 Waveform 1. Propagation Delay for Non-Inverting Paths March 3, 1989 VM Waveform 2. Propagation Delay for Inverting Paths 8 Philips Semiconductors FAST Products Product specification Arithmetic logic unit 74F181 TEST CIRCUIT AND WAVEFORMS VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for Open Collector Outputs POSITIVE PULSE VM VM 10% TEST Open Collector All other SWITCH closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00195 March 3, 1989 9