54F/74F181 4-Bit Arithmetic Logic Unit General Description Features The ’F181 is a 4-bit Arithmetic logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations. It is 40% faster than the Schottky ALU and only consumes 30% as much power. Y Commercial Y Package Number Military 74F181PC N24A Full lookahead for high-speed arithmetic operation on long words Guaranteed 4000V minimum ESD protection Package Description 24-Lead (0.600× Wide) Molded Dual-In-Line N24C 24-Lead (0.300× Wide) Molded Dual-In-Line 54F181DM (Note 2) J24A 24-Lead Ceramic Dual-In-Line 54F181SDM (Note 2) J24F 24-Lead (0.300× ) Ceramic Dual-In-Line M24B 24-Lead (0.300× ) Molded Small Outline, JEDEC 54F181FM (Note 2) W24C 24-Lead Cerpack 54F181LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier,Type C 74F181SPC 74F181SC (Note 1) Note 1: Devices also available in 13× reel. Use suffix e SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9491 – 2 TL/F/9491 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9491 RRD-B30M105/Printed in U. S. A. 54F/74F181 4-Bit Arithmetic Logic Unit August 1995 Logic Symbols Active-HIGH Operands Active-LOW Operands TL/F/9491–3 IEEE/IEC TL/F/9491 – 4 Unit Loading/Fan Out 54F/74F Pin Names A 0 – A3 B 0 – B3 S0 – S3 M Cn F0 – F3 AeB G P Cn a 4 Description A Operand Inputs (Active LOW) B Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 1.0/3.0 1.0/3.0 1.0/4.0 1.0/1.0 1.0/5.0 50/33.3 OC*/33.3 50/33.3 50/33.3 50/33.3 TL/F/9491 – 10 20 mA/b1.8 mA 20 mA/b1.8 mA 20 mA/b2.4 mA 20 mA/b0.6 mA 20 mA/b3.0 mA b 1 mA/20 mA */20 mA b 1 mA/20 mA b 1 mA/20 mA b 1 mA/20 mA *OC-Open Collector Functional Description each group of four ’F181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A e B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode. The A e B output is open collector and can be wired AND with other A e B outputs to give a comparison for more than four bits. The A e B signal can also be used with the Cn a 4 signal to indicate AlB and AkB. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol. The ’F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0 – S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active LOW operands. The Function Table lists these operations. When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn a 4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). In the Add mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the Subtract mode P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed requirements are not stringent, the ’F181 can be used in a simple Ripple Carry mode by connecting the Carry output (Cn a 4) signal to the Carry input (Cn) of the next unit. For high speed operation the device is used in conjunction with a carry lookahead circuit. One carry lookahead package is required for 2 ’F181 Operation Table a. All Input Data Inverted b. All Input Data True c. A Input Data Inverted; B Input Data True d. A Input Data True; B Input Date Inverted S0 S1 S2 S3 Logic (M e H) Arithmetic (M e L, C0 e Inactive) Arithmetic (M e L, C0 e Active) L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H L L L L H H H H L L L L H H H H L L L L L L L L H H H H H H H H A A#B AaB Logic ‘‘1’’ AaB B AZB AaB A#B AZB B AaB Logic ‘‘0’’ A#B A#B A A minus 1 A # B minus 1 A # B minus 1 minus 1 (2s comp.) A plus (A a B) A # B plus (A a B) A minus B minus 1 AaB A plus (A a B) A plus B A # B plus (A a B) AaB A plus A (2 c A) A plus A # B A plus A # B A A A#B A#B Zero A plus (A a B) plus 1 A # B plus (A a B) plus 1 A minus B A a B plus 1 A plus (A a B plus 1 A plus B plus 1 A # B plus (A a B) plus 1 A a B plus 1 A plus A (2 c A) plus 1 A plus A # B plus 1 A plus A # B plus 1 A plus 1 L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H L L L L H H H H L L L L H H H H L L L L L L L L H H H H H H H H A AaB A#B Logic ‘‘0’’ A#B B AZB A#B AaB AZB B A#B Logic ‘‘1’’ AaB AaB A A AaB AaB minus 1 (2s comp.) A plus (A # B) A # B plus (A a B) A minus B minus 1 A # B minus 1 A plus A # B A plus B A # B plus (A a B) A # B minus 1 A plus A (2 c A) A plus (A a B) A plus (A a B) A minus 1 A plus 1 A a B plus 1 A a B plus 1 Zero A plus A # B plus 1 A # B plus (A a B) plus 1 A minus B A#B A plus A # B plus 1 A plus B plus 1 A # B plus (A a B) plus 1 A#B A plus A (2 c A) plus 1 A plus (A a B) plus 1 A plus (A a B) plus 1 A L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H L L L L H H H H L L L L H H H H L L L L L L L L H H H H H H H H A AaB A#B Logic ‘‘1’’ A#B B AZB AaB AaB AZB B AaB Logic ‘‘0’’ A#B A#B A A minus 1 A # B minus 1 A # B minus 1 minus 1 (2s comp.) A plus (A a B) A # B plus (A a B) A plus B AaB A plus (A a B) A minus B minus 1 A # B plus (A a B) AaB A plus A (2 c A) A plus A # B A plus A # B A A A#B A#B Zero A plus (A a B) plus 1 A # B plus (A a B) plus 1 A plus B plus 1 A a B plus 1 A plus (A a B) plus 1 A minus B A # B plus (A a B) plus 1 A a B plus 1 A plus A (2 c A) plus 1 A plus A # B plus 1 A plus A # B plus 1 A plus 1 L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H L L L L H H H H L L L L H H H H L L L L L L L L H H H H H H H H A A#B AaB Logic ‘‘0’’ AaB B AZB A#B A#B AZB B A#B Logic ‘‘1’’ AaB AaB A A AaB AaB minus 1 (2s comp.) A plus A # B A # B plus (A a B) A plus B A # B minus 1 A plus A # B A minus B minus 1 A # B plus (A a B) A # B minus 1 A plus A (2 c A) A plus (A a B) A plus (A a B) A minus 1 A plus 1 A a B plus 1 A a B plus 1 Zero A plus A # B plus 1 A # B plus (A a B) plus 1 A plus B plus 1 A#B A plus A # B plus 1 A minus B A # B plus (A a B) plus 1 A#B A plus A (2 c A) plus 1 A plus (A a B) plus 1 A plus (A a B) plus 1 A 3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. TL/F/9491 – 5 Logic Diagram 4 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Current Applied to Output in LOW State (Max) Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. b 55§ C to a 175§ C b 55§ C to a 150§ C VCC Pin Potential to Ground Pin 4000V Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions b 0.5V to a 7.0V Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATEÉ Output twice the rated IOL (mA) ESD Last Passing Voltage (Min) b 0.5V to a 7.0V Free Air Ambient Temperature Military Commercial b 30 mA to a 5.0 mA b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 0.5V to VCC b 0.5V to a 5.5V a 4.5V to a 5.5V a 4.5V to a 5.5V DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC IIH Input HIGH Current IBVI Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA 0.5 0.5 V Min IOL e 20 mA IOL e 20 mA 54F 74F 20.0 5.0 mA Max VIN e 2.7V Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC (Fn, G, P, Cn a 4) VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current 2.5 2.5 2.7 4.75 3.75 b 60 Recognized as a LOW Signal b 0.6 b 1.8 b 2.4 b 3.0 mA Max VIN VIN VIN VIN b 150 mA Max VOUT e 0V (Fn, G, P, Cn a 4) 250 mA Min VO e VCC (A e B) e e e e 0.5V (M) 0.5V (A0, A1, A3, B0, B1, B3) 0.5V (Sn, A2, B2) 0.5V (Cn) IOS Output Short-Circuit Current IOHC Open Collector, Output OFF Leakage Test ICCH Power Supply Current 43 65.0 mA Max VO e HIGH ICCL Power Supply Current 43 65.0 mA Max VO e LOW 5 AC Electrical Characteristics Symbol Parameter Path 54F 74F TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Units Min Typ Max Min Max Min Max 3.0 3.0 6.4 6.1 8.5 8.0 3.0 3.0 10.0 9.5 3.0 3.0 9.5 9.0 ns Sum 5.0 4.0 10.0 9.4 13.0 12.0 5.0 3.5 15.5 16.5 5.0 4.0 14.0 13.0 ns Propagation Delay A or B to Cn a 4 Dif 5.0 5.0 10.8 10.0 14.0 13.0 5.0 4.0 17.0 15.0 5.0 5.0 15.0 14.0 ns tPLH tPHL Propagation Delay Cn to F Any 3.0 3.0 6.7 6.5 8.5 8.5 2.5 2.5 16.0 12.0 3.0 3.0 9.5 9.5 ns tPLH tPHL Propagation Delay A or B or G Sum 3.0 3.0 5.7 5.8 7.5 7.5 2.5 2.5 9.0 9.5 3.0 3.0 8.5 8.5 ns tPLH tPHL Propagation Delay A or B to G Dif 3.0 3.0 6.5 7.3 8.5 9.5 2.5 2.5 11.5 11.0 3.0 3.0 9.5 10.5 ns tPLH tPHL Propagation Delay A or B to P Sum 3.0 3.0 5.0 5.5 7.0 7.5 2.5 3.0 8.5 9.5 3.0 3.0 8.0 8.5 ns tPLH tPHL Propagation Delay A or B to P Dif 3.0 4.0 5.8 6.5 7.5 8.5 2.5 3.0 11.0 11.0 3.0 4.0 8.5 9.5 ns tPLH tPHL Propagation Delay Ai or Bi to Fi Sum 3.0 3.0 7.0 7.2 9.0 10.0 3.0 3.0 14.5 14.5 3.0 3.0 10.0 10.0 ns tPLH tPHL Propagation Delay Ai or Bi to Fi Dif 3.0 3.0 8.2 5.0 11.0 11.0 3.0 3.0 17.5 14.5 3.0 3.0 12.0 12.0 ns tPLH tPHL Propagation Delay Any A or B to Any F Sum 4.0 4.0 8.0 7.8 10.5 10.0 3.5 4.0 16.5 13.5 4.0 4.0 11.5 11.0 ns tPLH tPHL Propagation Delay Any A or B to Any F Dif 4.5 3.5 9.4 9.4 12.0 12.0 3.5 3.0 17.5 14.0 4.5 3.5 13.0 13.0 ns tPLH tPHL Propagation Delay A or B to F Logic 4.0 4.0 6.0 6.0 9.0 10.0 3.5 3.0 14.5 15.5 4.0 4.0 10.0 11.0 ns tPLH tPHL Propagation Delay A or B to A e B Dif 11.0 6.0 18.5 9.8 27.0 12.5 8.0 5.5 35.0 21.0 11.0 6.0 29.0 13.5 ns tPLH tPHL Propagation Delay Cn to Cn a 4 tPLH tPHL Propagation Delay A or B to Cn a 4 tPLH tPHL Mode 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 181 P Temperature Range Family 74F e Commercial 54F e Military C Special Variations QB e Military grade device with environmental and burn-in processing Device Type Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Package Code P e Plastic DIP SP e Slim Plastic DIP D e Ceramic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC 6 Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Ceramic Dual-In-Line Package (D) NS Package Number J24A 7 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.300× Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 24-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M24B 8 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.600× Wide) Molded Dual-In-Line Package (P) NS Package Number N24A 24-Lead (0.300× Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C 9 54F/74F181 4-Bit Arithmetic Logic Unit Physical Dimensions inches (millimeters) (Continued) 24-Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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