SEMICONDUCTOR TECHNICAL DATA The MC14581B is a CMOS 4–bit ALU capable of providing 16 functions of two Boolean variables and 16 binary arithmetic operations on two 14–bit words. The level of the mode control input determines whether the output function is logic or arithmetic. The desired logic function is selected by applying the appropriate binary word to the select inputs (S0 thru S3) with the mode control input high, while the desired arithmetic operation is selected by applying a low voltage to the mode control input, the required level to carry in, and the appropriate word to the select inputs. The word inputs and function outputs can be operated with either active high or active low data. Carry propagate (P) and carry generate (G) outputs are provided to allow a full look–ahead carry scheme for fast simultaneous carry generation for the four bits in the package. Fast arithmetic operations on long words are obtainable by using the MC14582B as a second order look ahead block. An inverted ripple carry input (Cn) and a ripple carry output (Cn+4) are included for ripple through operation. When the device is in the subtract mode (LHHL), comparison of two 4–bit words present at the A and B inputs is provided using the A = B output. It assumes a high–level state when indicating equality. Also, when the ALU is in the subtract mode the Cn+4 output can be used to indicate relative magnitude as shown in this table: P SUFFIX PLASTIC CASE 709 DW SUFFIX SOIC CASE 751E ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. PIN ASSIGNMENT Data Level Cn Cn+4 Magnitude H L H L H H L L A B A<B A>B A B L H L H L L H H Active High Active Low • • • • • L SUFFIX CERAMIC CASE 623 v B0 1 24 VDD A0 2 23 A1 w AvB S3 3 22 B1 A<B A>B A B w Functional and Pinout Equivalent to 74181. Diode Protection on All Inputs All Outputs Buffered Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ S2 4 21 A2 S1 5 20 B2 S0 6 19 A3 Cn 7 18 B3 MC 8 17 G F0 9 16 Cn+4 F1 10 15 P F2 11 14 A=B VSS 12 13 F3 MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C 260 _C TL Lead Temperature (8–Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14581B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 1.2 – 0.64 – 1.6 – 4.2 — — — — – 1.0 – 0.51 – 1.3 – 3.4 – 1.7 – 0.88 – 2.25 – 8.8 — — — — – 0.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc IT 5.0 10 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (1.8 µA/kHz) f + IDD IT = (3.7 µA/kHz) f + IDD IT = (5.5 µA/kHz) f + IDD µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.008. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MC14581B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Sum in to Sum Out tPLH, tPHL = (1.7 ns/pF) CL + 620 ns tPLH, tPHL = (0.66 ns/pF) CL + 217 ns tPLH, tPHL = (0.5 ns/pF) CL + 155 ns tPLH, tPHL Sum in to Sum Out (Logic Mode) tPLH, tPHL = (1.7 ns/pF) CL + 520 ns tPLH, tPHL = (0.66 ns/pF) CL + 182 ns tPLH, tPHL = (0.5 ns/pF) CL + 155 ns tPLH, tPHL Sum in to A = B tPLH, tPHL = (1.7 ns/pF) CL + 870 ns tPLH, tPHL = (0.66 ns/pF) CL + 297 ns tPLH, tPHL = (0.5 ns/pF) CL + 220 ns tPLH, tPHL Sum in to P or G tPLH, tPHL = (1.7 ns/pF) CL + 400 ns tPLH, tPHL = (0.66 ns/pF) CL + 147 ns tPLH, tPHL = (0.5 ns/pF) CL + 105 ns tPLH, tPHL Sum in to Cn+4 tPLH, tPHL = (1.7 ns/pF) CL + 530 ns tPLH, tPHL = (0.66 ns/pF) CL + 187 ns tPLH, tPHL = (0.5 ns/pF) CL + 135 ns tPLH Carry in to Sum Out tPLH, tPHL = (1.7 ns/pF) CL + 295 ns tPLH, tPHL = (0.66 ns/pF) CL + 112 ns tPLH, tPHL = (0.5 ns/pF) CL + 80 ns tPLH, tPHL Carry in to Cn+4 tPLH, tPHL = (1.7 ns/pF) CL + 220 ns tPLH, tPHL = (0.66 ns/pF) CL + 87 ns tPLH, tPHL = (0.5 ns/pF) CL + 60 ns tPLH, tPHL VDD Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 Unit ns ns 5.0 10 15 — — — 705 250 180 1410 500 360 5.0 10 15 — — — 605 215 180 1210 430 360 5.0 10 15 — — — 955 330 245 1910 660 490 5.0 10 15 — — — 485 180 130 970 360 260 5.0 10 15 — — — 615 220 160 1230 440 360 5.0 10 15 — — — 380 145 105 760 290 210 5.0 10 15 — — — 305 120 85 610 240 170 ns ns ns ns ns ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. AC TEST SETUP REFERENCE TABLE AC Paths DC Data Inputs Test Inputs Outputs To VSS To VDD Mode Fig. 3 Waveform Sumin to Sumout Delay Time A0 Any F Remaining A’s Cn All B’s Add #1 Sumin to P Delay Time A0 P Remaining A’s Cn All B’s Add #1 Sumin to G Delay Time B0 G All A’s Cn Remaining B’s Add #1 Sumin to Cn+4 Delay Time B0 Cn+y All A’s Cn Remaining B’s Add #2 Cn to Sumout Delay Time Cn Any F All A’s All B’s Add #1 Cn to Cn+4 Delay Time Cn Cn+4 All A’s All B’s Add #1 Sumin to A = B Delay Time A0 A=B All B’s Remaining A’s Cn Sub #2 Sumin to Sumout Delay Time (Logic Mode) B0 Any F All A’s M Exclusive OR #2 MOTOROLA CMOS LOGIC DATA MC14581B 3 Vout = VOH VDD S0 S1 S2 S3 A0 A1 A2 A3 B0 B1 B2 B3 Cn MC VDD HIGH FOR ALL OUTPUTS EXCEPT Cn+4 S0 S1 S2 S3 F0 IOH F2 F3 A=B Cn+4 G P EXTERNAL POWER SUPPLY HIGH FOR ALL OUTPUTS EXCEPT Cn+4 Figure 1. Typical Source Current Test Circuit 50 pF TPin S0 S1 S2 S3 F0 A0 F1 A1 A2 F2 A3 F3 B0 B1 A=B B2 Cn+4 B3 G Cn P MC SEE AC TEST SETUP REFERENCE TABLE FOR CONNECTIONS F0 F1 IOH F2 F3 A=B Cn+4 G P EXTERNAL POWER SUPPLY VSS Figure 2. Typical Sink Current Test Circuit LOAD A TP out VDD PULSE GENERATOR A0 A1 A2 A3 B0 B1 B2 B3 Cn MC VDD F1 VSS Vout = VOH VDD 20 ns 20 ns VDD 90% TPin 10% tPHL tTLH LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A 0V VOH #1 TPout 10% VOL tPLH tTHL tTHL 90% #2 TPout tPHL VOH 10% VOL tTLH tPLH Figure 3. Switching Time Test Circuit and Waveforms VDD LOAD A S0 S1 S2 S3 TPin PULSE GENERATOR DUTY CYCLE = 50% A0 A1 A2 A3 B0 B1 B2 B3 Cn MC TPout 50 pF F0 F1 F2 LOAD A F3 LOAD A A=B LOAD A Cn+4 G LOAD A LOAD A LOAD A P LOAD A LOAD A 20 ns TPin 90% 50% 20 ns VDD 10% 0V VARIABLE WIDTH Figure 4. Dynamic Power Dissipation Test Circuit and Waveform MC14581B 4 MOTOROLA CMOS LOGIC DATA BLOCK DIAGRAM (ACTIVE LOW) FUNCTION SELECT INPUTS WORD A WORD B BLOCK DIAGRAM (ACTIVE HIGH) 3 4 5 6 3 4 5 6 VDD = PIN 24 VSS = PIN 12 S0 S1 S2 S3 A0 F0 A1 F1 A2 F2 A3 F3 B0 B1 A=B B2 Cn+4 B3 G Cn P MC 2 23 21 19 1 22 20 18 CARRY IN 7 MODE CONTROL 8 9 10 11 13 S0 S1 S2 S3 A0 F0 A1 F1 A2 F2 A3 F3 B0 B1 A=B B2 Cn+4 B3 G Cn P MC 2 23 OUTPUT FUNCTION 21 19 1 22 14 COMPARISON OUTPUT 20 18 16 RIPPLE CARRY OUTPUT 17 LOOK AHEAD 15 CARRY OUTPUTS 7 8 9 10 11 13 14 16 17 15 TRUTH TABLE Function Select Inputs/Outputs Active Low Logic Function (MC = H) Arithmetic* Function (MC = L, Cn = L) Inputs/Outputs Active High Logic Function (MC = H) Arithmetic* Function (MC = L, Cn = H) S3 S2 S1 S0 L L L L L L L H A AB A minus 1 AB minus 1 A A+B A A+B L L H L A+B AB minus 1 AB A+B L L H H Logic “1” minus 1 Logic “0” minus 1 L H L L A+B A plus (A + B) AB A plus AB L H L H B AB plus (A + B) B (A + B) plus AB L H H L A A minus B minus 1 A L H H H A+B A+B AB AB minus 1 H L L L AB A plus (A + B) A+B A plus AB H L L H A A plus B A A plus B H L H L B AB plus (A + B) B (A + B) plus AB H L H H A+B A+B AB AB minus 1 H H L L Logic “0” A plus A Logic “1” A plus A H H L H AB AB plus A A+B (A + B) plus A H H H L AB AB plus A A+B (A + B) plus A H H H H A A A A minus 1 ęB ęB ęB ęB A minus B minus 1 * Expressed as two’s complements. For arithmetic function with C n in the opposite state, the resulting function is as shown plus 1. MOTOROLA CMOS LOGIC DATA MC14581B 5 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 623–05 ISSUE M 24 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). 13 B 1 12 DIM A B C D F G J K L M N A F SEATING PLANE C L N D G INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050 J M K MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 P SUFFIX PLASTIC DIP PACKAGE CASE 709–02 ISSUE C 24 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 13 B 1 12 A L C N K H F G MC14581B 6 D SEATING PLANE M J DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E–04 ISSUE E –A– 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 –B– 12X P 0.010 (0.25) 1 M B M 12 24X D J 0.010 (0.25) M T A S B S F R C –T– SEATING PLANE M 22X G K X 45 _ DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14581B/D* MC14581B MC14581B/D 7