MM54HC181/MM74HC181 Arithmetic Logic Units/Function Generators General Description These arithmetic logic units (ALU)/function generators utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads. The MM54HC181/MM74HC181 are arithmetic logic unit (ALU)/function generators that have a complexity of 75 equivalent gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown in Tables 1 and 2. These operations are selected by the four function-select lines (S0, S1, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme is made available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (pins 15 and 17) for the four bits in the package. When used in conjunction with the MM54HC182 or MM74HC182, full carry lookahead circuits, high-speed arithmetic operations can be performed. The method of cascading HC182 circuits with these ALU’s to provide multi-level full carry look-ahead is illustrated under typical applications data for the MM54HC182/ MM74HC182. If high speed is not of importance, a ripple-carry input (Cn) and a ripple-carry output (Cn a 4) are available. However, the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be performed without external circuitry. Connection Diagram Pin Designations Dual-In-Line Package TL/F/5320 – 1 Top View Features Y Y Y Y Y Y Full look-ahead for high-speed operations on long words Arithmetic operating modes: Addition Subtraction Shift operand a one position magnitude comparison Plus twelve other arithmetic operations Logic function modes: Exclusive-OR Comparator AND, NAND, OR, NOR Plus ten other logic operations Wide operating voltage range: 2V – 6V Low input current: 1 mA maximum Low quiescent current: 80 mA maximum Designation Pin Nos. Function A3, A2, A1, A0 19, 21, 23, 2 Word A Inputs B3, B2, B1, B0 18, 20, 22, 1 Word B Inputs S3, S2, S1, S0 3, 4, 5, 6 Function-Select Inputs Cn 7 Inv. Carry Input M 8 Mode Control Input F3, F2, F1, F0 13, 11, 10, 9 Function Outputs AeB 14 Comparator Outputs P 15 Carry Propagate Output Cn a 4 16 Inv. Carry Output G 17 Carry Generate Output VCC 24 Supply Voltage GND 12 Ground Order Number MM54HC181 or MM74HC181 C1995 National Semiconductor Corporation TL/F/5320 RRD-B30M105/Printed in U. S. A. MM54HC181/MM74HC181 Arithmetic Logic Units/Function Generators January 1988 General Description (Continued) but also to provide 16 possible functions of two Boolean variables without the use of external circuitry. These logic functions are selected by use of the four function-select inputs (S0, S1, S2, S3) with the mode-control input (M) at a high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusiveOR, NAND, AND, NOR, and OR functions. These circuits will accommodate active-high or active-low data, if the pin designations are interpreted as shown below. Subtraction is accomplished by 1’s complement addition where the 1’s complement of the subtrahend is generated internally. The resultant output is AÐBÐ1, which requires an end-around or forced carry to produce AÐB. The 181 can also be utilized as a comparator. The A e B output is internally decoded from the function outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume a high level to indicate equality (A e B). The ALU should be in the subtract mode with Cn e H when performing this comparison. The A e B output is open-drain so that it can be wire-AND connected to give a comparison for more than four bits. The carry output (Cn a 4) can also be used to supply relative magnitude information. Again, the ALU should be placed in the subtract mode by placing the function select inputs S3, S2, S1, S0 at L, H, H, L, respectively. These circuits have been designed to not only incorporate all of the designer’s requirements for arithmetic operations, 1 23 22 21 ALU SIGNAL DESIGNATIONS The MM54HC181/MM74HC181 can be used with the signal designations of either Figure 1 or Figure 2 . The logic functions and arithmetic operations obtained with signal designations as in Figure 1 are given in Table 1; those obtained with the signal designations of Figure 2 are given in Table 2. The 54HC/74HC logic family is speed, function, and pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Pin Number 2 20 19 18 9 10 11 Active-High Data (Table 1) A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 Active-Low Data (Table 1) A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 Input Cn Output Cn a 4 Active-High Data (Figure 1) Active-Low Data (Figure 2) H H L L H L H L AsB AlB AkB AtB AtB AkB AlB AsB 13 7 16 15 17 F3 Cn Cn a 4 X Y F3 Cn Cn a 4 P G Table I Active High Data Selection MeH Logic S3 S2 S1 S0 Functions TL/F/5320–2 FIGURE 1 L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H FeA FeA a B F e AB Fe0 F e AB FeB FeA Z B F e AB FeA a B FeA Z B FeB F e AB Fe1 FeA a B FeA a B FeA M e L; Arithmetic Operations Cn e H (no carry) Cn e L (with carry) FeA FeA a B FeA a B F e Minus 1 (2’s Compl) F e A Plus AB F e (A a B) Plus AB F e A Minus B Minus 1 F e AB Minus 1 F e A Plus AB F e A Plus B F e (A a B) Plus AB F e AB Minus 1 F e A Plus A* F e (A a B) Plus A F e (A a B) Plus A F e A Minus 1 F e A Plus 1 F e (A a B) Plus 1 F e (A a B) Plus 1 F e Zero F e A Plus AB Plus 1 F e (A a B) Plus AB Plus 1 F e A Minus B F e AB F e A Plus AB Plus 1 F e A Plus B Plus 1 F e (A a B) Plus AB Plus 1 F e AB F e A Plus A Plus 1 F e (A a B) Plus A Plus 1 F e (A a B) Plus A Plus 1 FeA *Each bit is shifted to the next more significant position. 2 General Description (Continued) TL/F/5320 – 3 FIGURE 2 Table II Active Low Data Selection S3 S2 S1 S0 MeH Logic Functions L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H FeA F e AB FeA a Fe1 FeA a FeB FeA a FeA a F e AB FeA a FeB FeA a Fe0 F e AB F e AB FeA B B B B B B M e L; Arithmetic Operations Cn e L (no carry) Cn e H (with carry) F e A Minus 1 F e AB Minus 1 F e AB Minus 1 F e Minus 1 (2’s Compl) F e A Plus (A a B) F e AB Plus (A a B) F e A Minus B Minus 1 FeA a B F e A Plus (A a B) F e A Plus B F e AB Plus (A a B) FeA a B F e A Plus A* F e AB Plus A F e AB Plus A FeA FeA F e AB F e (AB) F e Zero F e A Plus (A a B) Plus 1 F e AB Plus (A a B) Plus 1 F e A Minus B F e (A a B Plus 1 F e A Plus (A a B) Plus 1 F e A Plus B Plus 1 F e AB Plus (A a B) Plus 1 F e (A a B) Plus 1 F e A Plus A Plus 1 F e AB Plus A Plus 1 F e AB Plus A Plus 1 F e A Plus 1 *Each bit is shifted to the next more significant position. Number of Bits Typical Addition Times 1 to 4 5 to 8 9 to 16 17 to 64 20 ns 30 ns 30 ns 50 ns Package Count Arithmetic/ Logic Units Look Ahead Carry Generators 1 2 3 or 4 5 to 16 0 0 1 2 to 5 3 Carry Method Between ALU’s None Ripple Full Look-Ahead Full Look-Ahead Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V b 1.5 to VCC a 1.5V Operating Temp. Range (TA) MM74HC MM54HC b 0.5 to VCC a 0.5V g 20 mA Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V g 25 mA g 50 mA b 65§ C to a 150§ C 600 mW 500 mW (Soldering 10 seconds) 260§ C DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC TA e 25§ C 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage (any output except A e B) VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA ILKG Maximum Leakage Open Drain Output Current (A e B Output) VIN e VIH or VIL VOUT e VCC VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 0.5 5.0 10 mA 6.0V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. ** VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 4 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Typ Guaranteed Limit Units 13 20 ns M e 0V, S0 e S3 e VCC S1 e S0 e 0V (Sum mode) 30 45 ns Maximum Propagation Delay from any A or B to CN a 4 M e 0V, S0 e S3 e 0V S1 e S2 e VCC (Diff. mode) 30 45 ns tPHL, tPLH Maximum Propagation Delay from Cn to any F M e 0V (Sum or Diff. mode) 20 30 ns tPHL, tPLH Maximum Propagation Delay from any A or B to G M e 0V, S0 e S3 e VCC S1 e S2 e 0V (Sum mode) 20 30 ns tPHL, tPLH Maximum Propagation Delay from any A or B to G M e 0V, S0 e S3 e 0V S1 e S2 e VCC (Diff mode) 20 30 ns tPHL, tPLH Maximum Propagation Delay from any A or B to P M e 0V, S0 e S3 e VCC S1 e S2 e 0V (Sum mode) 27 41 ns tPHL, tPLH Maximum Propagation Delay from any A or B to P M e 0V, S0 e S3 e 0V S1 e S2 e VCC (Diff mode) 24 37 ns tPHL, tPLH Maximum Propagation Delay from AI or BI to FI M e 0V, S0 e S3 e VCC S1 e S2 e 0V (Sum mode) 20 30 ns tPHL, tPLH Maximum Propagation Delay from AI or BI to FI M e 0V, S0 e S3 e 0V S1 e S2 e VCC (Diff mode) 19 29 ns tPHL, tPLH Maximum Propagation Delay from AI or BI to FI M e VCC (Logic mode) 25 37 ns tPHL, tPLH Maximum Propagation Delay from any A or B to A e B M e 0V, S0 e S3 e 0V S1 e S2 e VCC (Diff mode) 25 37 ns Symbol Parameter tPHL, tPLH Maximum Propagation Delay from Cn to Cn a 4 tPHL, tPLH Maximum Propagation Delay from any A or B to CN a 4 tPHL, tPLH Conditions 5 AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions TA e 25§ C VCC Typ tPHL, tPLH Maximum Propagation Delay from Cn to Cn a 4 2.0V 4.5V 6.0V tPHL, tPLH Maximum Propagation Delay from any A or B to Cn a 4 M e 0V, S0 e S3 e VCC S1 e S2 e 0V (Sum mode) 2.0V 4.5V 6.0V tPHL, tPLH Maximum Propagation Delay from any A or B to Cn a 4 M e 0V, S0 e S3 e 0V S1 e S2 e VCC (Diff mode) 2.0V 4.5V 6.0V tPHL, tPLH Maximum Propagation Delay from Cn to any F M e 0V (Sum or Diff mode) 2.0V 4.5V 6.0V tPHL, tPLH Maximum Propagation Delay from any A or B to G M e 0V, S0 e S3 e VCC, S1 e S2 e 0V (Sum mode) tPHL, tPLH Maximum Propagation Delay from any A or B to G tPHL, tPLH 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits 125 25 22 155 31 28 190 38 33 ns ns ns 250 50 43 325 63 53 375 75 65 ns ns ns 250 50 43 325 63 53 375 75 65 ns ns ns 65 22 14 150 32 28 190 40 35 225 48 42 ns ns ns 2.0V 4.5V 6.0V 70 20 12 175 35 30 220 44 38 263 53 45 ns ns ns M e 0V, S0 e S3 e 0V S1 e S2 (Diff mode) 2.0V 4.5V 6.0V 65 23 16 165 33 29 210 42 37 250 50 44 ns ns ns Maximum Propagation Delay from any A or B to P M e 0V, S0 e S3 e VCC S1 e S2 e 0V (Sum mode) 2.0V 4.5V 6.0V 80 30 25 220 44 37 275 55 47 330 66 56 ns ns ns tPHL, tPLH Maximum Propagation Delay from any A or B to P M e 0V, S0 e S3 e 0V S1 e S2 e VCC (Diff mode) 2.0V 4.5V 6.0V 75 27 24 195 39 34 244 49 43 293 60 51 ns ns ns tPHL, tPLH Maximum Propagation Delay from AI or BI to FI M e 0V, S0 e S3 e VCC S1 e S2 e 0V (Sum mode) 2.0V 4.5V 6.0V 70 26 21 180 36 31 225 45 39 270 54 47 ns ns ns tPHL, tPLH Maximum Propagation Delay from AI or BI to FI M e 0V, S0 e S3 e 0V S1 e S2 e VCC (Diff mode) 2.0V 4.5V 6.0V 160 32 27 200 40 34 290 48 41 ns ns ns tPHL, tPLH Maximum Propagation Delay from AI or BI to FI M e VCC (Logic mode) 2.0V 4.5V 6.0V 180 30 23 200 40 34 250 50 43 300 60 51 ns ns ns tPHL, tPLH Maximum Propagation Delay from any A or B to A e B M e 0V, S0 e S3 e 0V S1 e S2 e VCC (Diff mode) 2.0V 4.5V 6.0V 180 30 23 200 40 34 250 50 43 300 60 51 ns ns ns tTLH, tTHL Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V 30 8 7 75 15 13 95 19 16 110 22 19 ns ns ns CPD Power Dissipation Capacitance (Note 5) CIN Maximum Input Capacitance 110 35 30 300 5 pF 15 15 15 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 6 Parameter Measurement Information Logic Mode Test Table Parameter Input Under Test tPHL, tPLH tPHL, tPLH Function Inputs: S1 e S2 e M e VCC, S0 e S3 e 0 V Other Input Same Bit Other Data Inputs Output Under Test Output Waveform Remaining A and B, Cn FI Out-of-Phase Remaining A and B, Cn FI Out-of-Phase Apply VCC Apply GND Apply VCC Apply GND AI BI None None BI AI None None SUM Mode Test Table Parameter Input Under Test tPHL, tPLH tPHL, tPLH Function Inputs: S0 e S3 e VCC S1 e S2 e M e 0 V Other Input Same Bit Other Data Inputs Apply VCC Apply GND Apply VCC Apply GND Output Under Test Output Waveform AI BI None Remaining A and B Cn FI In-Phase BI AI None Remaining A and B Cn FI In-Phase P In-Phase tPHL, tPLH AI BI None None Remaining A and B, Cn tPHL, tPLH BI AI None None Remaining A and B, Cn P In-Phase tPHL, tPLH AI None BI Remaining B Remaining A, Cn G In-Phase tPHL, tPLH BI None AI Remaining B Remaining A, Cn G In-Phase All B Any F or Cn a 4 In-Phase tPHL, tPLH Cn None None All A tPHL, tPLH AI None BI Remaining B Remaining A, Cn Cn a 4 Out-of-Phase tPHL, tPLH BI None AI Remaining B Remaining A, Cn Cn a 4 Out-of-Phase Output Under Test Output Waveform Diff Mode Test Table Parameter Input Under Test tPHL, tPLH AI Function Inputs: S1 e S2 e VCC, S0 e S3 e M e 0 V Other Input Same Bit Other Data Inputs Apply VCC Apply GND Apply VCC Apply GND None BI Remaining A Remaining B, Cn FI In-Phase Remaining B, Cn FI Out-of-Phase tPHL, tPLH BI AI None Remaining A tPHL, tPLH AI None BI None Remaining A and B, Cn P In-Phase tPHL, tPLH BI AI None None Remaining A and B, Cn P Out-of-Phase tPHL, tPLH AI BI None None Remaining A and B, Cn G In-Phase G Out-of-Phase tPHL, tPLH BI None AI None Remaining A and B, Cn tPHL, tPLH AI None BI Remaining A Remaining B, Cn AeB In-Phase tPHL, tPLH BI AI None Remaining A Remaining B, Cn AeB Out-of-Phase All A and B None Cn a 4 In-Phase Cn a 4 Out-of-Phase Cn a 4 In-Phase tPHL, tPLH Cn None None tPHL, tPLH AI BI None None Remaining A, B, Cn tPHL, tPLH BI None AI None Remaining A, B, Cn 7 or any F Logic Diagram VCC e PIN 24 GND e PIN 12 TL/F/5320 – 4 8 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54HC181J or MM74HC181J NS Package Number J24F 9 MM54HC181/MM74HC181 Arithmetic Logic Units/Function Generators Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM74HC181N NS Package Number N24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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