TI LMR62421XSDX

LMR62421
LMR62421 SIMPLE SWITCHER ® 24Vout, 2.1A Step-Up Voltage Regulator in
SOT-23
Literature Number: SNVS734A
LMR62421
SIMPLE SWITCHER® 24Vout, 2.1A Step-Up Voltage
Regulator in SOT-23
Features
Performance Benefits
■
■
■
■
■
■
■
■
■
■ Extremely easy to use
■ Tiny overall solution reduces system cost
Input voltage range of 2.7V to 5.5V
Output voltage up to 24V
Switch current up to 2.1A
1.6 MHz switching frequency
Low shutdown Iq, 80 nA
Cycle-by-cycle current limiting
Internally compensated
Internal soft-start
SOT23-5 (2.92 x 2.84 x 1mm) and LLP-6 (3 x 3 x 0.8 mm)
packaging
■ Fully enabled for WEBENCH® Power Designer
Applications
■
■
■
■
■
Boost / SEPIC Conversions from 3.3V, 5V Rails
Space Constrained Applications
Embedded Systems
LCD Displays
LED Applications
System Performance
Efficiency vs Load Current
VOUT = 20V
Efficiency vs Load Current
VOUT = 12V
30167212
30167214
Typical Application
30167201
© 2011 Texas Instruments Incorporated
301672
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LMR62421 SIMPLE SWITCHER® 24Vout, 2.1A Step-Up Voltage Regulator in SOT-23
October 31, 2011
LMR62421
Connection Diagrams
Top View
Top View
30167203
5-Pin SOT23
30167204
6-Pin LLP
Ordering Information
Order Number
Description
Package Type
Package Drawing
LMR62421XMFE
LMR62421XMF
LMR62421XMFX
LMR62421XSDE
LMR62421XSD
SOT23-5
MF05A
1000 Units on Tape & Reel
3000 Units on Tape & Reel
1.6 MHz
250 Units on Tape & Reel
LLP-6
SDE06A
LMR62421XSDX
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Supplied As
250 Units on Tape & Reel
1000 Units on Tape & Reel
4500 Units on Tape & Reel
2
LMR62421
Pin Descriptions - 5-Pin SOT23
Pin
Name
1
SW
Function
2
GND
3
FB
Feedback pin. Connect FB to external resistor divider to set output voltage.
4
EN
Shutdown control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN +
0.3V.
5
VIN
Supply voltage for power stage, and input supply voltage.
Switch node. Connect to the inductor, output diode.
Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible to this
pin.
Pin Descriptions - 6-Pin LLP
Pin
Name
Function
1
PGND
Power ground pin. Place PGND and output capacitor GND close together.
2
VIN
Supply voltage for power stage, and input supply voltage.
3
EN
Shutdown control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN +
0.3V.
4
FB
Feedback pin. Connect FB to external resistor divider to set output voltage.
5
AGND
6
SW
DAP
GND
Signal ground pin. Place the bottom resistor of the feedback network as close as possible to this pin & pin
4.
Switch node. Connect to the inductor, output diode.
Signal & Power ground. Connect to pin 1 & pin 5 on top layer. Place 4-6 vias from DAP to bottom layer GND
plane.
3
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LMR62421
Storage Temp. Range
-65°C to 150°C
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
VIN
SW Voltage
FB Voltage
EN Voltage
ESD Susceptibility (Note 6)
Junction Temperature (Note 2)
-0.5V to 7V
-0.5V to 26.5V
-0.5V to 3.0V
-0.5V to VIN + 0.3V
2kV
150°C
Operating Ratings
(Note 1)
VIN
VEN (Note 7)
Junction Temperature Range
2.7V to 5.5V
0V to VIN
−40°C to +125°C
Electrical Characteristics (Note 3), (Note 4) Limits in standard type are for TJ = 25°C only; limits in boldface
type apply over the junction temperature range of (TJ = -40°C to 125°C). Minimum and Maximum limits are guaranteed through
test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for
reference purposes only. VIN = 5V unless otherwise indicated under the Conditions column.
Symbol
VFB
ΔVFB/VIN
Parameter
Feedback Voltage
Feedback Voltage Line Regulation
Conditions
Min
Typ
Max
−40°C ≤ to TJ ≤ +125°C (SOT23-5)
1.230 1.255
1.280
0°C ≤ to TJ ≤ +125°C (SOT23-5)
1.236 1.255
1.274
−40°C ≤ to TJ ≤ +125°C (LLP-6)
1.225 1.255
1.285
−0°C ≤ to TJ ≤ +125°C (LLP-6)
1.229 1.255
1.281
VIN = 2.7V to 5.5V
0.06
Units
V
%/V
IFB
Feedback Input Bias Current
0.1
1
µA
FSW
Switching Frequency
1200
1600
2000
kHz
DMAX
Maximum Duty Cycle
88
96
%
DMIN
Minimum Duty Cycle
5
%
RDS(ON)
Switch On Resistance
ICL
Switch Current Limit
SS
Soft Start
IQ
UVLO
SOT23-5
170
330
LLP-6
190
350
2.1
3
A
4
Quiescent Current (switching)
7.0
Quiescent Current (shutdown)
VEN = 0V
Undervoltage Lockout
VIN Rising
VIN Falling
ms
11
80
2.3
1.7
mΩ
mA
nA
2.65
V
1.9
Shutdown Threshold Voltage
(Note 7)
Enable Threshold Voltage
(Note 7)
I-SW
Switch Leakage
VSW = 24V
1.0
µA
I-EN
Enable Pin Current
Sink/Source
100
nA
VEN_TH
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4
0.4
1.8
V
Parameter
Conditions
Min
Typ
LLP-6
80
SOT23-5
118
LLP-6
18
SOT23-5
60
θJA
Junction to Ambient
0 LFPM Air Flow (Note 5)
θJC
Junction to Case
TSD
Thermal Shutdown Temperature (Note 2)
160
Thermal Shutdown Hysteresis
10
Max
Units
°C/W
°C/W
°C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see Electrical Characteristics.
Note 2: Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.
Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 4: Typical numbers are at 25°C and represent the most likely parametric norm.
Note 5: Applies for packages soldered directly onto a 3” x 3” PC board with 2oz. copper on 4 layers in still air.
Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 7: Do not allow this pin to float or be greater than VIN +0.3V.
5
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LMR62421
Symbol
LMR62421
Typical Performance Characteristics
Current Limit vs Temperature
FB Pin Voltage vs Temperature
30167206
30167207
Oscillator Frequency vs Temperature
Typical Maximum Output Current vs VIN
30167208
30167210
RDSON vs Temperature
Efficiency vs Load Current, Vo = 20V
30167212
30167211
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LMR62421
Efficiency vs Load Current, Vo = 12V
Output Voltage Load Regulation
30167214
30167216
Output Voltage Line Regulation
30167217
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LMR62421
Simplified Internal Block Diagram
30167218
FIGURE 1. Simplified Block Diagram
schematic (Figure 2), and its associated waveforms (Figure
3). The LMR62421 supplies a regulated output voltage by
switching the internal NMOS control switch at constant frequency and variable duty cycle. A switching cycle begins at
the falling edge of the reset pulse generated by the internal
oscillator. When this pulse goes low, the output control logic
turns on the internal NMOS control switch. During this ontime, the SW pin voltage (VSW) decreases to approximately
GND, and the inductor current (IL) increases with a linear
slope. IL is measured by the current sense amplifier, which
generates an output proportional to the switch current. The
sensed signal is summed with the regulator’s corrective ramp
and compared to the error amplifier’s output, which is proportional to the difference between the feedback voltage and
VREF. When the PWM comparator output goes high, the output switch turns off until the next switching cycle begins.
During the switch off-time, inductor current discharges
through diode D1, which forces the SW pin to swing to the
output voltage plus the forward voltage (VD) of the diode. The
regulator loop adjusts the duty cycle (D) to maintain a constant output voltage .
General Description
The LMR62421 is an easy-to-use, space-efficient 2.1A lowside switch regulator ideal for Boost and SEPIC DC-DC regulation. It provides all the active functions to provide local DC/
DC conversion with fast-transient response and accurate regulation in the smallest PCB area. Switching frequency is
internally set to 1.6 MHz, allowing the use of extremely small
surface mount inductor and chip capacitors while providing
efficiencies near 90%. Current-mode control and internal
compensation provide ease-of-use, minimal component
count, and high-performance regulation over a wide range of
operating conditions. External shutdown features an ultra-low
standby current of 80 nA ideal for portable applications. Tiny
SOT23-5 and LLP-6 packages provide space-savings. Additional features include internal soft-start, circuitry to reduce
inrush current, pulse-by-pulse current limit, and thermal shutdown.
Application Information
THEORY OF OPERATION
The following operating description of the LMR62421 will refer
to the Simplified Block Diagram (Figure 1) the simplified
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LMR62421
30167219
FIGURE 2. Simplified Schematic
30167220
FIGURE 3. Typical Waveforms
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LMR62421
CURRENT LIMIT
The LMR62421 uses cycle-by-cycle current limiting to protect
the internal NMOS switch. It is important to note that this current limit will not protect the output from excessive current
during an output short circuit. The input supply is connected
to the output by the series connection of an inductor and a
diode. If a short circuit is placed on the output, excessive current can damage both the inductor and diode.
30167224
Design Guide
FIGURE 4. Inductor Current
ENABLE PIN / SHUTDOWN MODE
The LMR62421 has a shutdown mode that is controlled by
the Enable pin (EN). When a logic low voltage is applied to
EN, the part is in shutdown mode and its quiescent current
drops to typically 80 nA. Switch leakage adds up to another
1 µA from the input supply. The voltage at this pin should
never exceed VIN + 0.3V.
THERMAL SHUTDOWN
Thermal shutdown limits total power dissipation by turning off
the output switch when the IC junction temperature exceeds
160°C. After thermal shutdown occurs, the output switch
doesn’t turn on until the junction temperature drops to approximately 150°C.
A good design practice is to design the inductor to produce
10% to 30% ripple of maximum load. From the previous equations, the inductor value is then obtained.
SOFT-START
This function forces VOUT to increase at a controlled rate during start up. During soft-start, the error amplifier’s reference
voltage ramps to its nominal value of 1.255V in approximately
4.0ms. This forces the regulator output to ramp up in a more
linear and controlled fashion, which helps reduce inrush current.
Where: 1/TS = FSW = switching frequency
One must also ensure that the minimum current limit (2.1A)
is not exceeded, so the peak current in the inductor must be
calculated. The peak current (ILPK ) in the inductor is calculated by:
INDUCTOR SELECTION
The Duty Cycle (D) can be approximated quickly using the
ratio of output voltage (VO) to input voltage (VIN):
or
ILpk = IIN + ΔIL
ILpk = IOUT / D' + ΔIL
When selecting an inductor, make sure that it is capable of
supporting the peak input current without saturating. Inductor
saturation will result in a sudden reduction in inductance and
prevent the regulator from operating correctly. Because of the
speed of the internal current limit, the peak current of the inductor need only be specified for the required maximum input
current. For example, if the designed maximum input current
is 1.5A and the peak current is 1.75A, then the inductor should
be specified with a saturation current limit of >1.75A. There is
no need to specify the saturation or peak current of the inductor at the 3A typical switch current limit.
Because of the operating frequency of the LMR62421, ferrite
based inductors are preferred to minimize core losses. This
presents little restriction since the variety of ferrite-based inductors is huge. Lastly, inductors with lower series resistance
(DCR) will provide better operating efficiency. For recommended inductors see Example Circuits.
Therefore:
Power losses due to the diode (D1) forward voltage drop, the
voltage drop across the internal NMOS switch, the voltage
drop across the inductor resistance (RDCR) and switching
losses must be included to calculate a more accurate duty
cycle (See Calculating Efficiency and Junction Temperature
for a detailed explanation). A more accurate formula for calculating the conversion ratio is:
INPUT CAPACITOR
An input capacitor is necessary to ensure that VIN does not
drop excessively during switching transients. The primary
specifications of the input capacitor are capacitance, voltage,
RMS current rating, and ESL (Equivalent Series Inductance).
The recommended input capacitance is 10 µF to 44 µF depending on the application. The capacitor manufacturer
specifically states the input voltage rating. Make sure to check
any recommended deratings and also verify if there is any
Where η equals the efficiency of the LMR62421 application.
The inductor value determines the input ripple current. Lower
inductor values decrease the size of the inductor, but increase
the input ripple current. An increase in the inductor value will
decrease the input ripple current.
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LMR62421
significant change in capacitance at the operating input voltage and the operating temperature. The ESL of an input
capacitor is usually determined by the effective cross sectional area of the current path. At the operating frequencies
of the LMR62421, certain capacitors may have an ESL so
large that the resulting impedance (2πfL) will be higher than
that required to provide stable operation. As a result, surface
mount capacitors are strongly recommended. Multilayer ceramic capacitors (MLCC) are good choices for both input and
output capacitors and have very low ESL. For MLCCs it is
recommended to use X7R or X5R dielectrics. Consult capacitor manufacturer datasheet to see how rated capacitance
varies over operating conditions.
OUTPUT CAPACITOR
The LMR62421 operates at frequencies allowing the use of
ceramic output capacitors without compromising transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple. The output capacitor
is selected based upon the desired output ripple and transient
response. The initial current of a load transient is provided
mainly by the output capacitor. The output impedance will
therefore determine the maximum voltage perturbation. The
output ripple of the converter is a function of the capacitor’s
reactance and its equivalent series resistance (ESR):
30167229
FIGURE 5. Setting Vout
A good value for R1 is 10kΩ.
COMPENSATION
The LMR62421 uses constant frequency peak current mode
control. This mode of control allows for a simple external
compensation scheme that can be optimized for each application. A complicated mathematical analysis can be completed to fully explain the LMR62421’s internal & external
compensation, but for simplicity, a graphical approach with
simple equations will be used. Below is a Gain & Phase plot
of a LMR62421 that produces a 12V output from a 5V input
voltage. The Bode plot shows the total loop Gain & Phase
without external compensation.
When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the output
ripple will be approximately sinusoidal and 90° phase shifted
from the switching action .
Given the availability and quality of MLCCs and the expected
output voltage of designs using the LMR62421, there is really
no need to review any other capacitor technologies. Another
benefit of ceramic capacitors is their ability to bypass high
frequency noise. A certain amount of switching edge noise
will couple through parasitic capacitances in the inductor to
the output. A ceramic capacitor will bypass this noise while a
tantalum will not. Since the output capacitor is one of the two
external components that control the stability of the regulator
control loop, most applications will require a minimum at 4.7
µF of output capacitance. Like the input capacitor, recommended multilayer ceramic capacitors are X7R or X5R.
Again, verify actual capacitance at the desired operating voltage and temperature.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the following equation where
R1 is connected between the FB pin and GND, and R2 is
connected between VOUT and the FB pin.
30167231
FIGURE 6. LMR62421 Without External Compensation
One can see that the Crossover frequency is fine, but the
phase margin at 0dB is very low (22°). A zero can be placed
just above the crossover frequency so that the phase margin
will be bumped up to a minimum of 45°. Below is the same
application with a zero added at 8 kHz.
11
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LMR62421
30167229
FIGURE 8. Setting External Pole-Zero
30167232
FIGURE 7. LMR62421 With External Compensation
The simplest method to determine the compensation component value is as follows.
Set the output voltage with the following equation.
There is an associated pole with the zero that was created in
the above equation.
It is always higher in frequency than the zero.
A right-half plane zero (RHPZ) is inherent to all boost converters. One must remember that the gain associated with a
right-half plane zero increases at 20dB per decade, but the
phase decreases by 45° per decade. For most applications
there is little concern with the RHPZ due to the fact that the
frequency at which it shows up is well beyond crossover, and
has little to no effect on loop stability. One must be concerned
with this condition for large inductor values and high output
currents.
Where R1 is the bottom resistor and R2 is the resistor tied to
the output voltage. The next step is to calculate the value of
C3. The internal compensation has been designed so that
when a zero is added between 5 kHz & 10 kHz the converter
will have good transient response with plenty of phase margin
for all input & output voltage combinations.
Lower output voltages will have the zero set closer to 10 kHz,
and higher output voltages will usually have the zero set closer to 5 kHz. It is always recommended to obtain a Gain/Phase
plot for your actual application. One could refer to the Typical
applications section to obtain examples of working applications and the associated component values.
Pole @ origin due to internal gm amplifier:
There are miscellaneous poles and zeros associated with
parasitics internal to the LMR62421, external components,
and the PCB. They are located well over the crossover frequency, and for simplicity are not discussed.
FP-ORIGIN
PCB Layout Considerations
Pole due to output load and capacitor:
When planning layout there are a few things to consider when
trying to achieve a clean, regulated output. The most important consideration when completing a Boost Converter layout
is the close coupling of the GND connections of the COUT capacitor and the LMR62421 PGND pin. The GND ends should
be close to one another and be connected to the GND plane
with at least two through-holes. There should be a continuous
ground plane on the bottom layer of a two-layer board. The
FB pin is a high impedance node and care should be taken to
make the FB trace short to avoid noise pickup and inaccurate
regulation. The feedback resistors should be placed as close
as possible to the IC, with the AGND of R1 placed as close
as possible to the GND (pin 5 for the LLP) of the IC. The
VOUT trace to R2 should be routed away from the inductor and
any other traces that are switching. High AC currents flow
through the VIN, SW and VOUT traces, so they should be as
This equation only determines the frequency of the pole for
perfect current mode control (CMC). I.e, it doesn’t take into
account the additional internal artificial ramp that is added to
the current signal for stability reasons. By adding artificial
ramp, you begin to move away from CMC to voltage mode
control (VMC). The artifact is that the pole due to the output
load and output capacitor will actually be slightly higher in frequency than calculated. In this example it is calculated at 650
Hz, but in reality it is around 1 kHz.
The zero created with capacitor C3 & resistor R2:
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LMR62421
Substituting IL1 into IL2
short and wide as possible. However, making the traces wide
increases radiated noise, so the designer must make this
trade-off. Radiated noise can be decreased by choosing a
shielded inductor. The remaining components should also be
placed as close as possible to the IC. Please see Application
Note AN-1229 for further considerations and the LMR62421
demo board as an example of a good layout.
The average inductor current of L2 is the average output load.
SEPIC Converter
The LMR62421 can easily be converted into a SEPIC converter. A SEPIC converter has the ability to regulate an output
voltage that is either larger or smaller in magnitude than the
input voltage. Other converters have this ability as well (CUK
and Buck-Boost), but usually create an output voltage that is
opposite in polarity to the input voltage. This topology is a
perfect fit for Lithium Ion battery applications where the input
voltage for a single cell Li-Ion battery will vary between 3V &
4.5V and the output voltage is somewhere in between. Most
of the analysis of the LMR62421 Boost Converter is applicable to the LMR62421 SEPIC Converter.
SEPIC Design Guide:
SEPIC Conversion ratio without loss elements:
30167263
FIGURE 9. Inductor Volt-Sec Balance Waveform
Applying Charge balance on C1:
Therefore:
Since there are no DC voltages across either inductor, and
capacitor C6 is connected to Vin through L1 at one end, or to
ground through L2 on the other end, we can say that
Small ripple approximation:
In a well-designed SEPIC converter, the output voltage, and
input voltage ripple, the inductor ripple and is small in comparison to the DC magnitude. Therefore it is a safe approximation to assume a DC value for these components. The
main objective of the Steady State Analysis is to determine
the steady state duty-cycle, voltage and current stresses on
all components, and proper values for all components.
In a steady-state converter, the net volt-seconds across an
inductor after one cycle will equal zero. Also, the charge into
a capacitor will equal the charge out of a capacitor in one cycle.
Therefore:
VC1 = VIN
Therefore:
This verifies the original conversion ratio equation.
It is important to remember that the internal switch current is
equal to IL1 and IL2. During the D interval. Design the converter
so that the minimum guaranteed peak switch current limit
(2.1A) is not exceeded.
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LMR62421
30167280
FIGURE 10. SEPIC CONVERTER Schematic
Steady State Analysis with Loss
Elements
30167266
Using inductor volt-second balance & capacitor charge balance, the following equations are derived:
Therefore:
One can see that all variables are known except for the duty
cycle (D). A quadratic equation is needed to solve for D. A
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14
LMR62421
less accurate method of determining the duty cycle is to assume efficiency, and calculate the duty cycle.
30167290
Efficiencies for Typical SEPIC Application
30167272
SEPIC Converter PCB Layout
FIGURE 11. SEPIC PCB Layout
The layout guidelines described for the LMR62421 BoostConverter are applicable to the SEPIC Converter. Below is a
proper PCB layout for a SEPIC Converter.
15
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LMR62421
LLP Package
The LMR62421 packaged in the 6–pin LLP:
30167273
FIGURE 12. Internal LLP Connection
For certain high power applications, the PCB land may be
modified to a "dog bone" shape (see Figure 19). Increasing
the size of ground plane, and adding thermal vias can reduce
the RθJA for the application.
30167274
FIGURE 13. PCB Dog Bone Layout
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LMR62421
LMR62421 Design Example 1
30167275
Vin = 3V - 5V, Vout = 12V @ 500 mA
LMR62421 Design Example 2
30167278
Vin = 3V, Vout = 5V @ 500 mA
17
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LMR62421
LMR62421 Design Example 3
30167279
Vin = 3.3V, Vout = 20V @ 100 mA
LMR62421 SEPIC Design Example 4
30167281
Vin = 2.7V - 5V, Vout = 3.3V @ 500mA
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LMR62421
Physical Dimensions inches (millimeters) unless otherwise noted
6-Lead LLP Package
NS Package Number SDE06A
5-Lead SOT23-5 Package
NS Package Number MF05A
19
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LMR62421 SIMPLE SWITCHER® 24Vout, 2.1A Step-Up Voltage Regulator in SOT-23
Notes
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