(ARCHIVED) FXAS21000, Xtrinsic 3-Axis Digital Rate Gyroscope - Data Sheet

Freescale Semiconductor, Inc.
Data Sheet: Advance Information
FXAS21000
Rev 1.3, 11/2014
3-Axis Digital Angular Rate
Gyroscope
FXAS21000
FXAS21000 is a small, low-power, 3-axis yaw, pitch, and roll
angular rate gyroscope. The full-scale range is adjustable from
±200°/s to ±1600°/s, with Output Data Rates (ODR) from 1.5625
to 200 Hz. It features both I2C and SPI interfaces. The device
may be configured to generate an interrupt when a userprogrammable angular rate threshold is crossed on any one of
the enabled axes.
ED
24 QFN
4 mm x 4 mm x 1 mm
Case 2209-01
FXAS21000 is available in a plastic QFN package; the device is
guaranteed to operate over the extended temperature range of
–40 °C to +85 °C.
Reserved
Reserved
Reserved
Reserved
23
22
21
20
1
19
GND
INT2
2
18
VDDIO
FXAS21000
SPI_CS_B
24 pin QFN
16
VREGD
GND
5
4 mm x 4 mm x 1 mm
15
VDD
Reserved
6
14
GND
Reserved
7
13
SA0 / MISO
9
10
11
12
SDA / MOSI
/ SPI_DIO
8
SCL / SCLK
17
4
Reserved
INT1
RST_B
Reserved
H
C
A
R
24
GND
3
Typical Applications
• Game controller
• Gyro stabilized electronic compass
• Orientation determination
• Gesture-based user interfaces and Human Machine Interface (HMI)
• Indoor navigation
• Mobile phones
• Hobby and toy grade RC vehicles and UAVs
• Virtual and augmented reality devices (including glasses)
This document contains information on a new product. Specifications and information herein
are subject to change without notice. © 2014 Freescale Semiconductor, Inc. All rights reserved.
Reserved
Top View
IV
• Supply voltage (VDD) from 1.95 V to 3.6 V
• Interface supply voltage (VDDIO) from 1.62 V to 3.6 V
• I2C interfaces
• Normal mode (100 kHz)
• Fast mode (400 kHz)
• SPI interface
• Up to 2 MHz (3- and 4-wire modes)
• FIFO buffer is 192 bytes (32 X/Y/Z samples) with stop and
circular operating modes
• Output Data Rates (ODR) from 1.5625 to 200 Hz;
integrated antialiasing filter ensures that output signal
bandwidth is limited to ODR/2
• Angular rate sensitivity of 0.2°/s in ±1600°/s FSR mode
• Low power standby mode
• Rate threshold interrupt
• Integrated self-test function
• No external charge-pump capacitor required
Reserved
Features
Pin Connections
Ordering Information
Part Number
Temperature Range
Package Description
Shipping
FXAS21000CQR1
–40 °C to +85 °C
QFN
Tape and reel (1 k)
Related Documentation
A
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C
H
IV
ED
The FXAS21000CFXAS21000C device features and operations are described in a variety of reference
manuals, user guides, and application notes. To find the most-current versions of these documents:
1. Go to freescale.com/FXAS21000CFXAS21000C.
2. Click on the Documentation tab.
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Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Table of Contents
0x00: STATUS......................................................................25
0x01–0x06: OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB,
OUT_Y_LSB, OUT_Z_MSB, OUT_Z_LSB........................25
6.3 0x07: DR_STATUS.............................................................. 27
6.4 0x08: F_STATUS..................................................................28
6.5 0x09: F_SETUP.....................................................................29
6.6 0x0A: F_EVENT...................................................................30
6.7 0x0B: INT_SOURCE_FLAG............................................... 31
6.8 0x0C: WHO_AM_I............................................................... 32
6.9 0x0D: CTRL_REG0..............................................................32
6.10 0x0E: RT_CFG......................................................................34
6.11 0x0F: RT_SRC...................................................................... 35
6.12 0x10: RT_THS...................................................................... 36
6.13 0x11: RT_COUNT................................................................ 37
6.14 0x12: TEMP.......................................................................... 37
6.15 0x13: CTRL_REG1...............................................................38
6.16 0x14: CTRL_REG2...............................................................40
7 Printed Circuit Board Layout and Device Mounting.......................42
7.1 Printed Circuit Board Layout................................................ 42
7.2 Overview of Soldering Considerations................................. 43
7.3 Halogen Content....................................................................44
8 Package Information........................................................................ 44
8.1 Product Identification Markings............................................44
8.2 Tape and Reel Information....................................................44
8.3 Package Description.............................................................. 45
9 Revision History.............................................................................. 47
ED
6.1
6.2
A
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IV
1 General Description......................................................................... 4
1.1 Block Diagram.......................................................................4
1.2 Pinout.....................................................................................4
1.3 System Connections.............................................................. 6
1.3.1 Typical Application Circuit—I2C Mode................. 6
1.3.2 Typical Application Circuit—SPI Mode..................7
1.4 Sensitive Axes Orientations and Polarities............................7
2 Mechanical and Electrical Specifications........................................ 8
2.1 Absolute Maximum Ratings..................................................8
2.2 Operating Conditions.............................................................9
2.3 Mechanical Characteristics....................................................9
2.4 Electrical Characteristics....................................................... 10
2.5 Temperature Sensor Characteristics...................................... 10
3 Digital Interfaces..............................................................................11
3.1 I²C Interface...........................................................................11
3.1.1 I²C Operation............................................................13
3.1.2 I²C Read Operations................................................. 14
3.1.3 I²C Write Operations................................................ 15
3.2 General SPI Operation (4-Wire Mode)................................. 17
3.2.1 SPI Write (4-Wire Mode).........................................17
3.2.2 SPI Single Read (4-Wire Mode).............................. 18
3.2.3 SPI 3-Wire Mode..................................................... 19
4 Modes of Operation......................................................................... 20
5 Functionality.................................................................................... 20
5.1 FIFO Data Buffer.................................................................. 21
5.2 Rate Threshold Detection Function.......................................22
6 Register Descriptions....................................................................... 24
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
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Freescale Semiconductor, Inc.
General Description
1 General Description
1.1 Block Diagram
Drive Z
Ωx,y,z
X/Y Vibrating
Mass
X–
Voltage References
and Regulators
VDDIO
Z Vibrating
Mass
C2V
Oscillators,
Clock
Generator
Temperature
Sensor
LPF
Gain
AAF
MUX
ADC-14
Digital
Signal
Processing
Angular Rate
Demod
Z–
Y–
GND VDD VREGD
MUX
Configuration
and Control
Registers
NVM,
Trim Logic
IV
Self-Test
Fd
Z+
Y+
Interrupt
Outputs
I2C/SPI Interface
H
X+
Programmable
32 Sample
FIFO Buffer
Drive X/Y
ED
Charge
Pump
INT1
INT2
SCL/SCLK
SDA/MOSI/
SPI_DIO
SA0/MISO
SPI_CS_B
RST_B
A
R
C
Figure 1. Block Diagram
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Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
General Description
Reserved
Reserved
Reserved
Reserved
Reserved
1.2 Pinout
24
23
22
21
20
GND
1
19
GND
INT2
2
18
VDDIO
17
SPI_CS_B
16
VREGD
FXAS21000
4 mm x 4 mm x 1 mm
Reserved
7
8
9
10
11
15
VDD
14
GND
13
SA0 / MISO
12
ED
5
6
SDA / MOSI
/ SPI_DIO
GND
Reserved
SCL / SCLK
24 pin QFN
Reserved
4
Reserved
3
Reserved
INT1
RST_B
Figure 2. Device pinout (top view)
Table 1. Pin functions
Name
Function
1
GND
Ground
2
INT2
Interrupt Output 2
3
INT1
Interrupt Output 1
4
RST_B
5
GND
6
Reserved
Reserved - Must be tied to ground
7
Reserved
Reserved - Must be tied to ground
8
Reserved
Reserved - Must be tied to ground
9
Reserved
Reserved - Must be tied to ground
10
Reserved
Reserved - Must be tied to ground
11
SCL/SCLK
I2C / SPI clock
H
IV
Pin
Reset input (active low, connect to VDDIO if unused)
A
R
C
Ground
12
SDA/MOSI/SPI_DIO I2C data / SPI 4-wire Master Out Slave In / SPI 3-wire data In/Out, 1
I2C address bit0 / SPI 4-wire Master In Slave Out
13
SA0/MISO
14
GND
Ground
15
VDD
Supply voltage
16
VREGD
17
SPI_CS_B
18
VDDIO
Interface supply voltage
19
GND
Ground
20
Reserved
Reserved - Must be tied to ground
21
Reserved
Reserved - Must be tied to ground
Digital regulator output. Please connect a 0.1 μF capacitor between this pin and GND
SPI chip select input, active low. This pin must be held logic high when operating in I2C
interface mode (I2C/SPI_CS_B set high) to ensure correct operation.
Table continues on the next page...
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
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Freescale Semiconductor, Inc.
General Description
Table 1. Pin functions (continued)
Pin
Name
Function
22
Reserved
Reserved - Must be tied to ground
23
Reserved
Reserved - Must be tied to ground
24
Reserved
Reserved - Must be tied to ground
1. MOSI becomes a bidirectional data pin when FXAS21000C is operated in 3-wire SPI mode with CTRL_REG0[SPIW] =
1.
1.3 System Connections
ED
The FXAS21000 offers the choice of connecting to a host processor through either I2C
or SPI interfaces. Figure 3 and Figure 4 show the recommended circuit connections for
implementing both options.
Reserved
Reserved
Reserved
H
Reserved
GND
0.1 μF
INT2
VDDIO
18
3
INT1
SPI_CS_B
17
4
RST_B
5
VDDIO (1.62 – 3.6 V)
19
2
0.1 μF
FXAS21000
VREGD
16
GND
VDD
15
6
Reserved
GND 14
7
Reserved
VDD (1.95 – 3.6 V)
SDA
0.1 μF
SCL
Note: Connect RST_B pin to VDDIO
if unused in the application. A pull-up
resistor may be used if desired.
20
Reserved
INT1
21
Reserved
RST_B
INT2
22
Reserved
4.7 KΩ
(Optional)
GND
A
R
VDDIO
23
C
1
24
Reserved
IV
1.3.1 Typical Application Circuit—I2C Mode
8
9
10
11
12
SAO 13
1.0 μF
SAO
VDDIO
VDDIO
4.7 KΩ
4.7 KΩ
SCL
SDA
Figure 3. I2C mode electrical connections
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Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
General Description
Reserved
Reserved
INT1
20
Reserved
2
21
Reserved
INT2
22
GND
19
INT2
VDDIO
18
3
INT1
SPI_CS_B
17
4
RST_B
VREGD
16
5
GND
VDD
15
6
Reserved
7
Reserved
RST_B
0.1 μF
Host SPI
Chip Select
ED
VDD (1.95 – 3.6 V)
Reserved
8
9
10
11
12
1.0 μF
GND 14
MISO 13
H
IV
Reserved
0.1 μF
Reserved
Note: Connect RST_B pin to VDDIO
if unused in the application. A pull-up
resistor may be used if desired.
VDDIO
(1.62 – 3.6 V)
0.1 μF
FXAS21000
MOSI/SPI_DIO
47 kΩ
(Optional)
GND
23
SCLK
VDDIO
1
24
Reserved
1.3.2 Typical Application Circuit—SPI Mode
MISO
MOSI
SCLK
Note:
MOSI becomes a bidirectional data pin when
FXAS21000 is operated in 3-wire SPI mode
with CTRL_REG0[SPIW] = 1.
C
Figure 4. SPI mode electrical connections
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1.4 Sensitive Axes Orientations and Polarities
+ΩZ
+ΩY
FX
AS
2
10
00
+ΩX
Figure 5. Reference frame for rotational measurement
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
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Freescale Semiconductor, Inc.
Mechanical and Electrical Specifications
2 Mechanical and Electrical Specifications
2.1 Absolute Maximum Ratings
Absolute maximum ratings are the limits the device can be exposed to without
permanently damaging it. Absolute maximum ratings are stress ratings only; functional
operation at these ratings is not guaranteed. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
ED
This device contains circuitry to protect against damage due to high static voltage or
electrical fields. It is advised, however, that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either GND or VDD).
IV
Table 2. Absolute maximum ratings
Rating
Interface supply voltage
Input voltage on any control pin (SA0, SCL, SDA)
Maximum Acceleration (all axes, 100 μs)
C
Operating temperature
A
R
Storage temperature
Min
Max
Unit
VDD
–0.3
3.6
V
VDDIO
–0.3
VDD +0.3
V
VIN
–0.3
VDDIO +0.3
V
gmax
—
5000
g
TOP
–40
+85
°C
TSTG
–40
+125
°C
H
Supply voltage
Symbol
Table 3. ESD and latch-up protection characteristics
Rating
Symbol
Value
Unit
Human body model (HBM)
VHBM
±2000
V
Machine model (MM)
VMM
±200
V
Charge device model (CDM)
VCDM
±500
V
Latch-up current at T = 85 °C
ILU
±100
mA
Caution
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
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Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Mechanical and Electrical Specifications
Caution
This is an ESD sensitive device, improper handling can cause permanent damage to the part.
2.2 Operating Conditions
Table 4. Nominal operating conditions
Supply voltage
Digital supply voltage
Symbol
Min
Typ
Max
Unit
VDD
1.95
—
3.6
V
VDDIO
1.62
—
VDD + 0.3
V
VIH
Digital low-level input voltage on SCL, SDA,
SA0, I2C, RST_B
VIL
Operating temperature
TOP
0.7 * VDDIO
—
—
V
—
—
0.3 * VDDIO
V
–40
+25
+85
°C
IV
Digital high-level input voltage on SCL,
SDA, SA0, I2C, RST_B
ED
Rating
H
2.3 Mechanical Characteristics
Table 5. Mechanical characteristics
Symbol
Test Conditions
C
Parameter
Min
FS = 00
FS
FS = 01
A
R
Full-scale range
Sensitivity1
So
FS = 10
Typ
—
±800
±400
±200
FS = 00
0.2
FS = 10
Unit
—
dps
—
dps/LSB
±1600
FS = 11
FS = 01
Max
—
FS = 11
0.1
0.05
0.025
Sensitivity change vs.
temperature
TCS
–40 °C ≤ T ≤ 85 °C
—
±0.1
—
%/°C
Initial zero-rate offset
ZRO
Factory calibrated, before
board mount
—
±100
—
dps
Zero-rate offset change
vs. temperature
TCO
—
—
±0.3
—
dps/°C
Cross axis sensitivity
CAS
—
—
±1.5
—
%
NL
—
—
±1
—
%FS
STOC
—
50
—
—
LSB
Nonlinearity
Self-test output change
Table continues on the next page...
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
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Freescale Semiconductor, Inc.
Mechanical and Electrical Specifications
Table 5. Mechanical characteristics (continued)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output data bandwidth
BW
—
—
ODR/2
—
Hz
Noise density
ND
ODR = 100 Hz
—
0.055
—
dps/√Hz
Test conditions (unless otherwise noted):
• VDD = 2.5 V
• T = 25 °C
2.4 Electrical Characteristics
ED
1. Sensitivity based on XYZ output data registers that are 14-bit left justified data
Table 6. Electrical characteristics
Test conditions
Min
Typ
Max
Unit
Current consumption
IddAct
Active Mode; Probe data
on a trimmed oscillator
and iref
—
5.8
—
mA
Supply current drain in
Standby mode
IddStby
Standby mode
—
2
—
µA
Supply current drain in
Ready mode
IddRdy
Ready mode
—
4.8
—
mA
High-level output voltage
INT1, INT2
VOH
IO = 500 µA
0.9 * VDDIO
—
—
V
Low-level output voltage
INT1, INT2
VOL
IO = 500 µA
—
—
0.1 * VDDIO
V
Low-level output voltage
SDA
VOLSDA
IO = 500 µA
—
—
0.1 * VDDIO
V
Output data rate
frequency tolerance
ODRTOL
—
—
±2.5
—
% ODR
Signal bandwidth
BW
—
—
ODR/2
—
Hz
Boot time from POR/Reset
to Standby mode
Tboot
—
—
16
—
µs
Turn-on time 1, Standby to
Active mode transition
Ton1
—
—
2/ODR + 250
—
ms
Turn-on time 2, Ready to
Active mode transition
Ton2
—
—
2/ODR + 10
—
ms
C
H
IV
Symbol
A
R
Parameter
Test conditions (unless otherwise noted):
• VDD = 2.5 V
• T = 25°C
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Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Digital Interfaces
2.5 Temperature Sensor Characteristics
Table 7. Temperature sensor characteristics
Characteristic
Symbol
Condition(s)
Min
Typ
Max
Unit
Full scale range
TFSR
—
–40
—
+85
°C
25 °C
—
±1
—
Over Temperature Range
—
±3
—
Temperature Accuracy
—
Operating Temperature
TOP
—
–40
+25
+85
°C
TSENS
—
—
1
—
°C/LSB
Temperature sensor
sensitivity
°C
Test conditions (unless otherwise noted):
ED
• VDD = 2.5 V
3 Digital Interfaces
C
H
IV
The registers embedded inside the FXAS21000 are accessed through either an I2C or
an SPI serial interface. To enable either interface, the VDDIO line must be connected to
the interface supply voltage. If VDD is not present and VDDIO is present, FXAS21000
is in shutdown mode and communications on the interface are ignored. If VDDIO is
maintained, VDD can be powered off and the communications pins will be placed in a
high impedance state. This will allow communications to continue on the bus with
other devices.
Table 8. Serial interface pin descriptions
Pin description
A
R
Pin name
VDDIO
I2C/SPI_CS_B
SCL/SCLK
Digital interface power
I2C/SPI interface mode selection and SPI chip select pin
I2C/SPI serial clock
SDA/MOSI/SPI_DIO
I2C serial data/SPI master serial data out slave serial data in, SPI 3-wire data In/Out (in 3wire SPI mode with CTRL_REG0[SPIW]=1)
SA0/MISO
I2C least significant slave device address bit/SPI master serial data in slave serial data out
3.1 I²C Interface
To use the I2C interface, the I2C/SPI_CS_B pin should be connected to VDDIO. The
implemented I2C interface is compliant with the NXP I2C-bus specification for
Normal and Fast modes. The 7-bit slave addresses that may be assigned to the device
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
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Digital Interfaces
are 0x20 (with SA0 = 0) and 0x21 (with SA0 = 1). When I2C/SPI_CS_B is high, the
SA0/MISO pin is used to define the LSB of this I2C address. The key timing constraints
are shown in Table 9.
Table 9. Slave timing values
Parameter
Symbol
I2C Standard Mode1, 2
I2C Fast Mode1, 2
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
Bus free time between STOP and START
conditions
tBUF
4.7
—
1.3
—
µs
tHD;STA
4
—
0.6
—
µs
Set-up time for a repeated START condition
tSU;STA
4.7
—
0.6
—
µs
Set-up time for a STOP condition
tSU;STO
4
—
0.6
—
µs
0.05
0.93
µs
—
0.93
µs
3.45
—
0.93
µs
250
—
1005
—
ns
4.7
—
1.3
—
µs
tHD;DAT
SDA valid time
SDA valid acknowledge
tVD;DAT
time4
tVD;ACK
SDA setup time
tSU;DAT
SCL clock low time
tLOW
SCL clock high time
SDA and SCL rise time
SDA and SCL fall time
—
—
—
3.45
tHIGH
—
—
0.6
—
µs
tr
—
1000
20+0.1Cb6
300
ns
tf
—
300
20+0.1Cb6
300
ns
50
—
50
ns
H
Pulse width of spikes on SDA and SCL that must
be suppressed by the internal input filter
—
IV
SDA data-hold
time2
ED
Hold time (repeated) START condition
tSP
—
A
R
C
1. All values refer to VIH (min) and VIL (max) levels.
2. tHD;DAT is the data-hold time that is measured from the falling edge of SCL, applies to data in transmission and the
acknowledge.
3. The maximum tHD;DAT could be 3.45 µs and 0.9 µs for Standard mode and Fast mode, but must be less than the
maximum of tVD;DAT or tVD;ACK by a transition time.
4. tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is
worse).
5. tSU;DAT = maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output
stage tf is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL
pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
6. Cb = total capacitance of one bus line in pF.
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Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Digital Interfaces
tBUF
tSU:STA
SCL
tHD:STA
ED
SDA
tVD:ACK
tSP
70%
30%
Sr
tSU:STO
9th clock
P
S
H
3.1.1 I²C Operation
IV
Figure 6. I2C timing diagram
A
R
C
There are two signals associated with the I2C bus: the serial clock line (SCL) and the
serial data line (SDA). The SDA is a bidirectional line used for sending and receiving
the data to/from the interface. External pull-up resistors connected to VDDIO are
required for SDA and SCL. When the bus is free, both the lines are high. The I2C
interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C
standards. Operation at frequencies higher than 400 kHz is possible, but depends on
several factors including the pull-up resistor values, and total bus capacitance (trace +
device capacitance). For more information, see Table 10.
A transaction on the bus is started through a start condition (ST) signal, which is
defined as a HIGH-to-LOW transition on the data line while the SCL line is held
HIGH. After the ST signal has been transmitted by the master, the bus is considered
busy. The next byte of data transmitted contains the slave address in the first seven
bits, and the eighth bit, the read/write bit, indicates whether the master is receiving
data from the slave or transmitting data to the slave. Each device in the system
compares the first seven bits after the ST condition with its own address. If the two
addresses match, the device considers itself addressed by the master. The ninth clock
pulse following the slave address byte (and each subsequent byte) is the acknowledge
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
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Freescale Semiconductor, Inc.
Digital Interfaces
(ACK). The transmitter must release the SDA line during the ACK period. The receiver
must then pull the data line low so that it remains stable low during the high period of
the acknowledge clock period.
The number of bytes per transfer is unlimited. If a receiver cannot receive another
complete byte of data until it has performed some other function, it can hold SCL low
to force the transmitter into a wait state. Data transfer continues only when the receiver
is ready for another byte and releases the data line. This delay action is called clock
stretching. Not all receiver devices support clock stretching, and not all master devices
recognize clock stretching. The FXAS21000 does not support clock stretching.
ED
A LOW-to-HIGH transition on the SDA line while SCL is high is defined as a stop
condition (SP) signal. A write or burst write is always terminated by the master issuing
the SP signal. A master should properly terminate a read by not acknowledging a byte
at the appropriate time in the protocol. A master may also issue a repeated start signal
(SR) during a transfer.
Table 10. I2C Address Selection
Slave Address (SA0 = 1)
Comment
0100000 (0x20)
0100001 (0x21)
Factory Default
H
IV
Slave Address (SA0 = 0)
Single-Byte Read
A
R
3.1.2.1
C
3.1.2 I²C Read Operations
The master (or MCU) transmits an ST to the FXAS21000, followed by the slave
address, with the R/W bit set to “0” for a write, and the FXAS21000 sends an
acknowledgement. Then, the MCU transmits the address of the register to read and the
FXAS21000 sends an acknowledgement. The MCU transmits an SR, followed by the
byte containing the slave address and the R/W bit set to “1” for a read from the
previously selected register. The FXAS21000 then acknowledges and transmits the data
from the requested register. The master does not transmit a no acknowledge (NACK),
but transmits an SP to end the data transfer.
14
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Digital Interfaces
3.1.2.2
Multiple-Byte Read
When performing a multiple-byte or burst read, the FXAS21000 increments the
register address read pointer after a read command is received. Therefore, after
following the steps of a single-byte read, multiple bytes of data can be read from
sequential registers after each FXAS21000 ACK is received. This continues until a
NACK occurs followed by an SP signaling an end of transmission.
3.1.3 I²C Write Operations
Single-Byte Write
ED
3.1.3.1
3.1.3.2
H
IV
To start a write command, the MCU transmits an ST to the FXAS21000, followed by
the slave address with the R/W bit set to “0” for a write, and the FXAS21000 sends an
ACK. Then, the MCU transmits the address of the register to write to, and the
FXAS21000 sends an ACK. Then, the MCU transmits the 8-bit data to write to the
designated register and the FXAS21000 sends an ACK that it has received the data.
Since this transmission is complete, the master transmits an SP to end the data
transfer. The data sent to the FXAS21000 is now stored in the appropriate register.
Multiple-Byte Write
A
R
C
The FXAS21000 automatically increments the register address write pointer after a
write command is received. Therefore, after following the steps of a single-byte write,
multiple bytes of data can be written to sequential registers after each FXAS21000
ACK is received.
Command
Device Address
Bit[6:1]
Device Address Bit[0]
(SA0 pin state)
Device Address
Bit[6:0]
R/W Bit
Address Byte Transmitted
by Master
Read
6'b010000
0
0x20
1
0x41
Write
6'b010000
0
0x20
0
0x40
Read
6'b010000
1
0x21
1
0x43
Write
6'b010000
1
0x21
0
0x42
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
15
Freescale Semiconductor, Inc.
Digital Interfaces
3.1.3.3
I²C Data Sequence Diagrams
<Single Byte Read>
Master
ST
Register Address[7:0]
W
Device Address[6:0]
Slave
ACK
SR
Device Address[6:0]
NACK SP
R
ACK
ACK
Data[7:0]
<Multiple Byte Read>
Master
ST
Register Address[7:0]
W
Device Address[6:0]
SR
Device Address[6:0]
R
ACK
continued
ACK
Master
Slave
ACK
Data[7:0]
Data[7:0]
<Single Byte Write>
ST
Device Address[6:0]
Register Address[7:0]
W
Slave
ACK
ACK
<Multiple Byte Write>
ST
Device Address[6:0]
Slave
ACK
ACK
C
Legend
ST: Start Condition
Data[7:0]
Register Address[7:0]
W
SP: Stop Condition
SP
ACK
H
Master
Data[7:0]
IV
Master
Data[7:0]
NACK SP
ACK
Data[7:0]
ACK
ACK
ED
Slave
ACK: Acknowledge
NACK: No Acknowledge
Data[7:0]
ACK
W: Write = 0
SP
ACK
SR: Repeated Start Condition
A
R
Figure 7. I²C data sequence diagram
16
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Digital Interfaces
3.2 General SPI Operation (4-Wire Mode)
ED
The SPI_CS_B pin is driven low at the start of a SPI transaction, held low for the
duration of the transaction, and driven high after the transaction is complete. During a
transaction, the master toggles the SPI clock (SCLK). The SCLK polarity is defined as
having an idle value that is low and phase where data is captured on the clock's rising
edge and propagated on the falling edge. 1 Single read and write operations are
completed in 16 SCLK cycles or multiples of 8 cycles for multiple read/write
operations. The first SCLK cycle uses the first bit on MOSI to determine whether the
operation is a read (R/W = 1) or a write, such as R/W = 0. The following seven SCLK
cycles are the slave register addresses. SCLK cycles and are present on the MOSI line.
SCLK cycles nine through 16 are the data that is either read (present on MISO) or to
be written (present on MOSI).
IV
3.2.1 SPI Write (4-Wire Mode)
A
R
SPI_CS_B
C
H
A write operation is initiated by transmitting a 0 for the R/W bit. Then, the 7-bit
register address, ADDR[6:0](MSB first) is encoded in the first byte. Data to be written
starts in the second serialized byte (MSB first). Figure 8 shows the bus protocol for
the single write operation.
SCLK
MOSI
2
3
R/W A6
A5
1
4
A4
5
6
7
8
9
A3
A2
A1
A0
D7
10
D6
11
D5
12
D4
13
D3
14
D2
15
D1
16
D0
MISO
Figure 8. SPI single write operation. R/W = 1
Multiple write operations performed similar to the single write except bytes are
written in multiples of eight SCLK cycles. The register address is auto incremented so
that every eighth next clock edges will latch the MSB of the next register. When
desired, the rising edge on SPI_CS_B stops the SPI communication.
1.
From the Freescale SPI protocol definition, the polarity and phase settings are CPOL=0 and CPHA=0.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
17
Freescale Semiconductor, Inc.
Digital Interfaces
SPI_CS_B
SCLK
MOSI
1
2
R/W A6
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
MISO
3.2.2 SPI Single Read (4-Wire Mode)
ED
Figure 9. SPI multiple write operation showing 2 bytes written
IV
NOTE
this description pertains only to the default SPI 4-wire
interface mode (with CTRL_REG0[SPIW] = 0). This mode is
the default out of POR, or after a hard/soft reset.
C
H
A register read operation is initiated by transmitting a 1 for the R/W bit. Then the 7-bit
register read address, A[6:0] is encoded in the first byte. The data is read from the
MISO pin (MSb first). Figure 10 shows the bus protocol for a single byte read
operation.
A
R
SPI_CS_B
SCLK
MOSI
1
2
R/W A6
MISO
3
4
5
6
7
8
A5
A4
A3
A2
A1
A0
9
10
11
12
13
14
15
16
D7
D6
D5
D4
D3
D2
D1
D0
Figure 10. SPI single read operation. R/W = 1
Multi-byte read operations are performed similarly to single byte reads; additional bytes
are read in multiples of eight SCLK cycles. The register read address is auto
incremented by FXAS21002C so that every eighth clock edge will latch the address of
the next register read address. When the desired number of bytes has been read, the
rising edge on the SPI_CS_B terminates the transaction.
18
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Digital Interfaces
SPI_CS_B
SCLK
MOSI
1
2
3
R/W A6
A5
4
A4
5
6
7
8
A3
A2
A1
A0
MISO
9
D7
10
D6
11
12
D5
13
D4
D3
14
D2
15
D1
16
D0
17
D7
18
D6
19
D5
20
D4
21
D3
22
D2
23
D1
24
D0
Figure 11. SPI multiple read operation showing 2 bytes written
ED
3.2.3 SPI 3-Wire Mode
The FXAS21000CFXAS21000C can be configured to operate in 3-wire mode. In this
mode the only signal pins used are SPI_CS_B, SCLK, and SPI_DIO; the MISO pin is
not used. 3- wire mode is selected by setting the SPIW bit in CTRL_REG0.
IV
Read operations in 3-Wire mode are different from read operations in 4-Wire mode.
A
R
SPI_CS_B
C
H
• At the end of the address cycle of read operations in 3-Wire mode, the MOSI pin
switches from SI to SO
• Multiple read operations in 3-wire mode use auto-increment
• Multiple read operations in 3-wire mode return data on the MOSI pin
SCLK
SPI_DIO
1
2
R/W A6
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MISO
Figure 12. SPI 3-Wire single read operation
Write operations in 3-wire mode are identical to write operation in 4-wire mode since
the MISO pin is not used in either mode of operation.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
19
Freescale Semiconductor, Inc.
Modes of Operation
4 Modes of Operation
The device may be placed into one of three functional modes:
• Standby: Some digital blocks are enabled; I2C/SPI communication with
FXAS21000CFXAS21000C is possible.
• Active: All blocks are enabled (digital and analog), the device is actively
measuring the angular rate at the ODR specified in 0x13: CTRL_REG1.
• Ready: The drive circuits are running, but no measurements are being made.
ED
The functional mode is selected using 0x13: CTRL_REG1. After a power-on-reset
(POR) or triggered reset event (software or hardware pin), the device performs a boot
sequence and loads the registers with their preset values, which are stored within the
non-volatile memory (NVM).
Boot
Start-up sequence
IV
Power up
Boot_end = 1
Functional modes
H
Standby
Active = 0
and
Ready = 0
Active = 0
and
Ready = 0
C
Active = 1
Active
A
R
Active = 0
and
Ready = 1
Active = 0
and
Ready = 1
Active = 1
Ready
Figure 13. Functional mode diagram
5 Functionality
The FXAS21000 is a low-power, digital-output, 3-axis gyroscope with both I2C and
SPI interfaces. The functionality includes the following:
• 14-bit output data is left justified in 2's complement format (big endian format)
• Configurable full scale ranges of ±200, ±400, ±800 and ±1600 dps
• Configurable output data rates from 1.5625 to 200 Hz
20
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Functionality
• Configurable high-pass filter cutoff frequency; Integrated Anti-Aliasing Filter
(AAF) limits output data bandwidth to ODR/2
• Embedded rate threshold detection with programmable debounce timer
• 32-sample (X/Y/Z data at 14-bit) FIFO, configurable operating mode (Circular,
Stop, Triggered)
• 2 external interrupt pins that are configurable to trigger on data-ready, rate
threshold, or FIFO events
• Self-test function for indication of device health
• Single control bit for zero-rate offset compensation
ED
Data for each axis must be read from the respective data registers two bytes at a time;
for example, one byte for most significant byte and one byte for least significant.
Combining these two bytes results in a 16-bit 2's complement signed integer with the
sign bit in bit location #15 and the least significant bit in bit location #2. See the tables
below.
15
14
13
12
11
10
9
8
D13
D12
D11
D10
D9
D8
D7
D6
IV
Bit
Data bit
7
6
Data bit
D5
D4
5
4
3
2
1
0
D3
D2
D1
D0
X
X
C
Bit
H
Sign bit
LSB
A
R
The conversion from counts to a dps is done by first converting the 16-bit signed
integer to 14-bit left-justified signed integer. This can be done by dividing the counts
by four, or right shifting by two, then multiplying by the appropriate sensitivity value
for the currently selected full-scale range. See Table 33 for nominal sensitivity values.
5.1 FIFO Data Buffer
FXAS21000 contains a 32-sample FIFO data buffer that is useful for reducing the
frequency of transactions on the I2C/SPI bus. The FIFO can also provide system level
power savings by allowing the host processor/MCU to go into a sleep/low-power
mode while the FXAS21000 collects up to 32 samples of 3-axis angular rate data.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
21
Freescale Semiconductor, Inc.
Functionality
The FIFO can be configured to operate in Circular Buffer mode or Stop mode,
depending on the settings made in the 0x09: F_SETUP register. The Circular Buffer
mode allows the FIFO to be filled with a new sample replacing the oldest sample in the
buffer. The most recent 32 samples will be stored in the buffer. This is useful in
situations where the processor is waiting for a specific interrupt to indicate that the data
must be flushed to analyze the event.
The FXAS21000 FIFO Buffer has a configurable watermark, allowing an interrupt to be
signaled to the processor after a configurable number of samples are stored in the buffer
(from 1 to 32).
ED
5.2 Rate Threshold Detection Function
IV
The embedded rate detection function can be used to detect an angular rate event that
exceeds a programmed threshold on any one of the enabled axes for longer than the
programmed debounce time and to trigger an interrupt signal. The function is fully
programmable, offering flexibility for the various potential use cases.
RT_THS
>
CNT
>
A
R
DBCNTM
|x|
C
Data
RT_Pol
H
Sign
LATCH
RT
RT_COUNT
ELE
Output data rate (Hz)
Counter clock period (ms)
Event duration range
200
5
0 – 1.275
100
10
0 – 2.55
50
20
0 – 5.1
25
40
0 – 10.2
12.5
80
0 – 20.4
Table continues on the next page...
22
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Functionality
Output data rate (Hz)
Counter clock period (ms)
Event duration range
6.25
160
0 – 40.8
3.125
320
0 – 81
1.5625
640
0 – 163
The rate threshold (RT) event flag is set in the 0x0B: INT_SOURCE_FLAG register.
It is cleared by reading the RT_SRC register. Using 0x14: CTRL_REG2, the device
can be configured to generate an external interrupt on either the INT1 or INT2 pin
when a rate threshold event condition occurs.
Data
ED
RT_THS
Counter control
Counter value
RT_COUNT
t
IV
RT
Data
H
Figure 14. RT example 1
RT_THS
C
Counter control
Counter value
A
R
RT
RT_COUNT
t
Figure 15. RT example 2
Data
RT_THS
Counter control
Counter value
RT_COUNT
RT
Resetting the flag
t
Figure 16. RT example 3
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
23
Freescale Semiconductor, Inc.
Register Descriptions
Data
RT_THS
Counter control
Counter value
RT_COUNT
RT
Resetting the flag
t
6 Register Descriptions
ED
Figure 17. RT example 4
Table 12. Register address map
Type
Register address
Default value
STATUS
R
0x00
0x00
OUT_X_MSB
R
0x01
OUT_X_LSB
R
0x02
OUT_Y _MSB
R
0x03
OUT_Y_LSB
R
0x04
0x00
14-bit Y-axis measurement data bits 5:0
OUT_Z_MSB
R
0x05
0x00
14-bit Z-axis measurement data bits 13:6
OUT_Z_LSB
R
0x06
0x00
14-bit Z-axis measurement data bits 5:0
DR_STATUS
R
0x07
0x00
Data-ready status information
F_STATUS
R
0x08
0x00
FIFO Status
0x09
0x00
FIFO setup
F_EVENT
R/W
Comment
IV
Alias for DR_STATUS or F_STATUS
14-bit X-axis measurement data bits 13:6
0x00
14-bit X-axis measurement data bits 5:0
0x00
14-bit Y-axis measurement data bits 13:6
H
0x00
C
F_SETUP
A
R
Name
R
0x0A
—
FIFO event
INT_SRC_FLAG
R
0x0B
—
Interrupt event source status flags
WHO_AM_I
R
0x0C
0xD1
Device ID
CTRL_REG0
R/W
0x0D
0x00
Control register 0: Full-scale range selection, highpass filter setting, SPI mode selection
RT_CFG
R/W
0x0E
0x00
Rate threshold function configuration
RT_SRC
R
0x0F
0x00
Rate threshold event flags status register
RT_THS
R/W
0x10
0x00
Rate threshold function threshold register
RT_COUNT
R/W
0x11
0x01
Rate threshold function debounce counter
R
0x12
0x00
Device temperature in °C
CTRL_REG1
R/W
0x13
0x00
Control register 1: Operating mode, ODR selection,
self-test and soft reset
CTRL_REG2
R/W
0x14
0x00
Control register 2: Interrupt configuration settings
TEMP
24
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Register Descriptions
6.1 0x00: STATUS
The STATUS register content depends on the FIFO mode setting. It is a copy of either
0x07: DR_STATUS or 0x08: F_STATUS. This allows for easy reading of the
relevant status register before reading the current sample output data, or the first
sample stored in the FIFO.
ED
6.2 0x01–0x06: OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB,
OUT_Y_LSB, OUT_Z_MSB, OUT_Z_LSB
IV
X-, Y-, and Z-axis sample data are represented in 14-bit, 2's complement format. The
output data registers are either updated at the output data rate (F_MODE = 00) or
alternately point to the first sample stored in the FIFO buffer (F_MODE > 00). The
FIFO read pointer is incremented whenever the Z-axis data is read. Using the burstread mode, the data is read in the following order: OUT_X_MSB, OUT_X_LSB,
OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB and then OUT_Z_LSB.
C
H
NOTE
To avoid the loss of data, the user must burst-read all six
bytes of sample data (three axes) in a single I2C or SPI
transaction.
NOTE
A
R
Data output LSB registers only contain valid data after a
read of the corresponding axis MSB data register. When
F_SETUP[F_MODE] > 0b00, a data read operation must
start by reading the OUT_X_MSB register in order for the
contents of the other output data registers to be updated for
the currently indexed buffered sample. With
F_SETUP[F_MODE] > 0b00, the OUT_Z_MSB register
must also be read in order to advance the internal buffer read
pointer to index the next sample stored in the FIFO.
NOTE
The two least significant bits of each axis's data LSB are not
used. Data must be right shifted by two bits (or divided by 4)
in the user application to obtain a properly scaled 16-bit 2's
complement rate value.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
25
Freescale Semiconductor, Inc.
Register Descriptions
NOTE
After OUT_Z_LSB is read, the next read register by the autoincrement process is STATUS at 0x00.
Table 13. OUT_X_MSB register (default value 0x00)
Bit
7
6
5
4
Read
3
2
1
0
0
0
0
0
1
0
0
0
0
0
XD[13:6]
Write
Reset
0
0
0
0
Table 14. OUT_X_LSB register (default value 0x00)
7
6
5
Read
4
XD[5:0]
Write
Reset
0
0
0
0
3
2
ED
Bit
0
0
Bit
7
6
5
3
2
1
0
0
0
0
0
1
0
0
0
0
0
YD[13:6]
Write
0
0
0
0
C
Reset
4
H
Read
IV
Table 15. OUT_Y_MSB register (default value 0x00)
Table 16. OUT_Y_LSB register (default value 0x00)
Read
Write
Reset
7
6
5
A
R
Bit
0
0
0
4
3
2
YD[5:0]
0
0
0
Table 17. OUT_Z_MSB register (default value 0x00)
Bit
7
6
5
4
Read
3
2
1
0
0
0
0
0
ZD[13:6]
Write
Reset
0
26
Freescale Semiconductor, Inc.
0
0
0
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Register Descriptions
Table 18. OUT_Z_LSB register (default value 0x00)
Bit
7
6
5
Read
4
3
2
ZD[5:0]
1
0
0
0
0
0
Write
Reset
0
0
0
0
0
0
6.3 0x07: DR_STATUS
ED
The DR_STATUS register provides the sample data acquisition status and reflects the
real-time updates to the OUT_X, OUT_Y, and OUT_Z registers. The content of this
register is reset upon a transition from Standby to Active or from Ready to Active
modes.
Bit
7
6
Read
ZYXOW
ZOW
0
0
IV
Table 19. DR_STATUS register
3
2
1
0
YOW
XOW
ZYXDR
ZDR
YDR
XDR
0
0
0
0
0
0
C
Reset
4
H
Write
5
A
R
Table 20. DR_STATUS field descriptions
Field
7
ZYXOW
Description
X-, Y-, Z-axis data overwrite
• Asserted whenever new X-, Y-, and Z-axis data is acquired before completing the retrieval of the
previous set.
• Cleared after the high-bytes of the data of all channels (OUT_X_MSB, OUT_Y_MSB,
OUT_Z_MSB) are read.
0: No data overwrite has occurred
1: X, Y, and Z data overwrite occurred before the previous data was read
6
ZOW
Z-axis data overwrite
• Asserted whenever a new Z-axis acquisition is completed before the retrieval of the previous data.
When this occurs, the previous data is overwritten.
• Cleared anytime the OUT_Z_MSB (and respectively OUT_Y_MSB, OUT_X_MSB) register is
read.
0: No data overwrite has occurred
1: Z-axis data overwrite occurred before the previous data was read
Table continues on the next page...
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
27
Freescale Semiconductor, Inc.
Register Descriptions
Table 20. DR_STATUS field descriptions (continued)
Field
Description
Y-axis data overwrite
• Asserted whenever a new Y-axis acquisition is completed before the retrieval of the previous data.
When this occurs, the previous data is overwritten.
• Cleared anytime the OUT_Z_MSB (and respectively OUT_Y_MSB, OUT_X_MSB) register is
read.
5
YOW
0: No data overwrite has occurred
1: Y-axis data overwrite occurred before the previous data was read
4
XOW
ED
X-axis data overwrite
• Asserted whenever a new X-axis acquisition is completed before the retrieval of the previous data.
When this occurs, the previous data is overwritten.
• Cleared anytime the OUT_Z_MSB (and respectively OUT_Y_MSB, OUT_X_MSB) register is
read.
0: No data overwrite has occurred
1: X-axis data overwrite occurred before the previous data was read
ZYXDR
IV
3
X-, Y-, and Z-axis data available
• Signals that a new acquisition for any of the channels is available.
• Cleared when the high-bytes of the data of all channels (OUT_X_MSB, OUT_Y_MSB,
OUT_Z_MSB) are read.
0: No new data is ready
1: New data is ready
0: No new Z-axis data is ready
C
ZDR
H
2
Z-axis new data available
• Asserted whenever a new Z-axis data acquisition is completed.
• Cleared anytime the OUT_Z_MSB register is read.
1: New Z-axis data is ready
YDR
A
R
1
Y-axis new data available
• Asserted whenever a new Y-axis data acquisition is completed.
• Cleared anytime the OUT_Y_MSB register is read.
0: No new Y-axis data is ready
1: New Y-axis data is ready
0
XDR
X-axis new data available
• Asserted whenever a new X-axis data acquisition is completed.
• Cleared anytime the OUT_X_MSB register is read.
0: No new X-axis data is ready
1: New X-axis data is ready
28
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Register Descriptions
6.4 0x08: F_STATUS
Indicates the current status of the FIFO, when the FIFO is enabled.
When the FIFO is enabled, the STATUS register (address 0x00) also contains the
same content as this register to facilitate the emptying of the FIFO by the host
processor. The content of this register is reset upon a transition from Standby to
Active or from Ready to Active modes. The SRC_FIFO bit in the 0x0B:
INT_SOURCE_FLAG register is cleared when F_STATUS is read.
Table 21. F_STATUS register
7
6
F_OVF
F_WMKF
5
0
0
3
2
1
0
0
0
F_CNT[5:0]
Write
Reset
4
0
ED
Bit
Read
0
0
0
IV
Table 22. F_Status field descriptions
Field
F_OVF
FIFO overflow flag
• A FIFO overflow event, such as when F_CNT = 32 and a new sample arrives, asserts the F_OVF
flag.
• Cleared when this register is read.
H
7
Description
0: No overflow detected
FIFO watermark flag
• A FIFO sample count greater than or equal to the sample count watermark (determined by the
F_WMRK field in register 0x09: F_SETUP) asserts the F_WMKF event flag.
• Disabling the FIFO clears the F_WMKF
• Cleared when this register is read.
A
R
6
C
1: Overflow detected
F_WMKF
0: No watermark detected
1: Watermark detected
5:0
F_CNT
FIFO sample counter
• Indicates the number of samples currently stored in the FIFO.
• A count value of 0b000000 indicates that the FIFO is empty.
6.5 0x09: F_SETUP
The F_SETUP register is used to configure the FIFO. The FIFO update rate is set by
the selected system ODR (DR bits in 0x13: CTRL_REG1).
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
29
Freescale Semiconductor, Inc.
Register Descriptions
Table 23. F_Setup register
Bit
7
Read
6
5
4
3
F_MODE[1:0]
Write
Reset
0
2
1
0
0
0
F_WMRK[5:0]
0
0
0
0
0
Table 24. F_SETUP field descriptions
Field
F_MODE
Selects the FIFO operating mode
• In the Circular Buffer mode, the oldest sample is discarded and replaced by the newest sample
when the buffer is full (F_STATUS[F_CNT] = 32).
• In the Stop mode, the FIFO will stop accepting new samples when the buffer is full
( F_STATUS[F_CNT] = 32).
• The FIFO operating mode cannot be switched between Circular and Stop modes while the FIFO is
enabled.
• To change the FIFO operating mode, the FIFO function must first be disabled by setting
F_MODE[1:0] = 00.
• Disabling the FIFO clears the FIFO.
ED
7:6
Description
IV
00: FIFO is disabled
01: Circular Buffer mode
1x: Stop mode
5:0
• Used to set the watermark level.
• A FIFO sample count exceeding the watermark level does not stop the FIFO from accepting new
data.
• To suppress FIFO watermark event flag generation, F_WMRK[5:0] can be set to 0x00.
C
F_WMRK
H
FIFO sample count watermark setting
A
R
Default value is 0b000000.
30
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Register Descriptions
6.6 0x0A: F_EVENT
The F_EVENT register is used to monitor the system state and FIFO event status. The
content of this register is reset upon a transition from Standby to Active or from
Ready to Active modes.
Table 25. F_Event register
Bit
7
6
5
Read
0
0
F_EVENT
0
0
0
4
3
2
1
0
0
0
FE_TIME[4:0]
Write
Reset
0
0
0
ED
Table 26. F_EVENT field descriptions
Field
F_EVENT
FIFO Event
• Indicates if either F_WMKF or F_OVF flags are set (logical OR).
• The F_STATUS register must be read to determine which event(s) occurred.
0: FIFO Event not detected
1: FIFO Event was detected
C
FE_TIME
Number of ODR periods elapsed since F_EVENT was set
• indicates the number of samples acquired since a FIFO event flag (overflow or watermark) was
asserted.
• Reset when 0x08: F_STATUS is read.
H
4:0
IV
5
Description
A
R
6.7 0x0B: INT_SOURCE_FLAG
The INT_SOURCE_FLAG register provides the event-flag status for the functions
within the device. Reading the INT_SRC_FLAG register does not reset any event-flag
source bits; they are reset by reading the appropriate event source register. The content
of this register is reset upon a transition from Standby to Active or from Ready to
Active modes.
Table 27. INT_SRC register
Bit
7
6
5
4
3
2
1
0
Read
0
0
0
0
BOOTEND
SRC_FIFO
SRC_RT
SRC_DRDY
0
0
0
0
0
0
0
0
Write
Reset
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
31
Freescale Semiconductor, Inc.
Register Descriptions
Table 28. INT_SRC_FLAG field descriptions
Field
Description
Boot sequence complete event flag
• Asserted as soon as the device boot sequence has completed.
3
BOOTEND
1: Boot sequence is complete
0: Boot sequence is not complete
FIFO event source flag
• Indicates that the FIFO triggered the interrupt
• Cleared by reading the register
2
SRC_FIFO
1: F_OVF or F_WMKF are set, provided the FIFO interrupt is enabled (CTRL_REG2[INT_EN_FIFO=1])
0: Cleared by reading the register
SRC_RT
Rate threshold event source flag
• Indicates that the rate threshold event flag triggered the interrupt
• Cleared by reading RT_SRC register
ED
1
Data ready event source flag
0
H
6.8 0x0C: WHO_AM_I
IV
• Asserted whenever a data-ready event triggers the interrupt
• Cleared whenever the MSB's of the X, Y, and Z axes sample data are read
• Cleared by reading the MSB's of the X, Y, and Z axes sample data
SRC_DRDY
C
The WHO_AM_I register contains the device identifier which is factory programmed to
0xD1.
Table 29. WHO_AM_I
Read
Write
Reset
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
A
R
Bit
6.9 0x0D: CTRL_REG0
CTRL_REG0 is used for general control and configuration of the device. The bit fields
in CTRL_REG0 should be changed only in Standby or Ready modes. Accuracy of the
output data is not guaranteed if these bits are changed when the device is in Active
mode.
32
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Register Descriptions
Table 30. CTRL_REG0
Bit
Read
Write
Reset
7
6
5
4
0
0
SPIW
0
0
0
3
SEL[1:0]
0
2
1
HPF_EN
0
0
0
FS[1:0]
0
0
Table 31. CTRL_REG0 field descriptions
Field
Description
SPI interface mode selection
• The contents should only be modified when the device is in Standby mode
5
0: SPI 4-wire mode (default)
ED
SPIW
1: SPI 3-wire mode (MOSI is used for IN/OUT signals)
4:3
High-pass filter cutoff frequency selection
• Details of the high-pass filter settings are shown in Table 32.
SEL
2
HPF_EN
IV
High-pass filter enable
• The high-pass filter is initialized on mode change, ODR change, and assertion of the ZR_COND
bit.
• When enabled, the HPF is applied to the angular rate data supplied to the output registers/FIFO
and the embedded rate threshold algorithm.
0: High-pass filter disabled (default)
H
1: High-pass filter enabled
1:0
Full-scale range selection
• See Table 33
A
R
C
FS
Table 32. High-pass filter cutoff frequency selection
SEL1
SEL0
Cutoff Frequency in Hz versus ODR
200 Hz
100 Hz
50 Hz
25 Hz
12.5 Hz
6.25 Hz
3.15 Hz
1.5625 Hz
0
0
3.75
1.875
0.937
0.468
0234
0.12
0.06
0.03
0
1
1.925
0.963
0.481
0.241
0.120
0.06
0.03
0.015
1
0
0.975
0.488
0.244
0.122
0.061
0.03
0.015
0.008
1
1
0.495
0.248
0.124
0.062
0.031
0.015
0.008
0.004
Table 33. Selectable Full Scale Ranges
FS1
FS0
Range (dps)
Nominal Sensitivity (dps/LSB)
0
0
±1600
0.2
0
1
±800
0.1
Table continues on the next page...
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
33
Freescale Semiconductor, Inc.
Register Descriptions
Table 33. Selectable Full Scale Ranges (continued)
FS1
FS0
Range (dps)
Nominal Sensitivity (dps/LSB)
1
0
±400
0.05
1
1
±200
0.025
6.10 0x0E: RT_CFG
The RT_CFG register is used to enable the Rate Threshold interrupt generation.
Read
Write
Reset
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
ELE
ZTEFE
YTEFE
XTEFE
0
0
0
0
IV
Bit
ED
Table 34. RT_ CFG Register
Table 35. RT_CFG field descriptions
Field
Description
H
Event latch enable
Enables a latch event
• See Modes of Operation for more details.
• The internal state of the Rate Threshold function is reset when a transition from Standby to Active
or Ready to Active modes occurs.
• The contents should only be modified when the device is in Standby mode
C
3
ELE
A
R
0: Event flag latch disabled
1: Event flag latch enabled
2
ZTEFE
Event flag enable on Z axis
• Enable bits for rate threshold event detection on the Z axis
0: Z event detection disabled
1: Z event detection enabled
1
YTEFE
Event flag enable on Y axis
• Enable bits for rate threshold event detection on the Y axis
0: Y event detection disabled
1: Y event detection enabled
0
XTEFE
Event flag enable on X axis
• Enable bits for rate threshold event detection on the X axis
0: X event detection disabled
1: X event detection enabled
34
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Register Descriptions
6.11 0x0F: RT_SRC
This register indicates the source of the Rate Threshold event. It also clears the
RT_SRC flag in the 0x0B: INT_SOURCE_FLAG register.
Table 36. RT_ SRC Register
Bit
7
6
5
4
3
2
1
0
Read
0
EA
ZRT
Z_RT_Pol
YRT
Y_RT_Pol
XRT
X_RT_Pol
0
0
0
0
0
0
0
0
ED
Write
Reset
Table 37. RT_SRC field descriptions
Field
IV
EA
Event active flag
• Asserted whenever a rate threshold event has been detected on one or more of the enabled axes.
• The contents should only be modified when the device is in Standby mode
• The internal state of the Rate Threshold function is reset when a transition from Standby to Active
or Ready to Active modes occurs.
• It is upon reading this register when RT_CFG[ELE] = 1, or self-cleared by the function when the
condition is no longer true with RT_CFG[ELE] = 0.
H
6
Description
0: No event flags have been asserted
C
1: One or more event flags have been asserted
A
R
Z rate event
• Indicates that a rate threshold event (as defined in Modes of Operation) has been detected on the
Z axis
• Cleared when read if it has been latched (ELE = 1).
5
ZRT
0: Z rate lower than RT_THS value
1: Z rate greater than RT_THS event has occurred
4
Z_RT_Pol
Polarity of Z event
• Indicates the rate polarity for the event detected on the Z axis
0: Z rate event was Positive
1: Z rate event was Negative
3
YRT
Y rate event
• Indicates that a rate threshold event (as defined in Modes of Operation) has been detected on the
Y axis
• Cleared when read if it has been latched (ELE = 1).
0: Y rate lower than RT_THS value
1: Y rate greater than RT_THS value event has occurred
Table continues on the next page...
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
35
Freescale Semiconductor, Inc.
Register Descriptions
Table 37. RT_SRC field descriptions (continued)
Field
Description
Polarity of Y event
• Indicates the rate polarity for the event detected on the Y axis
2
Y_RT_Pol
0: Y rate event was Positive
1: Y rate event was Negative
X rate Event
• Indicates that a rate threshold event (as defined in Modes of Operation) has been detected on the
X axis
• Cleared when read if it has been latched (ELE = 1).
1
XRT
0: X rate lower than RT_THS value
1: X rate greater than RT_THS value event has occurred
0
X_RT_Pol
ED
Polarity of X event
• Indicates the rate polarity for the event detected on the X axis
0: X rate event was positive
IV
1: X rate event was negative
H
6.12 0x10: RT_THS
C
The RT_THS register sets the threshold limit for the detection of the rate and the
debounce counter mode. See Modes of Operation for more details.
Bit
A
R
Table 38. RT_THS register
7
Read
Write
Reset
6
5
4
DBCNTM
0
0
0
3
2
1
0
0
0
0
THS[6:0]
0
0
Table 39. RT_THS field descriptions
Field
7
DBCNTM
Description
Debounce counter mode selection
• The contents should only be modified when the device is in Standby mode
1: Clear counter when angular rate is below threshold value
0: Decrement counter when angular rate is below threshold value
Table continues on the next page...
36
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Register Descriptions
Table 39. RT_THS field descriptions (continued)
Field
6:0
THS
Description
Unsigned 7-bit rate threshold value
• The contents should only be modified when the device is in Standby mode
• The internal state of the Rate Threshold function is reset when a transition from Standby to Active
or Ready to Active modes occurs.
•
The rate threshold in dps is given by the following formula:
6.13 0x11: RT_COUNT
ED
RT_COUNT sets the number of debounce counts. See Modes of Operation for more
details.
Bit
7
6
5
0
IV
Table 40. RT_COUNT register
Read
3
2
1
0
0
0
1
D[7:0]
Write
0
0
0
0
H
Reset
4
Description
Debounce counter value
• The contents should only be modified when the device is in Standby mode
• A transition from Standby to Active or Ready to Active modes resets the internal state of the Rate
Threshold function.
• Stores the number of counts with the angular rate above the threshold needed before asserting
the rate threshold event flag
• The counter period is the same as the selected ODR period, allowing for a debounce time to be
calculated. For example, an RT_COUNT value of 10 (decimal) and an ODR of 100 Hz would
result in a debounce time of 100 ms.
A
R
Field
C
Table 41. RT_COUNT field descriptions
7:0
D
6.14 0x12: TEMP
The TEMP register contains an 8-bit 2's complement temperature value with a range
of –128 °C to +127 °C, with a scaling of 1 °C/LSB. This register is reset only by a
hard reset event (POR/RST_B pin assertion); a soft reset, such as setting
CTRL_REG1[RST] = 1, will not reset the contents of this register. The temperature
data is only compensated when the device is operating in the Active mode.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
37
Freescale Semiconductor, Inc.
Register Descriptions
Table 42. TEMP register
Bit
7
6
5
4
Read
3
2
1
0
0
0
0
0
Temp[7:0]
Write
Reset
0
0
0
0
6.15 0x13: CTRL_REG1
ED
The CTRL_REG1 register is used to configure the device ODR, set the operating mode,
and exercise the self-test and zero-rate offset adjustment functions.
IV
NOTE
Control bits in CTRL_REG1 should be changed only in
Standby or Ready mode. Accuracy of the data is not
guaranteed if these bits are changed when the device is in
Active mode.
Read
Write
6
ZR_cond
RST
0
5
0
4
ST
0
A
R
Reset
7
C
Bit
H
Table 43. CTRL_REG1 register
3
2
DR[2:0]
0
0
0
1
0
Active
Ready
0
0
Table 44. CTRL_REG1 field descriptions
Field
7
ZR_cond1
6
RST
Description
Zero-rate condition
• Used to trigger the offset compensation. For this reason, it is meant to be used only when the
device is in zero rate condition on all axes.
• Writing a 1 to this bit initiates the internal zero-rate offset calibration.
• Self-clears after the zero-rate offset calculation, and it can only be used once after a hard or soft
reset has occurred. In order to use the ZR_cond a second time, the device has to be reset either
with a hard or soft reset.
Software Reset
• Causes a synchronous reset of the device.
• On reset, all registers revert to their default values.
• Self cleared after assertion.
0: Device reset not triggered/completed
1: Device reset triggered
Table continues on the next page...
38
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Register Descriptions
Table 44. CTRL_REG1 field descriptions (continued)
Field
Description
Self-test enable
• Activates the self-test function.
• When ST is set, a data output change will occur even if no angular rate is applied. This allows the
host application to check the functionality of the sensor and the entire measurement signal chain.
5
ST
0: self test disabled
1: self test enabled
4:2
Output Data Rate selection
• Selects the output data rate as per Table 45
1
Active
0
Ready
Standby/Active mode selection
Standby/Ready mode selection
ED
DR
1. ZR_cond may be written only after the first rate sample is available, as it uses the current sample for calibration.
ZR_cond should not be used when the HPF is enabled.
DR1
0
0
0
0
0
1
0
1
Period (ms)
0
200.0
5
1
100.0
10
0
50.0
20
1
1
25
40
0
0
12.5
80
0
1
6.25
160
1
0
3.125
320
1
1.5625
640
A
R
1
ODR (Hz)
C
1
DR0
H
DR2
IV
Table 45. Output data rate selection
1
1
The Active and Ready bits are used to set the device operating mode. In Standby
mode, the device is only capable of digital communication over the I2C or SPI
interfaces. In Ready mode, the device is ready to measure but no sample acquisition is
performed. This state is useful for reducing the power consumption of the device
while also allowing for a fast transition to the Active mode. In Active mode, the
device is fully functional. The Active bit has higher priority than the Ready bit as per
Table 46.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
39
Freescale Semiconductor, Inc.
Register Descriptions
Table 46. Device mode
Active
Ready
Device mode
0
0
Standby
0
1
Ready
1
x
Active
6.16 0x14: CTRL_REG2
ED
This register enables and assigns the output pin(s) and logic polarities for the various
interrupt sources available on the device.
Table 47. CTRL_REG2 register
Bit
7
4
3
2
1
0
INT_CFG_FIFO INT_EN_FIFO INT_CFG_RT INT_EN _RT INT_CFG_DRDY INT_EN_DRDY IPOL PP_OD
Reset
0
0
0
IV
Write
5
0
0
0
0
0
H
Read
6
Table 48. Interrupt Enable register descriptions
0: Interrupt is routed to INT2 pin
A
R
INT_CFG_FIFO
INT_EN_FIFO
5
Description
FIFO interrupt pin routing
7
6
C
Register
INT_CFG_RT
4
INT_EN_RT
3
INT_CFG_DRDY
1: Interrupt is routed to INT1 pin
FIFO Interrupt Enable
0: FIFO interrupt disabled
1: FIFO interrupt enabled
Rate threshold interrupt pin routing
0: Interrupt is routed to INT2 pin
1: Interrupt is routed to INT1 pin
Rate threshold interrupt enable
0: Rate threshold interrupt disabled
1: Rate threshold interrupt enabled
Data-ready interrupt pin routing
0: Interrupt is routed to INT2 pin
1: Interrupt is routed to INT1 pin
Table continues on the next page...
40
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Register Descriptions
Table 48. Interrupt Enable register descriptions (continued)
Register
INT_EN_DRDY
1
IPOL
0
PP_OD
Data ready interrupt enable
0: Data-ready interrupt disabled
1: Data-ready interrupt enabled
Interrupt logic polarity
0: Active low
1: Active high
INT1 and INT2 pin output driver configuration
0: Push-pull output driver
1: Open-drain output driver
ED
2
Description
Table 49. INT pin behavior as a function of PP_OD and IPOL bit settings
PP_OD
IPOL
INT asserted value
INT deasserted value
CMOS output
0
0
0
1
CMOS output
0
1
1
0
External pull-up resistor added
1
0
0
high-z1
External pull-down resistor added
1
1
1
high-z1
IV
INT pin configuration
A
R
C
H
1. High-z = tri-state (high impedance) condition; the state of the INT pin will be defined by the external pull-up or pulldown resistor.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
41
Freescale Semiconductor, Inc.
Printed Circuit Board Layout and Device Mounting
7 Printed Circuit Board Layout and Device Mounting
Printed Circuit Board (PCB) layout and device mounting are critical to the overall
performance of the design. The footprint for the surface mount packages must be the
correct size as a base for a proper solder connection between the PCB and the package.
This, along with the recommended soldering materials and techniques, will optimize
assembly and minimize the stress on the package after board mounting.
7.1 Printed Circuit Board Layout
ED
Freescale application note AN1902, "Assembly Guidelines for QFN and DFN
Packages" discusses the QFN package used by the FXAS21000CFXAS21000C.
IV
The following recommendations are meant to serve as general guidelines for realizing
an effective PCB layout. See Figure 18 for component PCB footprint dimensions.
A
R
C
H
• The PCB land pattern should be designed with Non-Solder Mask Defined (NSMD)
as shown in Figure 18.
• On the layer that the device is soldered, there should be no trace routing or vias
underneath the device's component package.
• No components or vias should be placed at a distance less than 2 mm from the
package land area. This may cause additional package stress if it is too close to the
package land area.
• Signal traces connected to pads should be as symmetric as possible. Put dummy
traces on the NC pads in order to have same length of exposed trace for all pads.
• No copper traces should be on the top layer of the PCB under the package. This
will cause planarity issues with board mount. Freescale QFN sensors are compliant
with Restrictions on Hazardous Substances (RoHS), having halide-free molding
compound (green) and lead-free terminations. These terminations are compatible
with tin-lead (Sn-Pb) as well as tin-silver-copper (Sn-Ag-Cu) solder paste soldering
processes. Reflow profiles applicable to those processes can be used successfully
for soldering the devices.
42
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Printed Circuit Board Layout and Device Mounting
4X 2.175
4
8
24X 0.30
0.18
12
7
24X 0.8
24X 0.3
13
24X 0.725
0.525
20X 0.5
4
1
19
24
20
20X 0.5
Package outline
Package
PCB land pad
4.576
ED
4X 2.160
Package outline
4X 1.438
4X 1.938
24X 0.769
24X 0.269
20X 0.5
Package outline
H
IV
4.576
Solder mask opening
Solder stencil opening
C
Figure 18. Footprint
A
R
7.2 Overview of Soldering Considerations
The information provided here is based on experiments executed on QFN devices.
These experiments cannot represent exact conditions present at a customer site.
Therefore, information herein should be used for guidance purposes only. Process and
design optimizations are recommended to develop an application-specific solution.
With the proper PCB footprint and solder stencil designs, the package will self-align
during the solder reflow process.
• Stencil thickness should be 100 or 125 µm.
• The PCB should be rated for the multiple lead-free reflow condition with a
maximum 260 °C temperature.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
43
Freescale Semiconductor, Inc.
Package Information
• Use a standard pick-and-place process and equipment. Do not use a hand soldering
process.
• Do not use a screw-down or stacking to mount the PCB into an enclosure. These
methods could bend the PCB, which would put stress on the package.
7.3 Halogen Content
ED
This package is designed to be Halogen Free, exceeding most industry and customer
standards. Halogen Free means that no homogeneous material within the assembled
package will contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or
bromine (Br) in excess of 900 ppm or 0.09% weight/weight.
8 Package Information
IV
The FXAS21000 platform uses a 24-lead QFN package, case number 2209-01.
H
8.1 Product Identification Markings
C
Top View
263
S2100
ALYW
A
R
Freescale code
Part number
Traceability date code
Assembly site
Lot code
Work week
44
Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Package Information
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8.2 Tape and Reel Information
Pin 1
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Figure 19. Tape dimensions
Direction
to unreel
Barcode label
side of reel
Figure 20. Tape and reel orientation
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
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Package Information
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8.3 Package Description
This drawing is located at www.freescale.com/files/shared/doc/package_info/98ASA00356D.pdf.
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Freescale Semiconductor, Inc.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
Revision History
9 Revision History
Revision
number
Revision
date
1.0
09/2013
Initial release of document
1.1
10/2013
Register address map, Comments column, 5:0 was 7:2 (3 plcs)
Description
RT_THS register table, THS[6:0] was THS[6:3]
Electrical Characteristics, IddRdy, Typ, 4.8 was 3.8
1.2
7/2014
Figures 3 and 4, changed value of capacitor on pins 18/19 and 14/15 from 1.0 to 0.1 and
added a 0.1 μF capacitor to pins 14/15
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Added Table 2, Temperature sensor characteristics
Table 3, added Maximum Acceleration (all axes, 100 μs)
Table 3, deleted Drop-test height
Table 9, SDA setup time unit changed from μs to ns
Table 32, changed all cutoff frequency values
11/2014
Moved Table 2, Temperature sensor characteristics, to Table 5
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1.3
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Added Appendix A and A.1
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Appendix A: Errata
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A.1 I²C Communications
Description
PFXAS21000C erroneously processes I2C read commands addressed to other devices
on the I2C bus. This can have unintended effects including the clearing of status flags
such as data ready, decrementing the FIFO counter, and de-asserting interrupt pins
cleared by the action of an I2C read on flags. PFXAS21000C does not respond on the
I2C bus to these erroneously processed read commands and it does not respond to I2C
write commands addressed to other devices on the bus. As such, I2C bus
communications are never corrupted and the performance of other devices on the bus
will not be impacted.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
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I²C Communications
Affected device registers
The PFXAS21000C registers and bit fields within these registers which may be
erroneously read when the device is not actively addressed are shaded in the table
below. Reading of these registers and their related bit fields may cause interrupt flags to
be deasserted (for example, data ready, rate threshold, and FIFO status flags), or output
data stored within the FIFO to be lost in applications where F_SETUP[F_MODE] >
0b00 (reading OUT_Z_MSB causes the next stored sample to be latched in the output
registers, thereby discarding the previously stored set).
Register
Address Type
B7
B6
B5
B4
B3
B2
B1
B0
Name
0x00
R
Alias for DR_STATUS or F_STATUS depending on F_MODE setting
OUT_X_MSB
0x01
R
XD[15:8]
OUT_X_LSB
0x02
R
OUT_Y _MSB
0x03
R
OUT_Y_LSB
0x04
R
OUT_Z _MSB
0x05
R
OUT_Z_LSB
0x06
R
DR_STATUS
0x07
R
ZYXOW
ZOW
F_STATUS
0x08
R
F_OVF
F_WMKF
F_SETUP
0x09
R/W
F_EVENT
0x0A
INT_SRC_FLAG
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STATUS
XD[7:0]
YD[15:8]
YD[7:0]
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ZD[15:8]
ZD[7:0]
YOW
XOW
ZYXDR
ZDR
YDR
XDR
F_CNT[5:0]
F_WMR
K[5:0]
R
—
—
FEVENT
0x0B
R
—
—
—
WHO_AM_I
0x0C
R
CTRL_REG0
0x0D
R/W
RT_CFG
0x0E
R/W
—
—
—
—
ELE
ZTEFE
YTEFE
XTEFE
0x0F
R
—
EA
ZRT
Z_RT_P
OL
YRT
Y_RT_P
OL
XRT
X_RT_
POL
0x10
R/W
DBCNTM
0x11
R/W
RT_CNT[7:0]
0x12
R
TEMP[7:0]
CTRL_REG1
0x13
R/W
—
ACTIVE
READ
Y
CTRL_REG2
0x14
R/W
INT_CFG_
FIFO
IPOL
PP_O
D
RT_THS
RT_CNT
TEMP
C
BW[1:0]
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RT_SRC
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F_MODE[1:0]
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FE_TIME[4:0]
—
BOOT_E SRC_FIF SRC_RT SRC_
ND
O
DRDY
WHO_AM_I[7:0]
SPIW
SEL[1:0] HPF_EN
FS[1:0]
THS[6:0]
RST
ST
DR[2:0]
INT_EN INT_CFG INT_EN INT_CFG INT_EN_
_FIFO
_RT
_RT
_DRDY
DRDY
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
I²C Communications
Workarounds
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Three workarounds are associated with this erratum.
• Operate PFXAS21000C on a dedicated I2C bus. The part will behave as expected
provided no I2C commands are sent which specify a different device address.
• Operate PFXAS21000C in SPI mode. This erratum has no impact on SPI
operation.
• When operating PFXAS21000C on a shared I2C bus, poll the output registers
asynchronously under timing from the host microcontroller rather than checking
data ready bits or interrupts.
3-Axis Digital Angular Rate Gyroscope, Rev1.3, 11/2014.
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© 2014 Freescale Semiconductor, Inc.
Document Number FXAS21000
Revision 1.3, 11/2014