ES_LPC11E3x Errata sheet LPC11E3x Rev. 1.2 — 17 September 2014 Errata sheet Document information Info Content Keywords LPC11E36FBD64, LPC11E36FHN33, LPC11E37FBD48, LPC11E37FBD64, LPC11E37HFBD64, LPC11E35FHI33/50, LPC11E3x errata. Abstract This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table. ES_LPC11E3x NXP Semiconductors Errata sheet LPC11E3x Revision history Rev Date Description 1.2 20140917 Added LPC11E35FHI33 part. 1.1 20140123 Added LPC11E37HFBD64 part. 1 20130201 Initial version. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ES_LPC11E3X Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 September 2014 © NXP B.V. 2014. All rights reserved. 2 of 8 ES_LPC11E3x NXP Semiconductors Errata sheet LPC11E3x 1. Product identification The LPC11E3x devices typically have the following top-side marking: LPC11E3x /xxx xxxxxxx xxYYWWxR[x] The last letter in the last line (field ‘R’) will identify the device revision. This Errata Sheet covers the following revisions of the LPC11E3x: Table 1. Device revision table Revision identifier (R) Revision description ‘A’ Initial device revision Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. 2. Errata overview Table 2. Errata summary table Functional problems Short description ADC.1 A/D Global Data register should not be used with burst ‘A’ mode or hardware triggering. Section 3.1 I2C.1 In the slave-transmitter mode, the device set in the monitor mode must write a dummy value of 0xFF into the DAT register. ‘A’ Section 3.2 Table 3. Revision identifier Detailed description AC/DC deviations table AC/DC deviations Short description Revision identifier Detailed description n/a n/a n/a n/a Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description Note.1 During power-up, an unexpected glitch (low pulse) could occur on the port pins as the VDD supply ramps up. ‘A’ Section 5.1 ES_LPC11E3X Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 September 2014 © NXP B.V. 2014. All rights reserved. 3 of 8 ES_LPC11E3x NXP Semiconductors Errata sheet LPC11E3x 3. Functional problems detail 3.1 ADC.1: A/D Global Data register should not be used with burst mode or hardware triggering Introduction: On the LPC11E3x, the START field and the BURST bit in the A/D control register specify whether A/D conversions are initiated via software command, in response to some hardware trigger, or continuously in burst ("hardware-scan") mode. Results of the ADC conversions can be read in one of two ways. One is to use the A/D Global Data Register to read all data from the ADC. Another is to use the individual A/D Channel Data Registers. Problem: If the burst mode is enabled (BURST bit set to ‘1’) or if hardware triggering is specified, the A/D conversion results read from the A/D Global Data register could be incorrect. If conversions are only launched directly by software command (BURST bit = '0' and START = ‘001’), the results read from the A/D Global Data register will be correct provided the previous result is read prior to launching a new conversion. Work-around: When using either burst mode or hardware triggering, the individual A/D Channel Data registers should be used instead of the A/D Global Data register to read the A/D conversion results. ES_LPC11E3X Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 September 2014 © NXP B.V. 2014. All rights reserved. 4 of 8 ES_LPC11E3x NXP Semiconductors Errata sheet LPC11E3x 3.2 I2C.1: In the slave-transmitter mode, the device set in the monitor mode must write a dummy value of 0xFF into the DAT register Introduction: The I2C monitor allows the device to monitor the I2C traffic on the I2C bus in a non-intrusive way. Problem: In the slave-transmitter mode, the device set in the monitor mode must write a dummy value of 0xFF into the DAT register. If this is not done, the received data from the slave device will be corrupted. To allow the monitor mode to have sufficient time to process the data on the I2C bus, the device may need to have the ability to stretch the I2C clock. Under this condition, the I2C monitor mode is not 100 % non-intrusive. Work-around: When setting the device in monitor mode, enable the ENA_SCL bit in the MMCTRL register to allow clock stretching. Software code example to enable the ENA_SCL bit: LPC_I2C_MMCTRL |= (1<<1); //Enable ENA_SCL bit In the I2C ISR routine, for the status code related to the slave-transmitter mode, write the value of 0xFF into the DAT register to prevent data corruption. In order to avoid stretching the SCL clock, the data byte can be saved in a buffer and processed in the Main loop. This ensures the SI flag is cleared as fast as possible. Software code example for the slave-transmitter mode: case case case case case 0xA8: // Own SLA + R has been received, ACK returned 0xB0: 0xB8: // data byte in DAT transmitted, ACK received 0xC0: // (last) data byte transmitted, NACK received 0xC8: // last data byte in DAT transmitted, ACK received DataByte = LPC_I2C->DATA_BUFFER; //Save data. Data can be process in Main loop LPC_I2C->DAT = 0xFF; // Pretend to shift out 0xFF LPC_I2C->CONCLR = 0x08; // clear flag SI break; ES_LPC11E3X Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 September 2014 © NXP B.V. 2014. All rights reserved. 5 of 8 ES_LPC11E3x NXP Semiconductors Errata sheet LPC11E3x 4. AC/DC deviations detail 4.1 n/a 5. Errata notes detail 5.1 Note.1 The General Purpose I/O (GPIO) pins have configurable pull-up/pull-down resistors where the pins are pulled up to the VDD level by default. During power-up, an unexpected glitch (low pulse) could occur on the port pins as the VDD supply ramps up. ES_LPC11E3X Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 September 2014 © NXP B.V. 2014. All rights reserved. 6 of 8 ES_LPC11E3x NXP Semiconductors Errata sheet LPC11E3x 6. Legal information 6.1 Definitions Draft — The document is a draft version only. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or ES_LPC11E3X Errata sheet malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 September 2014 © NXP B.V. 2014. All rights reserved. 7 of 8 ES_LPC11E3x NXP Semiconductors Errata sheet LPC11E3x 7. Contents 1 2 3 3.1 3.2 4 4.1 5 5.1 6 6.1 6.2 6.3 7 Product identification . . . . . . . . . . . . . . . . . . . . 3 Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional problems detail . . . . . . . . . . . . . . . . 4 ADC.1: A/D Global Data register should not be used with burst mode or hardware triggering . . 4 I2C.1: In the slave-transmitter mode, the device set in the monitor mode must write a dummy value of 0xFF into the DAT register . . . . . . . . . . . . . . 5 AC/DC deviations detail . . . . . . . . . . . . . . . . . . 6 n/a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Errata notes detail . . . . . . . . . . . . . . . . . . . . . . . 6 Note.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 7 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 17 September 2014 Document identifier: ES_LPC11E3X