NSC LMX9830

LMX9830
Bluetooth™ Serial Port Module
1.0 General Description
The National Semiconductor LMX9830 Bluetooth Serial
Port module is a highly integrated Bluetooth 2.0 baseband
controller and 2.4 GHz radio, combined to form a complete
small form factor (6.1 mm x 9.1 mm x 1.2 mm) Bluetooth
node.
All hardware and firmware is included to provide a complete solution from antenna through the complete lower
and upper layers of the Bluetooth stack, up to the application including the Generic Access Profile (GAP), the Service Discovery Application Profile (SDAP), and the Serial
Port Profile (SPP). The module includes a configurable service database to fulfil service requests for additional profiles on the host. Moreover, the LMX9830 is pre-qualified
as a Bluetooth Integrated Component. Conformance testing through the Bluetooth qualification program enables a
short time to market after system integration by insuring a
high probability of compliance and interoperability.
Based on National’s CompactRISC™ 16-bit processor
architecture and Digital Smart Radio technology, the
LMX9830 is optimized to handle the data and link management processing requirements of a Bluetooth node.
The firmware supplied in the on-chip ROM memory offers a
complete Bluetooth (v2.0) stack including profiles and command interface. This firmware features point-to-point and
point-to-multipoint link management supporting data rates
up to the theoretical maximum over RFComm of 704 kbps
(Best in Class in the industry). The internal memory supports up to 7 active Bluetooth data links and one active
SCO link.
The on-chip Patch RAM provided for lowest cost and risk,
allows the flexibility of firmware upgrade.
The LMX9830 module is lead free and RoHS (Restriction
of Hazardous Substances) compliant. For more information
on those quality standards, please visit our green compliance website at http://www.national.com/quality/green/
1.1 APPLICATIONS
■ Personal Digital Assistants
■ POS Terminals
■ Data Logging Systems
■ Audio Gateway applications
■ Telemedicine/Medical, Industrial and Scientific.
2.0 Functional Block Diagram
Oscillator/
Crystal
Clock
Generator
including
PLL
Link
Manager
UART
Transport
UART
TXD
RXD
RTS#
CTS#
JTAG
Antenna
Radio
Baseband
Controller
CompactRISC
Processor
Access
bus
SPI
Voltage
Regulator
ROM
Combined
System and
Patch RAM
CVSD
Codecs
Audio
Port
SCL
SDA
MDODI
MWCS#
MSK
MDIDO
SCLK
SFS
STD
SRD
CompactRISC is a trademark of National Semiconductor Corporation.
Bluetooth is a trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor.
© 2006 National Semiconductor Corporation
www.national.com
LMX9830 BluetoothTM Serial Port Module
March 2006
LMX9830
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1
DIGITAL HARDWARE . . . . . . . . . . . . . . . . . . . . . . 3
3.2
FIRMWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.3
DIGITAL SMART RADIO . . . . . . . . . . . . . . . . . . . . 3
3.4
PHYSICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pad Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.1
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . 8
7.2
RF PERFORMANCE CHARACTERISTICS . . . . . 9
7.3
PERFORMANCE DATA (TYPICAL) . . . . . . . . . . 11
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1
BASEBAND AND LINK MANAGEMENT
PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1.1 Bluetooth Lower Link Controller . . . . . . . . . . . . 13
8.1.2 Bluetooth Upper Layer Stack . . . . . . . . . . . . . . 13
8.1.3 Profile support . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1.4 Application with command interface . . . . . . . . . 13
8.1.5 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1.6 External memory interfaces . . . . . . . . . . . . . . . 13
8.1.7 µ-wire/SPI interface . . . . . . . . . . . . . . . . . . . . . 13
8.1.8 Access.bus interface . . . . . . . . . . . . . . . . . . . . 14
8.2
TRANSPORT PORT - UART . . . . . . . . . . . . . . . . 14
8.3
AUDIO PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.3.1 Advanced Audio Interface . . . . . . . . . . . . . . . . 14
8.4
AUXILIARY PORTS . . . . . . . . . . . . . . . . . . . . . . . 15
8.4.1 RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.4.2 General Purpose I/Os . . . . . . . . . . . . . . . . . . . 15
8.5
SYSTEM POWER UP . . . . . . . . . . . . . . . . . . . . . 15
8.6
STARTUP SEQUENCE . . . . . . . . . . . . . . . . . . . . 17
8.6.1 Options Register . . . . . . . . . . . . . . . . . . . . . . . 17
8.6.2 Startup With External PROM Available . . . . . . 17
8.6.3 Startup Without External PROM Available . . . . 17
8.6.4 Configuring the LMX9830 through
transport layer . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.6.5 Auto Baud Rate Detection . . . . . . . . . . . . . . . . 19
8.7
USING AN EXTERNAL EEPROM FOR
NON-VOLATILE DATA . . . . . . . . . . . . . . . . . . . . 20
Digital Smart Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . 20
9.2
RECEIVER FRONT-END . . . . . . . . . . . . . . . . . . 20
9.2.1 Poly-Phase Bandpass Filter . . . . . . . . . . . . . . . 20
9.2.2 Hard-Limiter and RSSI . . . . . . . . . . . . . . . . . . . 20
9.3
RECEIVER BACK-END . . . . . . . . . . . . . . . . . . . . 20
9.3.1 Frequency Discriminator . . . . . . . . . . . . . . . . . 20
9.3.2 Post-Detection Filter and Equalizer . . . . . . . . . 20
9.4
AUTOTUNING CIRCUITRY . . . . . . . . . . . . . . . . . 21
9.5
SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.5.1 Phase-Frequency Detector . . . . . . . . . . . . . . . 21
9.6
TRANSMITTER CIRCUITRY . . . . . . . . . . . . . . . . 21
9.6.1 IQ-DA Converters and TX Mixers . . . . . . . . . . 21
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10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
2
9.7
CRYSTAL REQUIREMENTS . . . . . . . . . . . . . . . 21
9.7.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.7.2 TCXO (Temperature Compensated
Crystal Oscillator) . . . . . . . . . . . . . . . . . . . . . . 24
9.7.3 Optional 32 kHz Oscillator . . . . . . . . . . . . . . . 24
9.7.4 ESR (Equivalent Series Resistance) . . . . . . . 24
9.8
ANTENNA MATCHING AND FRONT-END
FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.9
LOOP FILTER DESIGN . . . . . . . . . . . . . . . . . . . 25
9.9.1 Component Calculations . . . . . . . . . . . . . . . . . 25
9.9.2 Phase Noise and Lock-Time Calculations . . . 27
9.9.3 Practical Optimization . . . . . . . . . . . . . . . . . . . 28
9.9.4 Component Values for NSC Reference
Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Integrated Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1.1 Operation Modes . . . . . . . . . . . . . . . . . . . . . . 30
10.1.2 Default Connections . . . . . . . . . . . . . . . . . . . . 30
10.1.3 Event Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1.4 Default Link Policy . . . . . . . . . . . . . . . . . . . . . 31
10.1.5 Audio Support . . . . . . . . . . . . . . . . . . . . . . . . . 31
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.1 POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . 32
11.2 ENABLING AND DISABLING UART
TRANSPORT 32
11.2.1 Hardware Wake up functionality . . . . . . . . . . . 32
11.2.2 Disabling the UART transport layer . . . . . . . . 33
11.2.3 LMX9830 enabling the UART interface . . . . . 33
11.2.4 Enabling the UART transport layer from
the host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.1 FRAMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.1.1 Start and End Delimiter . . . . . . . . . . . . . . . . . . 34
12.1.2 Packet Type ID . . . . . . . . . . . . . . . . . . . . . . . . 34
12.1.3 Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.1.4 Data Length . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.1.5 Checksum: . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.2 COMMAND SET OVERVIEW . . . . . . . . . . . . . . 35
Usage Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.1 SCENARIO 1: POINT-TO-POINT
CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.2 SCENARIO 2: AUTOMATIC POINT-TO-POINT
CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.3 SCENARIO 3: POINT-TO-MULTIPOINT CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Datasheet Revision History . . . . . . . . . . . . . . . . . . . . 45
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 46
■
■
■
■
■
3.3 DIGITAL SMART RADIO
Compliant with the Bluetooth 2.0 Core Specification
Better than -80 dBm input sensitivity
Class 2 operation
Low power consumption:
High integration:
– Implemented in 0.18 µm CMOS technology
– RF includes antenna filter and switch on-chip
■ Accepts external clock or crystal input:
– 13 MHz Typical
– Supports 10 - 20 MHz
– Secondary 32.768 kHz oscillator for low-power
modes
– 20 ppm cumulative clock error required for Bluetooth
■ Synthesizer:
– Integrated VCO
– Provides all clocking for radio and baseband functions
■ Antenna Port (50 Ohms nominal impedance):
– Embedded front-end filter for enhanced out of band
performance
■ Integrated transmit/receive switch (full duplex operation
via antenna port)
■ Better than -80 dBm input sensitivity
■ 0 dBm typical output power
3.1 DIGITAL HARDWARE
■
■
■
■
■
■
■
■
Baseband and Link Management processors
CompactRISC Core
Embedded ROM and Patch RAM memory
UART Command/Data Port:
– Support for up to 921.6k baud rate
Auxiliary Host Interface Ports:
– Link Status
– Transceiver Status (Tx or Rx)
– Three General Purpose I/Os, available through the
API
– Alternative IO functions:
– Link Status
– Transport layer activity
Advanced Power Management (APM) features
– Advanced power management functions
Advanced Audio Interface for external PCM codec
ACCESS.bus and SPI/Microwire for interfacing with external non-volatile memory
3.4 PHYSICAL
■ Compact size - 6.1 mm x 9.1 mm x 1.2 mm
■ Complete system interface provided in Ball Grid Array on
underside for surface mount assembly
4.0 Order Information
Table 1. Order Information
3.2 FIRMWARE
Order Number
■ Complete Bluetooth Stack including:
– Baseband and Link Manager
– L2CAP, RFCOMM, SDP
– Profiles:
– GAP
– SDAP
– SPP
■ Additional Profile support on Host. e.g:
– Dial Up Networking (DUN)
– Facsimile Profile (FAX)
– File Transfer Protocol (FTP)
– Object Push Profile (OPP)
– Synchronization Profile (SYNC)
– Headset (HSP)
– Handsfree Profile (HFP)
– Basic Imaging Profile (BIP)
– Basic Printing Profile (BPP)
■ On-chip application including:
– Default connections
– Command Interface:
– Link setup and configuration (also Multipoint)
– Configuration of the module
– Service database modifications
– UART Transparent mode
– Optimized cable replacement
– Automatic transparent mode
– Event filter
Shipment Method
LMX9830SM
NOPB1
388 pcs Tray
LMX9830SMX
NOPB1
2500 pcs Tape & Reel
1.
3
Spec
NOPB = No Pb (No Lead)
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LMX9830
3.0 Features
LMX9830
5.0 Connection Diagram
1
2
3
4
5
6
7
8
9
10
NC
NC
NC
RDY#
TMS
XOSCEN
PG6
VDD_IF
TE
VDD_RF
RTS#
GND
RXD
TCK
TDI
OP6/SCL/MSK
CTS#
TXD
VCC_IO
VCC_CORE
MDODI
PG7
VCC
GND
STD
VCC_IOP
SCLK
SFS
SRD
OP5
A
B
B_RESET_RA# RESET_BB# RESET_RA# GND_RF
TST1/DIV2#
C
ENV1#
TST2
TST3
TST4
GND_RF
OP4/PG4
GND_IF
TST5
TST6
ANT
X2_CKO
VDD_IOR
X1_CKI
VDD_X1
GND_VCO
GND_RF
X2_CKI
VCC_PLL
X1_CKO
VCO_OUT
VCO_IN
VDD_VCO
D
OP3/MWCS# OP7/SDA/MDIDO TDO
E
F
X-ray - Top View
Figure 1. Connection Diagram
6.0 Pad Description
Table 2. Pin Description
Pad
Location
Type
X1_CKO
F7
O
Crystal 10-20 MHz
X1_CKI
E7
I
Crystal or External Clock 10-20 MHz
X2_CKI
F5
I
GND (if not
used)
32.768 kHz Crystal Oscillator.
X2_CKO
E5
O
NC (if not used)
32.768 kHz Crystal Oscillator.
RESET_RA#
B8
I
B_RESET_RA#
B6
O
RESET_BB#
B7
I
ENV1#
C6
I
NC
ENV1: Environment Select (active low) used for
manufacturing test only
TE
A9
I
GND
Test Enable - Used for manufacturing test only
TST1/DIV2#
B10
I
NC
Pad Name
Default Layout
Description
Radio Reset (active low)
NC
Buffered Reset Radio Output (active low)
Baseband Reset (active low)
TST1: Test Mode. Leave not connected to permit use
with VTune automatic tuning algorithm
DIV2#: No longer supported
TST2
C7
I
GND
Test Mode, Connect to GND
TST3
C8
I
GND
Test Mode, Connect to GND
TST4
C9
I
GND
Test Mode, Connect to GND
TST5
D8
I
GND
Test Mode, Connect to GND
TST6
D9
I
VCO_OUT
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4
Test Input,
Connect to VCO_OUT via 0Ohm resistor to permit
use with VTune automatic tuning algorithm
LMX9830
6.0 Pad Description (Continued)
Table 2. Pin Description
Pad
Location
Type
MDODI1
D1
I/O
OP6/SCL/MSK
C1
OP6: I
Pad Name
SCL/MSK
: I/O
OP7: I
Default Layout
Description
SPI Master Out Slave In
See Table 17 on
page 17
OP6: Pin checked during Startup Sequence for configuration option
SCL: ACCESS.Bus Clock
MSK: SPI Shift
See Table 17 on
page 17
OP7: Pin checked during Startup Sequence for configuration option
SDA: ACCESS.Bus Serial Data
MDIDO: SPI Master In Slave Out
OP7/SDA/MDID
O
D4
OP3/MWCS#
D3
I
See Table 17 on
page 17 and
Table 18 on page
19
OP3: Pin checked during Startup Sequence for configuration option
MWCS#: SPI Slave Select Input (active low)
OP4/PG4
D6
OP4: I
See Table 17 on
page 17 and
Table 18 on page
19
OP4: Pin checked during Startup Sequence for configuration option
PG4: GPIO
See Table 17 on
page 17 and
Table 18 on page
19
OP5: Pin checked during Startup Sequence for configuration option
SDA/MDI
DO: I/O
PG4: I/O
OP5
F4
I/O
SCLK
F1
I/O
Audio PCM Interface Clock
SFS
F2
I/O
Audio PCM Interface Frame Synchronization
SRD
F3
I
Audio PCM Interface Receive Data Input
STD
E3
O
Audio PCM Interface Transmit Data Output
XOSCEN
A6
O
Clock Request. Toggles with X2 (LP0) crystal
enable/disable
PG6
A7
I/O
GPIO
PG7
D2
I/O
GPIO - Default setup RF traffic LED indication
CTS#2
C2
I
RXD
B3
I
RTS#3
B1
O
TXD
C3
O
RDY#
A4
O
NC
JTAG Ready Output (active low)
TCK
B4
I
NC
JTAG Test Clock Input
TDI
B5
I
NC
JTAG Test Data Input
TDO
D5
O
NC
JTAG Test Data Output
TMS
A5
I
NC
JTAG Test Mode Select Input
VCO_OUT
F8
O
Charge Pump Output, connect to Loop filter
VCO_IN
F9
I
VCO Tuning Input, feedback from Loop filter
D10
I/O
RF Antenna 50 ohm Nominal Impedance
VCC_PLL
F6
O
1.8V Core Logic Power Supply Output
VCC_CORE
C5
O
1.8V Voltage Regulator Output
ANT
GND (if not
used)
Host Serial Port Clear To Send (active low)
Host Serial Port Receive Data
NC (if not used)
Host Serial Port Request To Send (active low)
Host Serial Port Transmit Data
5
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LMX9830
6.0 Pad Description (Continued)
Table 2. Pin Description
Pad
Location
Type
VDD_X1
E8
I
Power Supply Crystal Oscillator
VDD_VCO
F10
I
Power Supply VCO
VDD_RF
A10
I
Power Supply RF
VDD_IOR
E6
I
Power Supply I/O Radio/BB
VDD_IF
A8
I
Power Supply IF
VCC_IOP
E4
I
Power Supply Audio Interface
VCC_IO
C4
I
Power Supply I/O
VCC
E1
I
Voltage Regulator Input
GND_VCO
E9
Ground
GND_RF
B9, C10,
E10
Ground
GND_IF
D7
Ground
Pad Name
GND
NC
1.
2.
3.
Default Layout
B2,E2
A1,A2,A3
Description
Ground
NC
Treat as no connect. Place pad for mechanical stability
Must use 1k ohm pull up
Connect to GND if CTS is not use.
Treat as No Connect if RTS is not used. Pad required for mechanical stability.
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6
Absolute Maximum Ratings (see Table 3) indicate limits
beyond which damage to the device may occur. Operating
Ratings (see Table 4) indicate conditions for which the
device is intended to be functional.
The following conditions are true unless otherwise stated in
the tables below:
■ TA = -40°C to +85°C
■ VCC = 3.3V
This device is a high performance RF integrated circuit and
is ESD sensitive. Handling and assembly of this device
should be performed at ESD free workstations.
■ RF system performance specifications are guaranteed
on National Semiconductor Mesa board rev 1.1 reference design platform.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VCC
Digital Voltage Regulator input
-0.2
4.0
V
VI
Voltage on any pad with GND = 0V
-0.2
VCC + 0.2
V
VDD_RF
Supply Voltage Radio
0.2
3.3
V
0
dBm
1.95
V
+150
oC
VDD_IF
VDD_X1
VDD_VCO
PINRF
RF Input Power
VANT
Applied Voltage to ANT pad
TS
Storage Temperature Range
TL
Lead Temperature1 (solder 4 sec.)
225
oC
TLNOPB
Lead Temperature NOPB1,2 (solder 40 sec.)
260
°C
ESDHBM
ESD - Human Body Model
2000
V
ESDMM
ESD - Machine Model
2003
V
1.
2.
3.
-65
Reference IPC/JDEC J-STD-20C spec.
NOPB = No Pb (No Lead)
A 200V ESD rating applies to all pins except OP3, OP6, OP7, MDODI, SCLK, SFS, STD, TDO, and ANT pins = 150V.
Table 4. Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
Unit
2.5
2.75
3.6
V
10
us
VCC
Digital Voltage Regulator input
TR
Digital Voltage Regulator Rise Time
TA
Ambient Operating Temperature Range
Fully Functional Bluetooth Node
-40
+25
+125
oC
VCC_IO
Supply Voltage Digital I/O
1.6
3.3
3.6
V
VCC_PLL
Internally connected to VCC_Core
VDD_RF
Supply Voltage Radio
2.5
2.75
3.0
V
VDD_IOR
Supply Voltage Radio I/O
1.6
2.75
VDD_RF
V
VCC_IOP
Supply Voltage PCM Interface
1.6
3.3
3.6
V
VCC_CORE
Supply Voltage Output
VCC_COREMAX
Supply Voltage Output Max Load
VCC_CORESHORT
When used as Supply Input (VCC grounded)
VDD_IF
VDD_X1
VDD_VCO
7
1.6
1.8
V
5
mA
1.8
2.0
V
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LMX9830
7.0 General Specifications
LMX9830
7.0 General Specifications (Continued)
Table 5. Power Supply Requirements1,2
Symbol
Parameter
ICC-TX
Max
Unit
Power supply current for continuous transmit
65
mA
ICC-RX
Power supply current for continuous receive
65
mA
IRXSL
Receive Data in SPP Link, Slave4
26
mA
IRXM
Receive Data in SPP Link, Master4
23
mA
ISnM
Sniff Mode, Sniff interval 1 second4
5.6
mA
ISC-TLDIS
Scanning, No Active Link, TL Disabled4
0.43
mA
IIdle
Idle, Scanning Disabled, TL Disabled4
100
µA
1.
2.
3.
4.
Min
Typ3
Power supply requirements based on Class II output power.
Based on UART Baudrate 921.6kbit/s.
VCC = 3.3V, VCC_IO = 3.3V, Ambient Temperature = +25 °C.
Average values excluding IO
7.1 DC CHARACTERISTICS
Table 6. Digital DC Characteristics
Symbol
VIH
VIL
Parameter
Min
Max
Units
V
Logical 1 Input Voltage high
1.6V ≤ VCC_IO ≤ 3.0V
0.7 x VCC_IO
VCC_IO + 0.2
(except oscillator I/O)
3.0V ≤ VCC_IO ≤ 3.6V
2.0
VCC_IO + 0.2
Logical 0 Input Voltage low
1.6V ≤ VCC_IO ≤ 3.0V
-0.2
0.25 x VCC_IO
(except oscillator I/O)
3.0V ≤ VCC_IO ≤ 3.6V
-0.2
0.8
VHYS
Hysteresis Loop Width1
IOH
Logical 1 Output Current
IOL
Logical 0 Output Current
1.
Condition
0.1 x VCC_IO
V
VOH = 2.4V,
VCC_IO = 3.0V
-10
mA
VOH = 0.4V,
VCC_IO = 3.0V
10
mA
Guaranteed by design.
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V
8
LMX9830
7.0 General Specifications (Continued)
7.2 RF PERFORMANCE CHARACTERISTICS
■ TA = -40°C to +85°C
In the performance characteristics tables the following
applies:
■ VDD_RF = 2.8V unless otherwise specified
RF system performance specifications are guaranteed on
National Semiconductor Mesa Board rev 1.1 reference design platform.
■ All tests performed are based on Bluetooth Test Specifi-
cation revision 2.0.
■ All tests are measured at antenna port unless otherwise
specified
Table 7. Receiver Performance Characteristics
Symbol
RXsense
Parameter
Receive Sensitivity
PinRF
Maximum Input Level
IMP2,3
Intermodulation Performance
RSSI
RSSI Dynamic Range at LNA Input
ZRFIN3
Input Impedance of RF Port
(RF_inout)
Return Loss3
Return Loss
OOB2,3
Out Of Band Blocking
Performance
1.
2.
3.
Typ1
Max
Unit
2.402 GHz
-80
-76
dBm
2.441 GHz
-80
-76
dBm
2.480 GHz
-80
-76
dBm
Condition
BER < 0.001
F1= + 3 MHz,
F2= + 6 MHz,
PinRF = -64 dBm
Min
-10
0
dBm
-38
-36
dBm
-72
-52
Ω
32
Single input impedance
Fin = 2.5 GHz
dBm
-8
dB
PinRF = -10 dBm,
30 MHz < FCWI < 2 GHz,
BER < 0.001
-10
dBm
PinRF = -27 dBm,
2000 MHz < FCWI < 2399 MHz,
BER < 0.001
-27
dBm
PinRF = -27 dBm,
2498 MHz < FCWI < 3000 MHz,
BER < 0.001
-27
dBm
PinRF = -10 dBm,
3000 MHz < FCWI < 12.75 GHz,
BER < 0.001
-10
dBm
Typical operating conditions are at 2.75V operating voltage and 25oC ambient temperature.
The f0 = -64 dBm Bluetooth modulated signal, f1 = -39dbm sine wave, f2 = -39 dBm Bluetooth modulated signal, f0 = 2f1
- f2, and |f2 - f1| = n * 1MHz, where n is 3, 4, or 5. For the typical case, n = 3.
Not tested in production
9
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LMX9830
7.0 General Specifications (Continued)
Table 8. Transmitter Performance Characteristics
Symbol
Min
Typ1
Max
Unit
2.402 GHz
-4
0
+3
dBm
2.441 GHz
-4
0
+3
dBm
2.480 GHz
-4
0
+3
dBm
175
kHz
Parameter
POUTRF
Transmit Output Power
Condition
MOD ∆F1AVG
Modulation Characteristics
Data = 00001111
140
165
MOD ∆F2MAX2
Modulation Characteristics
Data = 10101010
115
125
∆F2AVG/∆F1AVG3 Modulation Characteristics
0.8
20 dB Bandwidth
POUT2*fo4
PA 2nd Harmonic
Suppression
Maximum gain setting:
f0 = 2402 MHz,
Pout = 4804 MHz
ZRFOUT5
RF Output Impedance/Input
Impedance of RF Port
(RF_inout)
Pout @ 2.5 GHz
1.
2.
3.
4.
5.
kHz
1000
kHz
-30
dBm
Ω
47
Typical operating conditions are at 2.75V operating voltage and 25oC ambient temperature.
∆F2max > 115 kHz for at least 99.9% of all ∆f2max.
Modulation index set between 0.28 and 0.35.
Out-of-Band spurs only exist at 2nd and 3rd harmonics of the CW frequency for each channel.
Not tested in production.
Table 9. Synthesizer Performance Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
2480
MHz
fVCO
VCO Frequency Range
tLOCK
Lock Time
f0 + 20 kHz
∆f0offset1
Initial Carrier Frequency Tolerance
During preamble
-75
0
75
kHz
∆f0drift1
Initial Carrier Frequency Drift
DH1 data packet
-25
0
25
kHz
DH3 data packet
-40
0
40
kHz
DH5 data packet
-40
0
40
kHz
Drift Rate
-20
0
20
kHz/50µs
tD-Tx
1.
Transmitter Delay Time
2402
From Tx data to antenna
120
4
µs
µs
Frequency accuracy is dependent on crystal oscillator chosen. The crystal must have a cumulative accuracy of < +/20ppm to meet Bluetooth specifications.
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10
LMX9830
7.0 General Specifications (Continued)
7.3 PERFORMANCE DATA (TYPICAL)
Figure 4. Corresponding Eye Diagram
Figure 2. Modulation
Figure 5. Synthesizer Phase Noise
Figure 3. Transmit Spectrum
Filter Insertion Loss
0
-2
IL (dB)
-4
-6
-8
-10
2.1E+09
2.2E+09
2.3E+09
2.4E+09
2.5E+09
2.6E+09
2.7E+09
2.8E+09
Frequency (Hz)
Figure 6. Front-End Bandpass Filter Response
11
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1.00
2.00
S(1.1)
0.50
0.00
m1
0.50
2.00
m2
1.00
m2
freq=2.402ghz
S(1.1)=0.093/-29.733
impedance = Z0* (1.170 - j0.109)
-2.00
-1.00
m1
freq=2.500ghz
S(1.1)=0.035/175.614
impedance = Z0* (0.933 + j0.005)
freq(2.400ghz to 2.500ghz)
Figure 7. TX and RX Pin 50Ω Impedance Characteristics
0.0
-0.6
-1.6
-2.6
-3.6
-4.6
db(s(1.1))
LMX9830
7.0 General Specifications (Continued)
-5.6
-6.6
-7.6
m4
m4
freq=2.402GHz
dB(S(1.1))=-8.282
m5
freq=2.483GHz
dB(S(1.1))=-9.227
m3
freq=2.441GHz
dB(S(1.1))=-9.313
m3
-8.6
m5
-9.6
2.500
12
2.495
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2.485
Figure 8. Transceiver Return Loss
2.480
2.475
2.470
2.465
2.460
2.455
2.450
2.445
2.440
2.435
2.430
2.425
2.420
2.415
2.410
2.400
freq. ghz
8.1 BASEBAND AND LINK MANAGEMENT
PROCESSORS
8.1.5 Memory
The LMX9830 introduces 16 kB of combined system and
Patch RAM memory that can be used for data and/or code
upgrades of the ROM based firmware. Due to the flexible
startup used for the LMX9830 operating parameters like
the Bluetooth Device Address (BD_ADDR) are defined during boot time. This allows reading out the parameters of an
external EEPROM or programming them directly over
UART.
Baseband and Lower Link control functions are implemented using a combination of National Semiconductor’s
CompactRISC 16-bit processor and the Bluetooth Lower
Link Controller. These processors operate from integrated
ROM memory and RAM and execute on-board firmware
implementing all Bluetooth functions.
8.1.1 Bluetooth Lower Link Controller
The integrated Bluetooth Lower Link Controller (LLC) complies with the Bluetooth Specification version 2.0 and
implements the following functions:
8.1.6 External memory interfaces
■ Fast Connect
As the LMX9830 is a ROM based device with no on-chip
non volatile storage, the operation parameters will be lost
after a power cycle or hardware reset. In order to prevent re
initializing such parameters, patches or even user data, the
LMX9830 offers two interfaces to connect an external
EEPROM to the device:
■ Support for 1, 3, and 5 slot packet types
■ µ-wire/SPI
■ 79 Channel hop frequency generation circuitry
■ Access.bus (I2C compatible)
■ Fast frequency hopping at 1600 hops per second
The selection of the interface is done during start up based
on the option pins. See Table 17 on page 17 for the option
pin descriptions.
■ Adaptive Frequency Hopping
■ Interlaced Scanning
■ Power management control
■ Access code correlation and slot timing recovery
8.1.7 µ-wire/SPI interface
8.1.2 Bluetooth Upper Layer Stack
■ RFComm
In case the firmware is configured by the option pins to use
a µ-wire/SPI EEPROM, the LMX9830 will activate that interface and try to read out data from the EEPROM. The external memory needs to be compatible to the reference listed
in Table 10 on page 13. The largest size EEPROM supported is limited by the addressing format of the selected NVM.
■ SDP
The device must have a page size equal to N x 32 bytes.
8.1.3 Profile support
The firmware requires that the EEPROM supports Page
write. Clock must be HIGH when idle.
The integrated upper layer stack is prequalified and
includes the following protocol layers:
■ L2CAP
The on-chip application of the LMX9830 allows full standalone operation, without any Bluetooth protocol layer necessary outside the module. It supports the Generic Access
Profile (GAP), the Service Discovery Application Profile
(SDAP), and the Serial Port Profile (SPP).
Table 10. M95640-S EEPROM 8Kx8
Parameter
The on-chip profiles can be used as interfaces to additional
profiles executed on the host. The LMX9830 includes a
configurable service database to answer requests with the
profiles supported.
8.1.4 Application with command interface
The module supports automatic slave operation eliminating
the need for an external control unit. The implemented
transparent option enables the chip to handle incoming
data raw, without the need for packaging in a special format. The device uses a pin to block unallowed connections.
This pincode can be fixed or dynamically set.
Supplier
ST Microelectronics
Supply Voltage1
1.8 - 3.6V
Interface
SPI compatible (positive clock SPI
Modes)
Memory Size
8K x 8, 64kbit
Clock
Rate1
Access
Acting as master, the application offers a simple but versatile command interface for standard Bluetooth operation
like inquiry, service discovery, or serial port connection.
The firmware supports up to seven slaves. Default Link Policy settings and a specific master mode allow optimized
configuration for the application specific requirements. See
also Section "Integrated Firmware" on page 30.
1.
13
Value
2 MHz
Byte and Page Write (up to
32bytes)
Parameter range reduced to requirements of National
reference design
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LMX9830
8.0 Functional Description
LMX9830
8.0 Functional Description (Continued)
8.1.8 Access.bus interface
8.2 TRANSPORT PORT - UART
In case the firmware is configured by the option pins to use
an access.bus or i2c compatible EEPROM, the LMX9830
will activate that interface and try to read out data from the
EEPROM. The external memory needs to be compatible to
the reference listed in Table 11 on page 14.
The LMX9830 provides one Universal Asynchronous
Receiver Transmitter (UART). The UART interface consists
out of Receive (RX), Transmit (TX), Ready-to-Send (RTS)
and Clear-to-Send signals. RTS and CTS are used for
hardware handshaking between the host and the
LMX9830. Since the LMX9830 acts as gateway between
the bluetooth and the UART interface, National Semiconductor recommends to use the handshaking signals especially for transparent operation. In case two signals are
used CTS needs to be pulled to GND. Please refer also to
“LMX9830 Software User’s Guide” for detailed information
on 2-wire operation.
The largest size EEPROM supported is limited by the
addressing format of the selected NVM. The device must
have a page size equal to N x 32 bytes.
The device uses a 16 bit address format. The device
address must be “000”.
The UART interface supports formats of 8-bit data with or
without parity, with one or two stop bits. It can operate at
standard baud rates from 2400bits/s up to a maximum
baud rate of 921.6kbits/s. DMA transfers are supported to
allow for fast processor independent receive and transmit
operation.
Table 11. 24C64 EEPROM 8kx8
Parameter
Value
Supplier
Atmel
Supply Voltage1
2.7 - 5.5 V
Interface
2 wire serial interface
Memory Size
8K x 8, 64kbit
Clock Rate1
100 KHz
Access
32 Byte Page Write Mode
1.
The UART baudrate is configured during startup by checking option pins OP3, OP4 and OP5 for reference clock and
baudrate. In case Auto baud rate detect is chosen, the
firmware check the NVS area if a valid UART baudrate has
been stored in a previous session. In case, no useful value
can be found the device will switch to auto baud rate detection and wait for an incoming reference signal.
The UART offers wakeup from the power save modes via
the multi-input wakeup module. When the LMX9830 is in
low power mode, RTS# and CTS# can function as
Host_WakeUp and Bluetooth_WakeUp respectively. Table
12 on page 14 represents the operational modes supported by the firmware for implementing the transport via
the UART.
Parameter range reduced to requirements of National
reference design
Table 12. UART Operation Modes
Item
Range
Default at Power-Up
With Auto-Detect
Baud Rate
2.4 to 921.6 kbits/s
Either configured by option pins, NVS
parameter or auto baud rate detection
2.4 to 921.6 kbits/s
Flow Control
RTS#/CTS# or None
RTS#/CTS#
RTS#/CTS#
Parity
Odd, Even, None
None
None
Stop Bits
1,2
1
1
Data Bits
8
8
8
8.3 AUDIO PORT
MC145483 codec, the OKI MSM7717 codec, the Winbond
W681360/W681310 codecs and the PCM slave through
the AAI.
8.3.1 Advanced Audio Interface
The Advanced Audio Interface (AAI) is an advanced version of the Synchronous Serial Interface (SSI) that provides a full-duplex communications port to a variety of
industry-standard 13/14/15/16-bit linear or 8-bit log PCM
codecs, DSPs, and other serial audio devices.
In case an external codec or DSP is used the LMX9830
audio interface generates the necessary bit and frame
clock driving the interface.
Table 13 on page 15 summarizes the audio path selection
and the configuration of the audio interface at the specific
modes.
The interface allows the support one codec or interface.
The firmware selects the desired audio path and interface
configuration by a parameter that is located in RAM
(imported from non-volatile storage or programmed during
boot-up). The audio path options include the Motorola
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The LMX9830 supports one SCO link.
14
LMX9830
8.0 Functional Description (Continued)
.
Table 13. Audio path configuration
Audio setting
AAI Bit
Clock
AAI Frame
Clock
AAI Frame Sync
Pulse Length
8-bit log PCM
(a-law only)
480 KHz
8 KHz
14 Bits
13-bit linear
480 KHz
8 KHz
13 Bits
8-bit log PCM
(a-law only)
520 KHz
8 KHz
14 Bits
13-bit linear
520 KHz
8 KHz
13 Bits
13MHz
8 bit log PCM
A-law and u-law
520 KHz
8 KHz
14 Bits
Advanced audio
interface
13MHz
13-bit linear
520 KHz
8 KHz
13 Bits
Advanced audio
interface
ANY1
8/16 bits
128 - 1024
KHz
8 KHz
8/16 Bits
Interface
Freq
Format
OKI
MSM7717
Advanced audio
interface
ANY1
Motorola
MC1454832
Advanced audio
interface
OKI
MSM7717
Advanced audio
interface
Motorola
MC1454833
Advanced audio
interface
Winbond
W681310
Advanced audio
interface
Winbond
W681360
PCM slave4
1.
2.
3.
4.
13MHz
For supported frequencies see Table 22 on page 24
Due to internal clock divider limitations the optimum of 512KHz, 8KHz can not be reached. The values are set to the
best possible values. The clock mismatch does not result in any discernible loss in audio quality.
Due to internal clock divider limitations the optimum of 512KHz, 8KHz can not be reached. The values are set to the
best possible values. The clock mismatch does not result in any discernible loss in audio quality.
In PCM slave mode, parameters are stored in NVS. Bit clock and frame clock must be generated by the host interface.
PCM slave configuration example: PCM slave uses the slot 0, 1 slot per frame, 16 bit linear mode, long frame sync, normal
frame sync. In this case, 0x03E0 should be stored in NVS. See “LMX9830 Software User’s Guide” for more details.
In alternate function the pins have pre-defined indication
functionality. Please see Table 14 on page 15 for a description on the alternate indication functionality.
8.4 AUXILIARY PORTS
8.4.1 RESET#
There are two reset inputs: RESET_RA# for the radio and
RESET_BB# for the baseband. Both are active low.
Table 14. Alternate GPIO pin configuration
There is also a reset output, B_RESET_RA# (Buffered
Radio Reset) active low. This output follows input
RESET_RA#.
OP4/PG4
When
RESET_RA#
is
released,
going
high,
B_RESET_RA# stays low until the clock has started.
Operation Mode pin to configure Transport Layer settings during boot-up
PG6
GPIO
PG7
RF Traffic indication
Pin
Please see Section 8.5 "System Power Up" on page 15 for
details.
Description
8.4.2 General Purpose I/Os
8.5 SYSTEM POWER UP
The LMX9830 offers 3 pins which either can be used as
indication and configuration pins or can be used for General Purpose functionality. The selection is made out of settings derived out of the power up sequence.
In order to correctly power-up the LMX9830 the following
sequence is recommended to be performed:
In General Purpose configuration the pins are controlled
hardware specific commands giving the ability to set the
direction, set them to high or low or enable a weak pull-up.
The RESET_RA# should be driven high. Then
RESET_BB# should be driven high at a recommended
time of 1ms after the LMX9830 voltage rails are high. The
LMX9830 is properly reset.
Apply VCC_IO and VCC to the LMX9830.
Please see timing diagram, Figure 9 on page 16.
15
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LMX9830
8.0 Functional Description (Continued)
ESR of the crystal also has impact on the startup time of
the crystal oscillator circuit of the LMX9830 (SeeTable 15
and Table 16 on page 16).
all VCC and VDD lines
tPTORRA
RESET_RA#
tPTORBB
RESET_BB#
X1_CKO
LMX9830
Initialization
LMX9830
Oscillator
Start-Up
LMX9830 in Normal Mode
LMX9830 in
Power-Up Mode
Figure 9. LMX9830 Power on Reset Timing
Table 15. LMX9830 Power to Reset timing
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tPTORRA
Power to Reset _RA#
VCC and VCC_IO at operating
voltage level to valid reset
<5001
us
tPTORBB
Reset_RA# to Reset_BB#
VCC and VCC_IO at operating
voltage level to valid reset
12
ms
1.
2.
Rise time on power must switch on fast, rise time <500us.
Recommended value.
Table 16. ESR vs. Startup Time
ESR (Ohm)
Typical1,2
Unit
10
12
ms
25
13
ms
40
16
ms
50
24
ms
80
30
ms
1. Frequency, loading caps and ESR all must be considered for determining startup time.
2. For reference only, must be tested on each system to accurately design POR and correctly startup system.
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16
8.6 STARTUP SEQUENCE
read from it. If the BD Address is not present, enter the
BD address to be saved in the NVS. For more information see Section 8.6.4 "Configuring the LMX9830
through transport layer" on page 19
3. From the Options register OP3, OP4 and OP5, the
LMX9830 checks for clocking information and transport
layer settings. If the NVS information are not sufficient,
the LMX9830 will send the “Await Initialization” event on
the TL (Transport Layer) and wait for additional information (see Section 8.6.3 "Startup Without External PROM
Available" on page 17.)
4. The LMX9830 compensates the UART for new BBCLK
information from the NVS.
5. The LMX9830 starts up the Bluetooth core.
During startup the LMX9830 checks the options register
pins OP3 to OP7 for configuration on operation mode, external clock source, transport layer and available non volatile
storage PROM.
The different options for startup are described in Table 17 on
page 17.
8.6.1 Options Register
External pads in Table 17 on page 17 are latched in this register at the end of Reset. The Options register can be read
by firmware at any time.
All pads are inputs with weak on-chip pull-up/down resistors
during Reset. Resistors are disconnected at the end of
RESET_BB#.
8.6.3 Startup Without External PROM Available
The following sequence will take place if OP6 and OP7 have
been set to “No external memory” as described in Table 17
on page 17.
1 = Pull-up resistor connected in application
0 = Pull-down resistor connected in application
Startup sequence activities:
x = Don’t care
1. From the Options registers OP6 and OP7, the LMX9830
checks if a serial PROM is available to use.
2. From the Options register OP3, OP4 and OP5, the
LMX9830 checks for clocking mode and transport layer.
3. The LMX9830 sends the “Await Initialization” Event on
the TL (Transport Layer) and waits for NVS configuration
commands. The configuration is finalized by sending the
“Enter Bluetooth Mode” command.
4. The LMX9830 compensates the UART for new BBCLK
information from the NVS.
5. The LMX9830 starts up the Bluetooth core.
8.6.2 Startup With External PROM Available
To be able to read out information from an external PROM
the option pins have to be set according to Table 17 on page
17.
Startup sequence activities:
1. From the Options registers OP6 and OP7, the LMX9830
checks if a serial PROM is available to use (ACCESS.bus or Microwire).
2. If serial PROM is available, the permanent parameter
block, patch block, and non-volatile storage (NVS) are
Table 17. Startup Sequence Options1
Package Pad
Comment
OP3
OP4
OP5
OP62
OP73
ENV1#
PD
PD
PD
PD
PD
PU
x
x
x
Open (0)
Open (0)
Open (1)
BBCLK
No serial memory
x
x
x
1
Open (0)
Open (1)
BBCLK
TBD
x
x
x
Open (0)
1
Open (1)
BBCLK
Microwire serial memory
x
x
x
1
1
Open (1)
BBCLK
ACCESS.bus serial memory
T_SCLK
x
x
T_RFDAT
A
T_RFCE
0 BBCLK
Test mode
1.
2.
3.
PD = Internal Pull-down during Reset
PU = Internal Pull-up during Reset
1/0 pull-up/down resistor connected in application.
If OP6 is 1, must use 1k ohm pull up
If OP7 is 1, must use 1k ohm pull up
17
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LMX9830
8.0 Functional Description (Continued)
LMX9830
8.0 Functional Description (Continued)
Power Up or
Reset
Initialization Mode
10-20MHz
OP3/4/5
Clock definition
12 or 13MHz
OP3/4/5
UART speed
Clock defined
in EEPROM
no
yes
Read from
NVS
UART speed
defined in
EEPROM
no
Host sends 0x01 for Autobaudrate, waiting for
“Await Initialization Event”
from LMX9830
yes
9.6/115.2/921.6
Host sends “Set Clock
And Baud Rate”
BD_Addr
defined in
EEPROM
no
LMX9830 sends “Await
Initialization Event” in
case not already happened.
yes
Host sends “Change
Local Bluetooth Address”
Optionally host sends other configuration parameters or patch using
“WriteROM Patch”
If LMX9830 sent “Await Initialization
Event” , Host sends “Enter Bluetooth Mode”, otherwise done automatically
LMX9830
sends”LMX9830 Ready”
Bluetooth Mode
Figure 10. Flow Diagram for the Start-up Sequence
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18
LMX9830
8.0 Functional Description (Continued)
Table 18. Fixed Frequencies
Osc Freq.
(MHz)
BBCLK
(MHz)
PLL
(48 MHz)
OP31
OP42
OP53
12
12
OFF
0
0
0
UART speed read from NVS
ON
0
1
0
Clock and UART baudrate detection
1.
2.
3.
4.
1
Function
10-204
10-20
13
13
OFF
1
0
0
UART speed read from NVS
13
13
OFF
1
0
1
UART speed 9.6 kbps
13
13
OFF
1
1
0
UART speed 115.2 kbps
13
13
OFF
1
1
1
UART speed 921.6 kbps
If OP3 is 1, must use 1k ohm pull up.
If OP4 is 1, must use 1k ohm pull up.
If OP5 is 1, must use 1k ohm pull up.
Supported frequencies see Table 22 on page 24
8.6.4 Configuring the LMX9830 through transport layer
NOTE: In case no EEPROM is used, BDAddr, clock source
and Baudrate are only valid until the next power-cycle or
hardware reset.
As described in Section 8.5 "System Power Up" on page 15,
the LMX9830 will check during startup the Options Registers if an external PROM is available. If the information on
the PROM are incomplete or no PROM is installed the
LMX9830 will boot into the “initialization Mode”.
8.6.5 Auto Baud Rate Detection
The LMX9830 supports an Automatic Baudrate Detection in
case the external clock is different to 12, 13MHz or the
range 10-20 MHz or the baudrate is different to 9.6 kbps,
115.2 or 921.6kbit/s.
The mode is confirmed by the “Await Initialization” Event.
The following information are needed to enter Bluetooth
Mode:
The baudrate detection is based on the measurement of a
single character. The following issues need to be considered:
■ Bluetooth Device Address (BD_Addr)
■ External clock source (only if 10 - 20 MHz has been
selected)
■ The flow control pin CTS must be low or else the host is
in flow stop.
■ UART Baudrate (only if Auto baudrate detection has
been selected)
■ The Auto Baudrate Detector measures the length of the
0x01 character from the positive edge of bit 0 to the
positive edge of stop bit.
In general the following procedure will initialize the
LMX9830:
■ Therefore the very first received character must always
1. Wait for “Await initialization” Event
- Event will only appear if transport layer speed is set or
after successful baudrate detection.
2. Send “Set Clock and Baudrate” Command only if the
clock speed is not known through hardware configuration (i.e only if OP3 OP4 OP5 = 0 1 0).
3. Send “Write BD_Addr” to Configure Local Bluetooth Device Address.
4. Send “Enter Bluetooth Mode”
- LMX9830 will use configured clock and UART speed
and start the command interface.
be a 0x01.
■ The host can restrict itself to send only a 0x01 character
or also can send a command.
■ The host must flush the TX buffer within 50-100 millisec-
onds depend on clock frequency on the host controller.
■ After 50-100 milliseconds the UART is about to be initial-
ized and short after the host should receive a “Await
Initialization” Event or an “Command Status” Event.
CTS
RX
0x01
0x00
50 - 100ms delay
Figure 11. Auto baudrate detection timing diagram
19
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LMX9830
9.0 Digital Smart Radio (Continued)
8.7 USING AN EXTERNAL EEPROM FOR NONVOLATILE DATA
is directly followed by two hard-limiters that together generate an AD-converted RSSI signal.
The LMX9830 offers two interfaces to connect to external
memory. Depending on the EEPROM used, the interface is
activated by setting the correct option pins during start up.
See Table 17 on page 17 for the option pin settings.
9.2.1 Poly-Phase Bandpass Filter
The purpose of the IF bandpass filter is to reject noise and
spurious (mainly adjacent channel) interference that would
otherwise enter the hard limiting stage. In addition, it takes
care of the image rejection.
The external memory is used to store mandatory parameters like the BD_Address as well as many optional parameters like Link Keys or even User data.
The bandpass filter uses both the I- and Q-signals from the
mixers. The out-of-band suppression should be higher than
40 dB (f<1 MHz, f>3 MHz). The bandpass filter is tuned over
process spread and temperature variations by the autotuner
circuitry. A 5th order Butterworth filter is used.
The NVM is organized with fixed addresses for the parameters. Because of that the EEPROM can be preprogrammed
with default parameters in manufacturing. Refer to "Operation Parameters Stored in LMX9830" for the organization of
the NVS map.
9.2.2 Hard-Limiter and RSSI
In case the external memory is empty on first startup the
LMX9830 will behave as like no memory is connected. (See
Section 8.6.3 "Startup Without External PROM Available"
on page 17). During the startup process parameters can be
written directly to the EEPROM to be available after next
bootup. On first bootup, the EEPROM will be automatically
programmed to default values, including the UART speed of
9600 BPS. Patches supplied over the TL will be stored automatically into the EEPROM.
The I- and Q-outputs of the bandpass filter are each followed by a hard-limiter. The hard-limiter has its own reference current. The RSSI (Received Signal Strength
Indicator) measures the level of the RF input signal.
The RSSI is generated by piece-wise linear approximation
of the level of the RF signal. The RSSI has a mV/dB scale,
and an analog-to-digital converter for processing by the
baseband circuit. The input RF power is converted to a 5-bit
value. The RSSI value is then proportional to the input power (in dBm).
9.0 Digital Smart Radio
The digital output from the ADC is sampled on the BPKTCTL signal low-to-high transition.
9.1 FUNCTIONAL DESCRIPTION
The integrated Digital Smart Radio utilizes a heterodyne receiver architecture with a low intermediate frequency (2
MHz) such that the intermediate frequency filters can be integrated on chip. The receiver consists of a low-noise amplifier (LNA) followed by two mixers. The intermediate
frequency signal processing blocks consist of a poly-phase
bandpass filter (BPF), two hard-limiters (LIM), a frequency
discriminator (DET), and a post-detection filter (PDF). The
received signal level is detected by a received signal
strength indicator (RSSI).
9.3 RECEIVER BACK-END
The hard-limiters are followed by a two frequency discriminators. The I-frequency discriminator uses the 90× phaseshifted signal from the Q-path, while the Q-discriminator
uses the 90× phase-shifted signal from the I-path. A polyphase bandpass filter performs the required phase shifting.
The output signals of the I- and Q-discriminator are substracted and filtered by a low-pass filter. An equalizer is added to improve the eye-pattern for 101010 patterns.
After equalization, a dynamic AFC (automatic frequency offset compensation) circuit and slicer extract the RX_DATA
from the analog data pattern. It is expected that the Eb/No
of the demodulator is approximately 17 dB.
The received frequency equals the local oscillator frequency (fLO) plus the intermediate frequency (fIF):
fRF = fLO + fIF (supradyne).
The radio includes a synthesizer consisting of a phase detector, a charge pump, an (off-chip) loop-filter, an RF-frequency divider, and a voltage controlled oscillator (VCO).
9.3.1 Frequency Discriminator
The frequency discriminator gets its input signals from the
limiter. A defined signal level (independent of the power
supply voltage) is needed to obtain the input signal. Both inputs of the frequency discriminator have limiting circuits to
optimize performance. The bandpass filter in the frequency
discriminator is tuned by the autotuning circuitry.
The transmitter utilizes IQ-modulation with bit-stream data
that is gaussian filtered. Other blocks included in the transmitter are a VCO buffer and a power amplifier (PA).
9.2 RECEIVER FRONT-END
The receiver front-end consists of a low-noise amplifier
(LNA) followed by two mixers and two low-pass filters for the
I- and Q-channels.
9.3.2 Post-Detection Filter and Equalizer
The output signals of the FM discriminator first go through a
post-detection filter and then through an equalizer. Both the
post-detection filter and equalizer are tuned to the proper
frequency by the autotuning circuitry. The post-detection filter is a low-pass filter intended to suppress all remaining
spurious signals, such as the second harmonic (4 MHz)
from the FM detector and noise generated after the limiter.
The intermediate frequency (IF) part of the receiver frontend consists of two IF amplifiers that receive input signals
from the mixers, delivering balanced I- and Q-signals to the
poly-phase bandpass filter. The poly-phase bandpass filter
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20
The post-detection filter also helps for attenuating the first
adjacent channel signal. The equalizer improves the eyeopening for 101010 patterns. The post-detection filter is a
third order Butterworth filter.
crystal circuit. Table 22 on page 24 specifies system clock
requirements.
The RF local oscillator and internal digital clocks for the
LMX9830 is derived from the reference clock at the CLK+
input. This reference may either come from an external
clock or a dedicated crystal oscillator. The crystal oscillator
connections require an Xtal and two grounded capacitors.
9.4 AUTOTUNING CIRCUITRY
The autotuning circuitry is used for tuning the bandpass filter, the detector, the post-detection filter, the equalizer, and
the transmit filters for process and temperature variations.
The circuit also includes an offset compensation for the FM
detector.
It is also important to consider board and design dependant capacitance in tuning crystal circuit. Equations that
follow allow a close approximation of crystal tuning capacitance required, but actual values on board will vary with
capacitive properties of the board. As a result, there is
some fine tuning of crystal circuit that has to be done that
can not be calculated, must be tuned by testing different
values of load capacitance.
9.5 SYNTHESIZER
The synthesizer consists of a phase-frequency detector, a
charge pump, a low-pass loop filter, a programmable frequency divider, a voltage-controlled oscillator (VCO), a delta-sigma modulator, and a lookup table.
Many different crystals can be used with the LMX9830. Key
requirements from Bluetooth specification is + 20ppm.
Additionally, ESR (Equivalent Series Resistance) must be
carefully considered. LMX9830 can support maximum of
230ohm ESR, but it is recommended to stay <100ohms
ESR for best performance over voltage and temperature.
Reference Figure 17 on page 25 for ESR as part of crystal
circuit for more information.
The frequency divider consists of a divide-by-2 circuit (divides the 5 GHz signal from the VCO down to 2.5 GHz), a
divide-by-8-or-9 divider, and a digital modulus control. The
delta-sigma modulator controls the division ratio and also
generates an input channel value to the lookup table.
9.5.1 Phase-Frequency Detector
The phase-frequency detector is a 5-state phase-detector.
It responds only to transitions, hence phase-error is independent of input waveform duty cycle or amplitude variations. Loop lockup occurs when all the negative transitions
on the inputs, F_REF and F_MOD, coincide. Both outputs
(i.e., Up and Down) then remain high. This is equal to the
zero error mode. The phase-frequency detector input frequency range operates at 12MHz.
9.7.1 Crystal
The crystal appears inductive near its resonant frequency.
It forms a resonant circuit with its load capacitors. The resonant frequency may be trimmed with the crystal load
capacitance.
1. Load Capacitance
For resonance at the correct frequency, the crystal should
be loaded with its specified load capacitance, which is the
value of capacitance used in conjunction with the crystal
unit. Load capacitance is a parameter specified by the
crystal, typically expressed in pF. The crystal circuit shown
in Figure 13 on page 22 is composed of:
9.6 TRANSMITTER CIRCUITRY
The transmitter consists of ROM tables, two Digital to Analog (DA) converters, two low-pass filters, IQ mixers, and a
power amplifier (PA).
The ROM tables generate a digital IQ signal based on the
transmit data. The output of the ROM tables is inserted into
IQ-DA converters and filtered through two low-pass filters.
The two signal components are mixed up to 2.5 GHz by the
TX mixers and added together before being inserted into
the transmit PA.
■ C1 (motional capacitance)
■ R1 (motional resistance)
■ L1 (motional inductance)
■ C0 (static or shunt capacitance)
The LMX9830 provides some of the load with internal
capacitors Cint. The remainder must come from the external capacitors and tuning capacitors labeled Ct1 and Ct2
as shown in Figure 12 on page 22. Ct1 and Ct2 should
have the same the value for best noise performance.
9.6.1 IQ-DA Converters and TX Mixers
The ROM output signals drive an I- and a Q-DA converter.
Two Butterworth low-pass filters filter the DA output signals.
The 6 MHz clock for the DA converters and the logic circuitry around the ROM tables are derived from the autotuner.
The LMX9830 has an additional internal capacitance
CTUNE of 2.6pF. Crystal load capacitance (CL) is calculated
as the following:
The TX mixers mix the balanced I- and Q-signals up to 2.42.5 GHz. The output signals of the I- and Q-mixers are
summed.
CL = Cint + CTUNE + Ct1//Ct2
The CL above does not include the crystal internal selfcapacitance C0 as shown in Figure 13 on page 22, so the
total capacitance is:
9.7 CRYSTAL REQUIREMENTS
The LMX9830 contains a crystal driver circuit. This circuit
operates with an external crystal and capacitors to form an
oscillator. Figure 12 on page 22 shows the recommended
Ctotal = CL + C0
21
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LMX9830
9.0 Digital Smart Radio (Continued)
LMX9830
9.0 Digital Smart Radio (Continued)
TEW Crystal
The LMX9830 has been tested with the TEW TAS-4025A
crystal, reference Table 19 on page 22 for specification.
Since the internal capacitance of the crystal circuit is 8 pF
and the load capacitance is 16 pF, 12 pF is a good starting
point for both Ct1 and Ct2. The 2480 MHz RF frequency
offset is then tested. Figure 14 on page 23 shows the RF
frequency offset test results.
Based on crystal spec and equation:
CL = Cint + CTUNE + Ct1//Ct2
CL = 8pF + 2.6pF + 6pF = 16.6pF
16.6pF is very close to the TEW crystal requirement of
16pF load capacitance. With the internal shunt capacitance
Ctotal:
Figure 14 on page 23 shows the results are -20 kHz off the
center frequency, which is –1 ppm. The pullability of the
crystal is 2 ppm/pF, so the load capacitance must be
decreased by about 1.0 pF. By changing Ct1 or Ct2 to 10
pF, the total load capacitance is decreased by 1.0 pF. Figure 15 on page 23 shows the frequency offset test results.
The frequency offset is now zero with Ct1 = 10 pF, Ct2 = 10
pF.
Ctotal = 16.6pF + 5pF = 21.6pF
LMX9830
CLK+
CLK-
Cint
CTUNE
Reference Table 20 on page 22 for crystal tuning values
used on Mesa Development Board with TEW crystal.
Table 19. TEW TAS-4025A
Specification
Ct2
Ct1
Crystal
Figure 12. LMX9830 Crystal Recommended
Circuit
R1
C1
L1
C0
Value
Package
4.0x2.5x0.65 mm - 4 pads
Frequency
13.000 MHz
Mode
Fundamental
Stability
> ±15ppm @-40 to +85C
CL Load Capacitance
16pF
ESR
80 Ω max.
C0 Shunt Capacitance
5pF
Drive Level
50 ±10uV
Pullability
2 ppm/pF min
Storage Temperature
-40 to +85C
Figure 13. Crystal Equivalent Circuit
Table 20. TEW on LMX9830 DONGLE
2. Crystal Pullability
Pullability is another important parameter for a crystal,
which is the change in frequency of a crystal with units of
ppm/pF, either from the natural resonant frequency to a
load resonant frequency, or from one load resonant frequency to another. The frequency can be pulled in a parallel resonant circuit by changing the value of load
capacitance. A decrease in load capacitance causes an
increase in frequency, and an increase in load capacitance
causes a decrease in frequency.
3. Frequency Tuning
Frequency Tuning is achieved by adjusting the crystal load
capacitance with external capacitors. It is a Bluetooth
requirement that the frequency is always within ±20 ppm.
Crystal/oscillator must have cumulative accuracy specifications of +15 ppm to provide margin for frequency drift with
aging and temperature.
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22
Reference
LMX9830
Ct1
12pF
Ct2
12pF
LMX9830
9.0 Digital Smart Radio (Continued)
Figure 14.
Frequency Offset with 12 pF//12 pF Capacitors
Figure 15.
Frequency Offset with 10 pF//10 pF Capacitors
23
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LMX9830
9.0 Digital Smart Radio (Continued)
9.7.2 TCXO (Temperature Compensated Crystal
Oscillator)
ration and uses two external capacitors. Table 21 provides
the oscillator’s specifications.
The LMX9830 also can operate with an external TCXO
(Temperature Compensated Crystal Oscillator). The TCXO
signal is directly connected to the CLK+.
In case the 32Khz is placed optionally, it is recommended
to remove C2 and replace C1 with a zero ohm resistor.
1. Input Impedance
The LMX9830 CLK+ pin has in input impedance of 2pF
capacitance in parallel with >400kΩ resistance
32kHz_CLKI
32.768 kHz
9.7.3 Optional 32 kHz Oscillator
32kHz_CLKO
A second oscillator is provided (see Figure 16) that is tuned
to provide optimum performance and low-power consumption while operating with a 32.768 kHz crystal. An external
crystal clock network is required between the 32kHz_CLKI
clock input (pad B13) and the 32kHz_CLKO clock output
(pad C13) signals.The oscillator is built in a Pierce configu-
C2
C1
GND
Figure 16. 32.768 kHz Oscillator
Table 21. 32.768 kHz Oscillator Specifications
Symbol
Parameter
Condition
VDD
Supply Voltage
IDDACT
Supply Current (Active)
f
Nominal Output Frequency
VPPOSC
Oscillating Amplitude
Min
Typ
Max
Unit
1.62
1.8
1.98
V
Duty Cycle
2
µA
32.768
kHz
1.8
V
40
60
%
9.7.4 ESR (Equivalent Series Resistance)
LMX9830 can operate with a wide range of crystals with
different ESR ratings. Reference Table 22 on page 24 and
Figure 17 on page 25 for more details.
Table 22. System Clock Requirements
Parameter
Min
Typ
Max
Unit
External Reference Clock Frequency1
10
13
20
MHz
Frequency Tolerance (over full operating temperature and aging)
-20
+15
+20
ppm
230
Ω
400
mV
±1
ppm per year
Crystal Serial Resistance
External Reference Clock Power Swing, pk to pk
100
Aging
1.
200
Supported frequencies from external oscillator (in MHz): 10.00, 10.368, 12.00, 12.60, 12.80, 13.00, 13.824, 14.40,
15.36, 16.00, 16.20, 16.80, 19.20, 19.68, 19.80
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24
LMX9830
9.0 Digital Smart Radio (Continued)
Figure 17. ESR vs. Load capacitance for the crystal circuit
9.8 ANTENNA MATCHING AND FRONT-END FILTERING
9.9 LOOP FILTER DESIGN
The LMX9830 has an external loop filter which must be
designed for best performance by the end customer. This
section therefore gives some foresight into its design. Refer
also to Loop Filter application note and National’s
Webench on-line design tool for more information.
Figure 18 shows the recommended component layout to
be used between RF output and antenna input. Allows for
versatility in the design such that the match to the antenna
maybe improved and/or the blocking margin increased by
addition of a LC filter. Refer to antenna application note for
further details.
9.9.1 Component Calculations
The following parameters are required for component value
calculation of a third order passive loop filter.
LC filter
φ
Phase Margin: Phase of the open loop
transfer function
Fc
Loop Bandwidth
Fcomp
Comparison Frequency: Phase detector
frequency
KVOC
VCO gain: Sensitivity of the VCO to control
volts
KΦ
Charge Pump gain: Magnitude of the
To Antenna
PI Match
alternating current during lock
Figure 18. Front end Layout
25
FOUT
Maximum RF output frequency
T31
Ratio of the poles T3 to T1 in a 3rd order
filter
ϒ
Gamma optimization parameter
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LMX9830
9.0 Digital Smart Radio (Continued)
The third order loop filter being defined has the following topology. shown in Figure 19..
Figure 19. Third Order Loop filter
N
F out
= --------------- and ω C = 2πF C
F comp
Calculate the poles and zeros. Use exact method to solve for T1 using numerical methods,
φ = tan
–1 
γ
----------------------------------------------
 ω ⋅ T1 ⋅ T1 + T31
C
T3 = T31 × T1
–1
–1
– tan ( ω C ⋅ T1 ) – tan ( ω C ⋅ T1 ⋅ T31 )
γ
T2 = --------------------------------------2
ω C ⋅ ( T1 + T3 )
Calculate the loop filter coefficients,
2
2
1 + ω C ⋅ T2
Kφ ⋅ K vco
- ⋅ ----------------------------------------------------------------------------A0 = ----------------------2
2
2
2
2
ωC ⋅ N
( 1 + ω C ⋅ T1 ) ( 1 + ω C ⋅ T3 )
l
A1 = A0 ⋅ ( T1 + T3 )
A2 = A0 ⋅ T1 ⋅ T3
Summary;
Symbol
n
Description
Units
N counter value
None
Loop Bandwidth
rad/s
T1
Loop filter pole
S
T2
Loop filter zero
S
T3
Loop filter zero
S
A0
Total capacitance
nF
A1
First order loop filter coefficient
nFs
A2
Second order loop filter coefficient
nFs2
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26
LMX9830
9.0 Digital Smart Radio (Continued)
Components can then be calculated from loop filter coefficients
A2
T2 ⋅ A0 – T2 ⋅ A1
C1 = --------2- ⋅ ( 1 + 1 +  --------------------------------------------


A2
T2
2
2
1 ⋅ T2 ⋅ C1 + T2 ⋅ A1 ⋅ C1 – A2 ⋅ A0
C3 = ---------------------------------------------------------------------------------------------2
T2 ⋅ C1 – A2
T2
R2 = ------C2
C2 = A0 – C1 – C3
A2
R3 = -----------------------------C1 ⋅ C3 ⋅ T2
Some typical values for the LMX9830 are:
Phase noise
10Log[Fcomp]
(in-band)
=
PN1Hz
+
20Log[N]
+
Comparison Frequency
13
MHz
Phase Margin
48
Pl rad
Loop bandwidth
100
kHz
T3 over T1 ratio
40
%
Further out from the carrier, the phase noise will be
affected by the loop filter roll-off and hence its bandwidth.
As a rule-of-thumb; ∆ Phase noise = 40Log[ ∆ Fc]
Gamma
1.0
VCO gain
120
MHz per V
Charge pump gain
0.6
mA
Fout
2441
MHz
Where PH1Hz is the PLL normalized noise floor in 1 Hz
resolution bandwidth.
Where ∆ Fc is the relative change in loop BW expressed as
a fraction.
Which give the following component values:
C1
0.17
nF
C2
2.38
nF
C3
0.04
nF
R2
1737
ohms
R3
7025
ohms
For example if the loop bandwidth is reduced from 100kHz
to 50kHz or by one half, then the change in phase noise
will be -12dB. Loop BW in reality should be selected to
meet the lower limit of the modulation deviation, this will
yield the best possible phase noise.
Even further out from the carrier, the phase noise will be
mainly dominated by the VCO noise assuming the crystal
is relatively clean.
Lock-time is dependent on three factors, the loop bandwidth, the maximum frequency jump that the PLL must
make and the final tolerance to which the frequency must
settle. As a rule-of-thumb it is given by:
9.9.2 Phase Noise and Lock-Time Calculations
Phase noise has three sources, the VCO, crystal oscillator
and the rest of the PLL consisting of the phase detector,
dividers, charge pump and loop filter. Assuming the VCO
and crystal are very low noise, it is possible to put down
approximate equations that govern the phase noise of the
PLL.
400
LT = --------- ( 1 – log10 ∆F )
FC
Frequency – tolerance
Where ∆F = ----------------------------------------------------------Frequency – jump
These equations are approximations of the ones used by Webench to calculate phase noise and lock-time.
27
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LMX9830
9.0 Digital Smart Radio (Continued)
9.9.3 Practical Optimization
exceeding or touching the Bluetooth pass limits. These
measurements are taken with component values shown
above
In an example where frequency drift and drift rate can be
improved though loop filter tweaks, consider the results
taken below. The drift rate is 26.1 kHz per 50us and the
maximum drift is 25 kHz for DH1 packets, both of which are
Results below were taken on the same board with three
loop filter values changed. C2 and R2 have been
increased in value and C1 has been reduced. The drift rate
has improved by 13 kHz per 50 µs and the maximum drift
has improved by 10 kHz
The effect of changing these three components is to
reduce the loop bandwidth which reduces the phase noise.
The reduction in this noise level corresponds directly to the
reduction of noise in the payload area where drift is measured. This noise reduction comes at the expense of locktime which can be increased to 120 µs without suffering
any ill effects, however if we continue to reduce the loop
BW further the lock-time will increase such that the PLL
does not have time to lock before data transmission and
the drift will again increase. Before the lock-time goes out
of spec, the modulation index will start to fall since it is
being cut by the reducing loop BW. Therefore a compromise has to be found between lock-time, phase noise and
modulation, which yields best performance.
Note:
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The values shown in the LMX9830 datasheet, are
the best case optimized values that have been
shown to produce the best overall results and are
recommended as a starting point for this design.
Another example of how the loop filter values can affect
frequency drift rate, these results below show the DUT with
maximum drift on mid and high channels failing. Adjusting
the loop bandwidth as shown provides the improvement
required to pass qualification.
28
LMX9830
9.0 Digital Smart Radio (Continued)
Original results:
New results:
29
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LMX9830
10.0 Integrated Firmware (Continued)
The command interpreter listens to commands and links
can be set up. The full command list is supported.
9.9.4 Component Values for NSC Reference Designs
The following is a list of components for the loop filter values used on National reference design, (Serial Dongle)
they have been tweaked and optimized in each case to
yield optimum performance for each case. The values differ slightly from one platform to another due to board
paracitics caused by layout differences.
Platform
C8
C7
C9
R23
R14
LMX9830
Dongle
220pF
2200pF
39pF
3.3k
10k
If connected by another device, the module sends an event
back to the host, where the RFComm port has been connected, and switches to transparent mode.
Default Connections Stored:
If default connections were stored on a previous session,
once the LMX9830 is reset, it will attempt to connect each
device stored within the data RAM three times. The host
will be notified about the success of the link setup via a link
status event.
Non-Automatic Operation
In Non-Automatic Operation, the LMX9830 does not check
the default connections section within the Data RAM. If
connected by another device, it will NOT switch to transparent mode and continue to interpret data sent on the UART.
10.0 Integrated Firmware
The LMX9830 includes the full Bluetooth stack up to
RFComm to support the following profiles:
Transparent Mode
■ GAP (Generic Access Profile)
The LMX9830 supports transparent data communication
from the UART interface to a bluetooth link.
■ SDAP (Service Discovery Application Profile)
If activated, the module does not interpret the commands
on the UART which normally are used to configure and
control the module. The packages don’t need to be formatted as described in Table 25 on page 34. Instead all data
are directly passed through the firmware to the active bluetooth link and the remote device.
■ SPP (Serial Port Profile)
Figure 20 shows the Bluetooth protocol stack with command interpreter interface. The command interpreter offers
a number of different commands to support the functionality given by the different profiles. Execution and interface
timing is handled by the control application.
Transparent mode can only be supported on a point-topoint connection. To leave Transparent mode, the host
must send a UART_BREAK signal to the module
The chip has an internal data area in RAM that includes the
parameters shown in Table 23 on page 31.
Force Master Mode
In Force Master mode tries to act like an Accesspoint for
multiple connections. For this it will only accept the link if a
Master/slave role switch is accepted by the connecting
device. After successful link establishment the LMX9830
will be Master and available for additional incoming links.
On the first incoming link the LMX9830 will switch to transparent depending on the setting for automatic or command
mode. Additional links will only be possible if the device is
not in transparent mode.
Command Interpreter
Control Application
SPP
SDAP
GAP
RFComm
10.1.2 Default Connections
SDP
The LMX9830 supports the storage of up to 3 devices
within its NVS. Those connections can either be connected
after reset or on demand using a specific command.
L2CAP
10.1.3 Event Filter
Link Manager
The LMX9830 uses events or indicators to notify the host
about successful commands or changes at the bluetooth
interface. Depending on the application the LMX9830 can
be configured. The following levels are defined:
Baseband
Figure 20. LMX9830 Software Implementation
■ No Events:
10.1 FEATURES
– The LMX9830 is not reporting any events. Optimized
for passive cable replacement solutions.
10.1.1 Operation Modes
■ Standard LMX9830 events:
On boot-up, the application configures the module following
the parameters in the data area.
– only necessary events will be reported
Automatic Operation
■ All events:
No Default Connections Stored:
– Additional to the standard all changes at the physical
layer will be reported.
In Automatic Operation the module is connectable and discoverable and automatically answers to service requests.
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10.1.4 Default Link Policy
10.1.5 Audio Support
Each Bluetooth Link can be configured to support M/S role
switch, Hold Mode, Sniff Mode and Park Mode. The default
link policy defines the standard setting for incoming and
outgoing connections.
The LMX9830 offers commands to establish and release
synchronous connections (SCO) to support Headset or
Handsfree applications. The firmware supports one active
link with all available package types (HV1, HV2, HV3), routing the audio data between the bluetooth link and the
advanced audio interface. In order to provide the analog
data interface, an external audio codec is required. The
LMX9830 includes a list of codecs which can be used.
Table 23. Operation Parameters Stored in LMX9830
Parameter
Default Value
Description
BDADDR
(To be requested from IEEE)
Bluetooth device address
Local Name
Serial port device
Friendly Name
PinCode
0000
Bluetooth PinCode
Operation Mode
Automatic ON
Automatic mode ON or OFF
Default Connections
0
Up to seven default devices to connect to
SDP Database
1 SPP entry:
Name: COM1
Authentication and encryption enabled
Service discovery database, control for supported profiles
UART Speed
9600
Sets the speed of the physical UART interface to the
host
UART Settings
1 Stop bit, parity disabled
Parity and stop bits on the hardware UART interface
Ports to Open
0000 0001
Defines the RFComm ports to open
Link Keys
No link keys
Link keys for paired devices
Security Mode
2
Security mode
Page Scan Mode
Connectable
Connectable/Not connectable for other devices
Inquiry Scan Mode
Discoverable
Discoverable/Not Discoverable/Limited Discoverable
for other devices
Default Link Policy
All modes allowed
Configures modes allowed for incoming or outgoing
connections (Role switch, Hold mode, Sniff mode...)
Default Link Timeout
20 seconds
The Default Link Timeout configures the timeout, after
which the link is assumed lost, if no packages have
been received from the remote device.
Event Filter
Standard LMX9830 events reported
Defines the level of reporting on the UART
- no events
- standard events
- standard including ACL link events
Default Audio Settings
none
Configures the settings for the external codec and the
air format.
• Codecs:
— Motorola MC145483 / Winbond W681360
— OKI MSM7717 / Winbond W681310
— PCM Slave
• Airformat:
— CVSD
— µ-Law
— A-Law
31
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LMX9830
10.0 Integrated Firmware (Continued)
LMX9830
11.0 Low Power Modes
The LMX9830 supports different Low Power Modes to
reduce power in different operating situations. The modular
structure of the LMX9830 allows the firmware to power
down unused modules.
mand “Disable Transport Layer” is used. Thus only the
Host side command interface can disable the transport
layer. Enabling the transport layer is controlled by the HW
Wakeup signalling. This can be done from either the Host
or the LMX9830. See also “LMX9830 Software User’s
Guide” for detailed information on timing and implementation requirements.
The Low power modes have influence on:
■ UART transport layer
– enabling or disabling the interface
Table 24. Power Mode activity
■ Bluetooth Baseband activity
Power
Mode
– firmware disables LLC and Radio if possible
11.1 POWER MODES
The following LMX9830 power modes, which depend on
the activity level of the UART transport layer and the radio
activity are defined:
The radio activity level mainly depends on application
requirements and is defined by standard bluetooth operations like inquiry/page scanning or an active link.
A remote device establishing or disconnecting a link may
also indirectly change the radio activity level.
UART
activity
Radio
activity
Reference
Clock
PM0
OFF
OFF
none
PM1
ON
OFF
Main Clock
PM2
OFF
Scanning
Main Clock /
32.768khz
PM3
ON
Scanning
Main Clock
PM4
OFF
SPP Link
Main Clock
PM5
ON
SPP Link
Main Clock
The UART transport layer by default is enabled on device
power up. In order to disable the transport layer the comBluetooth Radio Activity
Page / Inquiry Scanning
No radio activity
Active Link(s)
All Links Released
Incoming Link
UART Disabled
Wake-up Enabled
PM2
PM0
Disable TL
Scanning Disabled
Disable TL
TL Enabled
Link Established
Scanning Enabled
PM1
PM4
Disable TL
TL Enabled
TL Enabled
UART Enabled
Wake-up Disabled
All Links released
PM3
All Links released
PM5
Link Established
All Links released
Figure 21. Transition between different Hardware Power Modes
11.2 ENABLING AND DISABLING UART
TRANSPORT
consumption. Afterwards both devices, host and LMX9830
are able to shut down their UART interfaces.
In order to save system connections the UART interface is
reconfigured to hardware wakeup functionality. For a
detailed timing and command functionality please see also
the “LMX9830 Software User’s Guide”.
11.2.1 Hardware Wake up functionality
In certain usage scenarios the host is able to switch off the
transport layer of the LMX9830 in order to reduce power
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32
LMX9830
11.0 Low Power Modes (Continued)
The interface between host and LMX9830 is defined as
described in Figure 22.
Host
LMX9830
RTS#
CTS#
TX
RX
RTS#
CTS#
TX
RX
Figure 22. UART NULL modem connection
11.2.2 Disabling the UART transport layer
The Host can disable the UART transport layer by sending
the “Disable Transport Layer” Command. The LMX9830
will empty its buffers, send the confirmation event and disable its UART interface. Afterwards the UART interface will
be reconfigured to wake up on a falling edge of the CTS
pin.
11.2.3 LMX9830 enabling the UART interface
As the Transport Layer can be disabled in any situation the
LMX9830 must first make sure the transport layer is
enabled before sending data to the host. Possible scenarios can be incoming data or incoming link indicators. If the
UART is not enabled the LMX9830 assumes that the Host
is sleeping and waking it up by activating RTS. To be able
to react on that Wake up, the host has to monitor the CTS
pin.
As soon as the host activates its RTS pin, the LMX9830 will
first send a confirmation event and then start to transmit
the events.
11.2.4 Enabling the UART transport layer from the host
If the host needs to send data or commands to the
LMX9830 while the UART Transport Layer is disabled it
must first assume that the LMX9830 is sleeping and wake it
up using its RTS signal.
When the LMX9830 detects the Wake-Up signal it activates the UART HW and acknowledges the Wake-Up signal by settings its RTS. Additionally the Wake up will be
confirmed by a confirmation event. When the Host has
received this “Transport Layer Enabled” event, the
LMX9830 is ready to receive commands.
33
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LMX9830
12.0 Command Interface
The LMX9830 offers Bluetooth functionality in either a self
contained slave functionality or over a simple command
interface. The interface is listening on the UART interface.
12.1.2 Packet Type ID
This byte identifies the type of packet. See Table 26 for
details.
The following sections describe the protocol transported on
the UART interface between the LMX9830 and the host in
command mode (see Figure 23). In Transparent mode, no
data framing is necessary and the device does not listen
for commands.
12.1.3 Opcode
The opcode identifies the command to execute. The
opcode values can be found within the “LMX9830 Software
User’s Guide” included within the LMX9830 Evaluation
Board.
12.1 FRAMING
The connection is considered “Error free”. But for packet
recognition and synchronization, some framing is used.
12.1.4 Data Length
Number of bytes in the Packet Data field. The maximum
size is defined with 333 data bytes per packet.
All packets sent in both directions are constructed per the
model shown in Table 25.
12.1.5 Checksum:
12.1.1 Start and End Delimiter
This is a simple Block Check Character (BCC) checksum of
the bytes “Packet type”, “Opcode” and “Data Length”. The
BCC checksum is calculated as low byte of the sum of all
bytes (e.g., if the sum of all bytes is 0x3724, the checksum
is 0x24).
The “STX” char is used as start delimiter: STX = 0x02. ETX
= 0x03 is used as end delimiter.
Existing device
without Bluetooth™
capabilities
LMX9830
UART
UART
Figure 23. Bluetooth Functionality
.
Table 25. Package Framing
Start
Delimiter
Packet
Type ID
Opcode
Data Length
Checksum
Packet Data
End
Delimiter
1 Byte
1 Byte
1 Byte
2 Bytes
1 Byte
<Data Length> Bytes
1 Byte
- - - - - - - - - - - - - Checksum - - - - - - - - - - - - -
Table 26. Packet Type Identification
ID
Direction
Description
0x52
REQUEST
A request sent to the Bluetooth module.
‘R’
(REQ)
All requests are answered by exactly one confirm.
0x43
Confirm
The Bluetooth modules confirm to a request.
‘C’
(CFM)
All requests are answered by exactly one confirm.
0x69
Indication
Information sent from the Bluetooth module that is not a direct confirm to a request.
‘i’
(IND)
Indicating status changes, incoming links, or unrequested events.
0x72
Response
An optional response to an indication.
‘r’
(RES)
This is used to respond to some type of indication message.
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34
LMX9830
12.0 Command Interface (Continued)
12.2 COMMAND SET OVERVIEW
■ Set up and handle links
The LMX9830 has a well defined command set to:
Tables 27 through 37 show the actual command set and
the events coming back from the device. A full documented
description of the commands can be found in the
“LMX9830 Software User’s Guide”.
■ Configure the device:
– Hardware settings
– Local Bluetooth parameters
– Service database
NOTE: For standard Bluetooth operation only commands
from Table 27 through Table 29 will be used. Most of the
remaining commands are for configuration purposes only..
Table 27. Device Discovery
Command
Event
Description
Inquiry
Inquiry Complete
Search for devices
Device Found
Lists BDADDR and class of device
Remote Device Name Confirm
Get name of remote device
Remote Device Name
Table 28. SDAP Client Commands
Command
Event
Description
SDAP Connect
SDAP Connect Confirm
Create an SDP connection to remote device
SDAP Disconnect
SDAP Disconnect Confirm
Disconnect an active SDAP link
Connection Lost
Notification for lost SDAP link
SDAP Service Browse
Service Browse Confirm
Get the services of the remote device
SDAP Service Search
SDAP Service Search Confirm
Search a specific service on a remote device
SDAP Attribute Request
SDAP Attribute Request Confirm
Searches for services with specific attributes
Table 29. SPP Link Establishment
Command
Event
Description
Establish SPP Link
Establishing SPP Link Confirm
Initiates link establishment to a remote device
Link Established
Link successfully established
Incoming Link
A remote device established a link to the local
device
Set Link Timeout
Set Link Timeout Confirm
Confirms the Supervision Timeout for the existing Link
Get Link Timeout
Get Link Timeout Confirm
Get the Supervision Timeout for the existing
Link
Release SPP Link
Release SPP Link Confirm
Initiate release of SPP link
SPP Send Data
SPP Send Data Confirm
Send data to specific SPP port
Incoming Data
Incoming data from remote device
Transparent Mode
Transparent Mode Confirm
Switch to Transparent mode on the UART
Table 30. Storing Default Connections
Command
Event
Description
Connect Default Connection
Connect Default Connection Confirm
Connects to either one or all stored default
connections
Store Default Connection
Store Default Connection Confirm
Store device as default connection
Get list of Default Connections
List of Default Devices
Delete Default Connections
Delete Default Connections Confirm
35
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LMX9830
12.0 Command Interface (Continued)
Table 31. Bluetooth Low Power Modes
Command
Event
Description
Set Default Link Policy
Set Default Link Policy Confirm
Defines the link policy used for any incoming or
outgoing link.
Get Default Link Policy
Get Default Link Policy Confirm
Returns the stored default link policy
Set Link Policy
Set Link Policy Confirm
Defines the modes allowed for a specific link
Get Link Policy
Get Link Policy Confirm
Returns the actual link policy for the link
Enter Sniff Mode
Enter Sniff Mode Confirm
Exit Sniff Mode
Exit Sniff Mode Confirm
Enter Hold Mode
Enter Hold Mode Confirm
Power Save Mode Changed
Remote device changed power save mode on
the link
Table 32. Audio Control Commands
Command
Event
Description
Establish SCO Link
Establish SCO Link Confirm
Establish SCO Link on existing RFComm
Link
SCO Link Established Indicator
A remote device has established a SCO link
to the local device
Release SCO Link Confirm
Release SCO Link
SCO Link Released Indicator
SCO Link has been released
Change SCO Packet Type Confirm
Changes Packet Type for existing SCO link
SCO Packet Type changed indicator
SCO Packet Type has been changed
Set Audio Settings
Set Audio Settings Confirm
Set Audio Settings for existing Link
Get Audio Settings
Get Audio Settings Confirm
Get Audio Settings for existing Link
Set Volume
Set Volume Confirm
Configure the volume
Get Volume
Get Volume Confirm
Get current volume setting
Mute
Mute Confirm
Mutes the microphone input
Release SCO Link
Change SCO Packet Type
Table 33. Wake Up Functionality
Command
Event
Description
Disable Transport Layer
Transport Layer Enabled
Disabling the UART Transport Layer and
activates the Hardware Wakeup function
Table 34. SPP Port Configuration and Status
Command
Event
Description
Set Port Config
Set Port Config Confirm
Set port setting for the “virtual” serial port link
over the air
Get Port Config
Get Port Config Confirm
Read the actual port settings for a “virtual”
serial port
Port Config Changed
Notification if port settings were changed from
remote device
SPP Get Port Status
SPP Get Port Status Confirm
Returns status of DTR, RTS (for the active RFComm link)
SPP Port Set DTR
SPP Port Set DTR Confirm
Sets the DTR bit on the specified link
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36
LMX9830
12.0 Command Interface (Continued)
Table 34. SPP Port Configuration and Status (Continued)
Command
Event
Description
SPP Port Set RTS
SPP Port Set RTS Confirm
Sets the RTS bit on the specified link
SPP Port BREAK
SPP Port BREAK
Indicates that the host has detected a break
SPP Port Overrun Error
SPP Port Overrun Error Confirm
Used to indicate that the host has detected an
overrun error
SPP Port Parity Error
SPP Port Parity Error Confirm
Host has detected a parity error
SPP Port Framing Error
SPP Port Framing Error Confirm
Host has detected a framing error
SPP Port Status Changed
Indicates that remote device has changed one
of the port status bits
Table 35. Local Bluetooth Settings
Command
Event
Description
Read Local Name
Read Local Name Confirm
Read actual friendly name of the device
Write Local Name
Write Local Name Confirm
Set the friendly name of the device
Read Local BDADDR
Read Local BDADDR Confirm
Change Local BDADDR
Change Local BDADDR Confirm
Store Class of Device
Store Class of Device Confirm
Set Scan Mode
Set Scan Mode Confirm
Change mode for discoverability and
connectability
Set Scan Mode Indication
Reports end of Automatic limited
discoverable mode
Get Fixed Pin
Get Fixed Pin Confirm
Reads current PinCode stored within the
device
Set Fixed Pin
Set Fixed Pin Confirm
Set the local PinCode
PIN request
a PIN code is requested during authentication of
an ACL link
Get Security Mode
Get Security Mode Confirm
Get actual Security mode
Set Security Mode
Set Security Mode Confirm
Configure Security mode for local device
(default 2)
Remove Pairing
Remove Pairing Confirm
Remove pairing with a remote device
List Paired Devices
List of Paired Devices
Get list of paired devices stored in the LMX9830
data memory
Set Default Link Timeout
Set Default Link Timeout Confirm
Store default link supervision timeout
Get Default Link Timeout
Get Default Link Timeout Confirm
Get stored default link supervision timeout
Force Master Role
Force Master Role Confirm
Enables/Disables the request for master role at
incoming connections
Note:
The BDADDR has to be obtained from
the IEEE organization. See http://standarts.ieee.org/regauth/oui/
Table 36. Local Service Database Configuration
Command
Event
Description
Store generic SDP Record
Store SDP Record Confirm
Create a new service record within the service database
Enable SDP Record
Enable SDP Record Confirm
Enable or disable SDP records
Delete All SDP Records
Delete All SDP Records Confirm
Ports to Open
Ports to Open Confirmed
Specify the RFComm Ports to open on startup
37
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LMX9830
12.0 Command Interface (Continued)
Table 37. Local Hardware Commands
Command
Event
Description
Set Default Audio Settings
Set Default Audio Settings Confirm
Configure Default Settings for Audio Codec and
Air Format, stored in NVS
Get Default Audio Settings
Get Default Audio Settings Confirm
Get stored Default Audio Settings
Set Event Filter
Set Event Filter Confirm
Configures the reporting level of the
command interface
Get Event Filter
Get Event Filter Confirm
Get the status of the reporting level
Read RSSI
Read RSSI Confirm
Returns an indicator for the incoming signal
strength
Change UART Speed
Change UART Speed Confirm
Set specific UART speed; needs proper ISEL
pin setting
Change UART Settings
Change UART Settings Confirm
Change configuration for parity and stop bits
Test Mode
Test Mode Confirm
Enable Bluetooth, EMI test, or local loopback
Restore Factory Settings
Restore Factory Settings Confirm
Reset
Dongle Ready
Soft reset
Firmware Upgrade
Stops the bluetooth firmware and executes the
In-system-programming code
Set Clock Frequency
Set Clock Frequency Confirm
Write Clock Frequency setting in the NVS
Get Clock Frequency
Get Clock Frequency Confirm
Read Clock Frequency setting from the NVS
Set PCM Slave Configuration
Set PCM Slave Configuration Confirm
Write the PCM Slave Configuration in the NVS
Write ROM Patch
Write ROM Patch Confirm
Store ROM Patch in the SimplyBlue module
Read Memory
Read Memory Confirm
Read from the internal RAM
Write Memory
Write Memory Confirm
Write to the internal RAM
Read NVS
Read NVS Confirm
Read from the NVS (EEPROM)
Write NVS
Write NVS Confirm
Write to the NVS (EEPROM)
Table 38. Initialization Commands
Command
Event
Description
Set Clock and Baudrate
Set Clock and Baudrate Confirm
Write Baseband frequency and Baudrate used
Enter Bluetooth Mode
Enter Bluetooth Mode Confirm
Request SimplyBlue module to enter BT mode
Set Clock and Baudrate
Set Clock and Baudrate Confirm
Write Baseband frequency and Baudrate used
Table 39. GPIO Control commands
Command
Event
Description
Set GPIO WPU
Set GPIO WPU Confirm
Enable/Disable weak pull up resistor on GPIOs
Get GPIO Input State
Get GPIO Input States Confirm
Read the status of the GPIOs
Set GPIO Direction
Set GPIO Direction Confirm
Set the GPIOs direction (Input, Ouput)
Set GPIO Output High
Set GPIO Output High Confirm
Set GPIOs Output to logical High
Set GPIO Output Low
Set GPIO Output Low Confirm
Set GPIOs Output to logical Low
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38
13.1 SCENARIO 1: POINT-TO-POINT
CONNECTION
The SPP conformance of the LMX9830 allows any device
using the SPP to connect to the LMX9830.
LMX9830 acts only as slave, no further configuration is
required.
Because of switching to Transparent automatically, the controller has no need for an additional protocol layer; data is
sent raw to the other Bluetooth device.
Example: Sensor with LMX9830; hand-held device with
standard Bluetooth option.
On default, a PinCode is requested to block unallowed targeting.
Air Interface
Standard Device
with Bluetooth
Sensor Device
UART
Inquiry Request
Search for Devices
Inquiry Response
SDP Link Request
Get Remote Services
SDP Link Accept
Service Browse
Service Response
Release SDP Link
Release Confirm
Connected
on Port L
SPP Link Request
Establish SPP Link
SPP Link Accept
Link Established
Transparent Mode
Raw Data
Microcontroller
LMX9830
The client software only
shows high level functions
No Bluetooth™ commands necessary
only “connected” event indicated to controller
Figure 24. Point-to-Point Connection
39
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LMX9830
13.0 Usage Scenarios
LMX9830
13.0 Usage Scenarios (Continued)
13.2 SCENARIO 2: AUTOMATIC POINT-TO-POINT
CONNECTION
If step 5 is executed, the stored default device is connected
(step 4) after reset (in Automatic mode only) or by sending
the command “Connect to Default Device”. The command
can be sent to the device at any time.
LMX9830 at both sides.
Example: Serial Cable Replacement.
If step 6 is left out, the microcontroller has to use the command “Send Data” instead of sending data directly to the
module.
Device #1 controls the link setup with a few commands as
described.
Serial Device #1
Serial Device #2
1. Devices in Range?
Air
Interface
Inquiry
Inquiry
Inquiry Result
Inquiry Result
Inquiry Response
Establish SDP Link
Establish SDP Link
SDP Link Request
SDP Link Established
SDP Link Established
SDP Link Accept
Service Browse
Service Browse
Service Browse
RFComm Port = R
Browse Result
Service Response
Release SDP Link
Release SDP Link
Release SDP Link
SDP Link Released
SDP Link Released
Release Confirm
Establish SPP Link
to Port R1 on Port L2
Establish SPP Link
to Port R on Port L
SPP Link Request
Connected on Port L
Link Established
SPP Link Accept
Inquiry Request
2. Choose the Device
3. Which COM Port is
available?
4. Create SPP Link
5. Connect on Default
(Optional)
Connected
on Port R
Transparent Mode
Store Default Device
Storing Default Device
Device Stored
Device Stored
6. Switch to
Transparent
Transparent Mode
Transparent Mode
Raw Data
Microcontroller
LMX9830
LMX9830
Bluetooth™ device controls link with
a few commands
Microcontroller
No Bluetooth™ commands necessary;
only “connected” event indicated to controller
1. Port R indicates the remote RFComm channel to connect to. Usually the result of the SDP request.
2. Port L indicates the Local RFComm channel used for that connection.
Figure 25. Automatic Point-to-Point Connection
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40
13.3 SCENARIO 3: POINT-TO-MULTIPOINT CONNECTION
Serial Device #1 is acting as master for both devices. As
the host has to decide to or from which device data is coming from, data must be sent using the “Send data command”. If the device receives data from the other devices, it
is packaged into an event called “Incoming data event”.
The event includes the device related port number.
LMX9830 acts as master for several slaves.
Example: Two sensors with LMX9830; one hand-held
device with implemented LMX9830.
Serial Devices #2 and #3 establish the link automatically as
soon as they are contacted by another device. No controller interaction is necessary for setting up the Bluetooth link.
Both switch automatically into Transparent mode. The host
sends raw data over the UART.
Serial Device #1
If necessary, a link configuration can be stored as default in
the master Serial Device #1 to enable the automatic reconnect after reset, power-up, or by sending the “connect
default connection” command.
Air
Interface
Serial Device #2
Connect to Device #2
see Scenario 2
Connect to Device #2
see Scenario 2
Connection Request
Link Established
on Port L1
Link Established
Automatic Link Setup
Connected
on Port L
Transparent Mode
Send Data to Port L1
Send Data Command
Data Received
from Port L1
Receive Data Event
Raw Data
LMX9830
Microcontroller
Serial Device #3
Connect to Device #3
see Scenario 2
Connect to Device #3
see Scenario 2
Connection Request
Link Established
on Port L2
Link Established
Automatic Link Setup
Connected
on Port L
Transparent Mode
Send Data to Port L2
Send Data Command
Data Received
from Port L2
Receive Data Event
Raw Data
Microcontroller
LMX9830
LMX9830
Microcontroller
Figure 26. Point-to-Multipoint Connection
41
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LMX9830
13.0 Usage Scenarios (Continued)
LMX9830
14.0 Reference design
Note: For a schematic including an RS232 communication
with the host, please refer to the “LMX9830DONGLE
designer guide”.
www.national.com
Recommended that a 4 component T-PI pad be used
between RF out and antenna input. Allows for versatility in
the design such that the match to the antenna maybe
improved and/or blocking margin increased by adding a LC
filter.
42
The LMX9830 bumps are designed to melt as part of the
Surface Mount Assembly (SMA) process. In order to
ensure reflow of all solder bumps and maximum solder
joint reliability while minimizing damage to the package,
recommended reflow profiles should be used.
Table 40, Table 41 and Figure 27 on page 44 provide the
soldering details required to properly solder the LMX9830 to
standard PCBs. The illustration serves only as a guide and
National is not liable if a selected profile does not work.
See IPC/JEDEC J-STD-020C, July 2004 for more information.
Table 40. Soldering Details
Parameter
Value
PCB Land Pad Diameter
13 mil
PCB Solder Mask Opening
19 mil
PCB Finish (HASL details)
Defined by customer or manufacturing facility
Stencil Aperture
17 mil
Stencil Thickness
5 mil
Solder Paste Used
Defined by customer or manufacturing facility
Flux Cleaning Process
Defined by customer or manufacturing facility
Reflow Profiles
See Figure 27 on page 44
Table 41. Classification Reflow Profiles 1,2
Profile Feature
NOPB Assembly
Average Ramp-Up Rate (TsMAX to Tp)
3°C/second maximum
Preheat:
Temperature Min (TsMIN)
Temperature Max (TsMAX)
Time (tsMIN to tsMAX)
150°C
200°C
60–180 seconds
Time maintained above:
Temperature (TL)
Time (tL)
217°C
60–150 seconds
Peak/Classification Temperature (Tp)
260 + 0°C
Time within 5°C of actual Peak Temperature (tp)
20–40 seconds
Ramp-Down Rate
6°C/second maximum
Time 25 °C to Peak Temperature
8 minutes maximum
Reflow Profiles
1.
2.
See Figure 27
See IPC/JEDEC J-STD-020C, July 2004.
All temperatures refer to the top side of the package, measured on the package body surface.
43
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LMX9830
15.0 Soldering
LMX9830
15.0 Soldering (Continued)
Figure 27. Typical Reflow Profiles
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44
This section is a report of the revision/creation process of
the datasheet for the LMX9830. Table 42 provides the
stages/definitions of the datasheet. Table 43 lists the revi-
sion history and Table 44 lists the specific edits to create
the current revision.
Table 42. Documentation Status Definitions
Datasheet Status
Product Status
Definition
Advance Information
Formative or in Design
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data. Supplementary data will
be published at a later date. National Semiconductor Corporation reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.S
No Identification Noted
Full production
This datasheet contains final specifications. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible
product.
Obsolete
Not in Production
This datasheet contains specifications on a product that has been
discontinued by National Semiconductor Corporation. The
datasheet is printed for reference information only.
Table 43. Revision History
Revision #
(PDF Date)
Revisions / Comments
0.1(November
2004)
Advanced datasheet revised to include new radio and additional functionality. Several edits have
been made to functional, performance, and electrical details.
0.2(July 2005)
Preliminary version.
0.3(August 2005)
1.0 (October
2005)
Preliminary version. Updated reference schematic.
Final revision. Minor changes to match the final version.
1.0 December
2005
Section added to digital smart radio and reference design, out of band rejection using front-end components. Also to digital smart radio, section on loop filter design added.
1.1 January 2006
Updated Sections for front end components and Loop Filter sections and formatted for final release
Table 44. Edits to Current Revision
Section
All
Revisions / Comments
• Misc corrections and typos
• Electrical characteristics update.
• Put back 32 KHz osc supported. Updated 32 khz schematic in Digital Smart Radio section.
• Added quality standard compliance.
• Updated BT specification to latest revision.
General description
• Added RoHS reference.
Connection diagram
and Pad description
• Changed VREGIN to VCC in every definition.
General specifications
• Updated current consumption to match latest measurements on Mesa 1.1
Autobaudrate description
• Corrected RTS to CTS.
Power on reset
• Timing “Power to Reset” Parameter names changed
Schematics
• Updated LMX9830 DONGLE reference design schematic.
45
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LMX9830
16.0 Datasheet Revision History
17.0 Physical Dimensions inches (millimeters) unless otherwise noted
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