User's Guide SLLU187 – November 2013 TLK10022 and TLK10081 Evaluation Module (EVM) This user’s guide describes the usage and construction of the TLK10022 and TLK10081 evaluation modules (EVM). This document provides guidance on proper use by showing some device configurations and test modes. In addition, design, layout, and schematic information is provided to the customer. Information in this guide can be used to assist the customer in choosing the optimal design methods and materials in designing a complete system. 22 23 ON LOW JMP100 C80 GND U42 12C_LS_EN U41 REF_SEL SI_MODE0 SI_MODE1 OUTB0P / OUTA4P / CLKB0N OUTB0N / OUTA4N / CLKB0P J5 INB0N / INA4N / CLKA3P GND JMP61 ON 1 2 3 4 LOW HIGH JMP62 JMP47 JTAG GND MDIOV 2p5V 3p3V USB DONGLE K3 JMP103 SW16 J4 MDC OUTPUT K1 MDIO K4 K2 MDC INPUT MDIO D110 PRI_REF_IN_P INB0P / INA4P / CLKA3N JMP50 J8 C249 R777 C672 C673 R684 OUTB3N / OUTA7N / CLKB3P J16 5 R1 J3 R1 JMP77 D100 I2C J73 A12 CLKOUTBp J48 CLKOUTBn J7 C247 HSRXBn J5 R581 HSRXBp J6 HSTXBp JMP104 R687R686 R685 J2 JTAG_V 3p3V SFP+ TX_DIS JMP36 MOD DETECT CLKOUTAp A1 U1 D48 JMP105 J46 CLKOUTAn M1 M12 REF CLK0p REFCLK0n J42 HSTXBn 1 2 SW19 EN D102 D103 R582 STATUS 1/PIN0 PRI_REF (30.72MHZ) (31.25MHZ) SEC_REF PLL_LOCK (STATUS 0) CLKB SW18 D101 ON SPI_MISO/PIN2 SPI_MOSI/PIN1 SPI_LE1/PIN3 SPI_LE2 PRI_REF_IN_N J104 SPI_CLK/PIN4 R781R780 R785 J45 REFCLK1p REF CLK1n U110 D107 RST/PWR D106 RST/PWR D108 U112 D109 CLK RST/ SW15 PWR J41 J102 CLKA DIS D111 R712 C693 R783 J47 RST RST BTN J72 JMP42 PDN PDN SW13 U108 J43 D104 D105 SW14 SYNCN J44 SYNCN CLK SYNCN C619 C671 C683 R704 R713 C682 R784 1 2 3 4 5 6 7 8 9 10 U64 J100 SW10 D11 D10 GND CLK PDN C127 CLK BUFFER INPUT SEC_OSC C674 C675 C676 C677 R703 C684 R782 C692 HIGH R630 R629 R631 R633 C120 C119 C121 1p0V_D2 REG 1p0V_A1 REG + C111 C110 C109 3p3V REG MAIN RESET C108 C118 C97 1p8V REG C43 U100 U115 R696 R697 R695 R698 + + VOLTAGE MONITOR DONGLE C84 C32 1p5V REG C29 C46 U16 D2 D1 D13 1p0V_D1 REG C94 1p0V_A2 REG C95 C98 5V D28 DIS + + P26 TLK10xxxEVM MOTHER BOARD REV NA 6566789 EN REGULATOR DISABLE P1 C139 1p5/8V BJ 1p5V 5V PLUG JMP35 JMP41 C138 +5V P14 GND 5V D9 D4 D6 D5 3p3V_CLK REG + C618 C616 C617 C681 C680 C679 C678 PRI_OSC HIGH STATUS 1 EXT SMA SEC_OSC CLK GEN J103 J101 C622 C623 PRI_OSC INT2 C620 C621 ON RESET2 C628 C629 1 2 3 4 RESET1 INT1 C625 R689 R691 U105 SCL SDA C624 C626 C627 R694R693 2p5V JMP102 TLK 10002 TLK 10232 R690 R692 D51 TX_FAULT R688 D52 R549 C654 C670 RX_LOS D49 C74 U24 C667 C668 R553 D50 C71 U114 TX DIS C128 LOW U92 GND TX DIS R548 R546 C99 C130 C129 J13 J15 J17 D4 USB RST RST SUSPND ONLINE OUTB1P / OUTA5P / CLKB1N OUTB2P / OUTA6P / CLKB2N LS_OK_IN_B LS_OK_OUT_B GND J18 OUTB3P / OUTA7P / CLKB3N CHA_CLKOUTN / CLKA1N_IN JMP3 GND LS_OK_IN_A LS_OK_OUT_A 7 6 R1 R3 5 Q1 R62 R63 R64 R65 R50 R51 MDC MDIO J37 R3 GND SW2 INB3N / INA7N / CLKA0P CHB_CLKOUTN / CLKB1P_IN JMP1 C16 C15 R539 INB3P / INA7P / CLKA0N J14 8 R78 TCK TMS TDI U40 INB2N / INA6N / CLKA1P OUTB2N / OUTA6N / CLKB2P J12 R1 R47 R46 R45 R44 R43 R42 C12 R57 R56 R93 R96 R55 R54 R53 R52 GND TDO D15 D12 LS_OK OUT_B TRST C124 C123 D14 J8 6 R58 R59 C13 R60 R61 SW1 LS_OK OUT_A C100 D11 RESET D10 RESET C101 J11 INB1N / INA5N / CLKA2P OUTB1N / OUTA5N / CLKB1P R1 ON R66 R74 R75 R67 R68 R69 R70 R71 R72 R73 R49 R48 U4 PRTAD4 PRTAD3 PRTAD2 PRTAD1 C140 C125 0 D21 R58 D20 6 D16 D19 R56 D12 D13 J7 R41 C4 U2 LOSB 2 R2 C3 ECS D 12.0 MHzR92RST LOSA 1 R1 R1 D3 INB2P / INA6P / CLKA1N J10 R5 R6 D2 PRBS PASS J6 J9 D1 GND PRTAD0 ON 1 2 INB1P / INA5P / CLKA2N J1 5 SW12 U12 C113 LS_OKINB R56 JMP101 1p8V LS_OKINA 9 IN R57 OUT D3 C89 C115 C114 D31 C91 C90 U22 D18 8 D17 6 D16 R57 D15 R57 8 D14 0 R699 R701R700 R56 R702 R57 C4 JN C17 U11 C8 7 U8 U20 C7 C15 U23 AMUXA CLK_VCC 9 AMUXB SW17 CLK_DVDD PRBS PASS 3P3V_CLK 3P3V 1P8V 1P5V 1P0V_D2 1P0V_D1 1P0V_A2 1P0V_A1 CLK_VDD_IN LOSB C67 VDDRB_HS CLK_VDD_OUTB R56 GND C93 C604 U101 C64 D8 CLK_VDD_OUTA 4 C10 D23 CLK_VDD_PLL R57 C14 3P3V_CLK CLK_VDD_PLLA C86 U29 C9 1 C85 D7 U26 C6 R56 7 LOSA D22 U17 C5 R57 5 JMP48 D30 C600 U41 C13 C107 U38 C12 C24 U14 U10 U35 C11 VDDRA_LS VDDRA_HS VDDRB_LS C22 D25 2 D27 D24 R57 U32 VDDO D29 D26 C117 VDDD DVDD 1p8V D28 C611 VDDT 1p5V R57 U102 + C607 C19 3 C87 U44 C1 R57 PDTRXA PDTRXB ST/GPI1 U5 C3 R628 U8 C2 VDDA R627 U2 1p0V_D2 R625 1p0V_D1 R626 +5V Q100 1p5V 1p0V_A1 1p0V_A2 R632 JMP1 MODE/REFCLK_SEL PRBSEN TESTEN GPIO MDIO_B2B_RLY MDIO_CON_RLY I2C_GPIO_ADDR 1p8V + SW11 2p5V ON VOLTAGE MONITOR 6568778 REV NA 3p3V GND 1 2 3 4 5 6 7 8 C18 C15 C16 TLK10xxx C17 5p0V R57 J19 J36 JMP2 CHB_CLKOUTP / CLKB1N_IN CHA_CLKOUTP / CLKA1P_IN C14 R91 R90 OUTA2N J27 R17 R19 R21 R23 R25 R27 R29 R31 R33 R35 R37 R39 R7 R9 R11 R13 R1 C1 J20 9 OUTA1N J31 INA0P J33 OUTA0N J35 J21 4 0 R2 R1 R3 3 R3 J30 J32 J34 INA3P INA3N J26 J22 J23 OUTA2P OUTA1P INA2P INA1P R3 R2 9 3 OUTA3N 0 R2 OUTA0P TLK10xxx SMA BREAKOUT BRD 6568779 REV N/A J29 4 R2 OUTA3P J25 INA0N J24 J28 INA2N INA1N WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at own expense will be required to take whatever measures may be required to correct this interference. Contents SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 1 www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Introduction .................................................................................................................. 4 EVM PCB and High-Speed Design Considerations .................................................................... 4 TLK10022/81 EVM Kit Contents .......................................................................................... 5 Power ......................................................................................................................... 5 Voltage Monitoring Board and Power Rail LEDs ....................................................................... 6 Control and Output Status Signals ....................................................................................... 6 MDIO ......................................................................................................................... 6 JTAG .......................................................................................................................... 7 Reset ......................................................................................................................... 7 Test and Setup Configurations ............................................................................................ 8 TLK10xxx EVM Motherboard Schematics ............................................................................. 16 TLK10xxx EVM Motherboard Layout ................................................................................... 31 TLK10xxx EVM SMA Breakout Board Schematics ................................................................... 42 TLK10xxx EVM SMA Breakout Board Layout ......................................................................... 46 TLK10xxx EVM Voltage Monitor Board Schematics .................................................................. 51 TLK10xxx EVM Voltage Monitor Board Layout, Top Signal Layer .................................................. 61 TLK10xxx EVM USB Dongle Board Schematics ...................................................................... 66 TLK10xxx EVM USB Dongle Board Layout ............................................................................ 68 List of Figures 1 TLK10xxx EVM Motherboard .............................................................................................. 9 2 TLK10xxx EVM SMA Breakout Board .................................................................................. 10 3 TLK10xxx EVM Voltage Monitor Board................................................................................. 11 4 TLK10xxx EVM USB Dongle Board..................................................................................... 12 5 TLK10xxx EVM Motherboard and SMA Breakout Board for Channels A/B ....................................... 13 6 TLK10xxx EVM Motherboard and SMA Breakout Board for Clock Channels ..................................... 14 7 TLK10xxx EVM Board Features ......................................................................................... 15 8 TLK10xxx EVM Schematic, Sheet 1 of 15 Cover Page and Index ................................................. 16 9 TLK10xxx EVM Schematic, Sheet 2 of 15 1p0V Regulators ........................................................ 17 10 TLK10xxx EVM Schematic, Sheet 3 of 15 1p5V, 1p8V, 2p5V, and 3p3V Regulators ........................... 18 11 TLK10xxx EVM Schematic, Sheet 4 of 15 Power Distribution ...................................................... 19 12 TLK10xxx EVM Schematic, Sheet 5 of 15 Voltage Monitoring ...................................................... 20 13 TLK10xxx EVM Schematic, Sheet 6 of 15 Device Power, Ground, and Local Decoupling ..................... 21 14 TLK10xxx EVM Schematic, Sheet 7 of 15 Global and Control Signals ............................................ 22 15 TLK10xxx EVM Schematic, Sheet 8 of 15 USB, MDIO, JTAG, and I2C Interface ................................ 23 16 TLK10xxx EVM Schematic, Sheet 9 of 15 Clocks .................................................................... 24 17 TLK10xxx EVM Schematic, Sheet 10 of 15 Clock Control........................................................... 25 18 TLK10xxx EVM Schematic, Sheet 11 of 15 Crystal Oscillators ..................................................... 26 19 TLK10xxx EVM Schematic, Sheet 12 of 15 Low-Speed Data Signals ............................................. 27 20 TLK10xxx EVM Schematic, Sheet 13 of 15 High-Speed Data Signals ............................................ TLK10xxx EVM Schematic, Sheet 14 of 15 Data Board-to-Board Connector ..................................... TLK10xxx EVM Schematic, Sheet 15 of 15 Clock Board to Board Connector .................................... TLK10xxx EVM Layout, Top Signal (Layer 1) ......................................................................... TLK10xxx EVM Layout, Internal Ground (Layer 2) ................................................................... TLK10xxx EVM Layout, Internal Signal (Layer 3) ..................................................................... TLK10xxx EVM Layout, Internal Ground (Layers 4, 6, 7, 9, 11, 13, 15) ........................................... TLK10xxx EVM Layout, Internal Power (Layer 5) ..................................................................... TLK10xxx EVM Layout, Internal 5-V Power (Layer 8) ................................................................ TLK10xxx EVM Layout, Internal 5-V Power (Layer 10) .............................................................. TLK10xxx EVM Layout, Internal Power (Layer 12) ................................................................... TLK10xxx EVM Layout, Internal Signal (Layer 14) ................................................................... 28 21 22 23 24 25 26 27 28 29 30 31 2 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 29 30 31 32 33 34 35 36 37 38 39 SLLU187 – November 2013 Submit Documentation Feedback www.ti.com 32 TLK10xxx EVM Layout, Bottom Signal (Layer 16 Top View) ........................................................ 33 TLK10xxx EVM SMA Breakout Board Schematic, Sheet 1 Cover Page and Index .............................. 42 34 TLK10xxx EVM SMA Breakout Board Schematic, Sheet 2 Channel B and CLKA/B Signals ................... 43 35 TLK10xxx EVM SMA Breakout Board Schematic, Sheet 3 Channel A and CLKA1_IN Signals ................ 44 36 TLK10xxx EVM SMA Breakout Board Schematic, Sheet 4 Common Control Signals ........................... 45 37 TLK10xxx EVM SMA Breakout Board Layout, Top Signal (Layer 1) ............................................... 46 38 TLK10xxx EVM SMA Breakout Board Layout, Internal Ground (Layer 2) ......................................... 47 39 TLK10xxx EVM SMA Breakout Board Layout, Internal GND (Layers 3, 4, 5) ..................................... 48 40 TLK10xxx EVM SMA Breakout Board Layout, Bottom Signal (Layers 6) .......................................... 49 41 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 1 of 10 Cover Page and Index...................... 51 42 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 2 of 10 1V_D1/D2, 2p5V, 3p3V LEDs ............. 52 43 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 3 of 10 1V_A1/A2, VDDRB_HS LEDs ............. 53 44 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 4 of 10 VDDA, VDDT, VDDD, DVDD LEDs ...... 54 45 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 5 of 10 CLK_DVDD/VCC/VDD_OUT_B/VDD_IN LEDs ....................................................................... 55 46 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 6 of 10 3P3V_CLK, CLK_VDD_PLL_A/_OUTA/_PLL LEDs ................................................................................. 56 47 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 7 of 10 VDDRB_LS AND VDDRA_HS LEDs ..... 57 48 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 8 of 10 VDDRA_LS AND VDDO LEDs ............ 58 49 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 9 of 10 1.5-, 1.8-, and 5-V LEDs ................... 59 50 TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 10 of 10 Edge Connector ........................... TLK10xxx EVM Voltage Monitor Board Layout, Top Signal Layer.................................................. TLK10xxx EVM Voltage Monitor Board Layout, Internal Ground (Layer 2) ........................................ TLK10xxx EVM Voltage Monitor Board Layout, Internal Power (Layer 3) ......................................... TLK10xxx EVM Voltage Monitor Board Layout, Bottom Signal (Layer 4).......................................... TLK10xxx EVM USB Dongle Board Schematic, Sheet 1 of 2 Cover Page and Index ........................... TLK10xxx EVM USB Dongle Board Schematic, Sheet 2 of 2 Schematics ........................................ TLK10xxx EVM USB Dongle Board Layout, Top Signal Layer ...................................................... TLK10xxx EVM USB Dole Board Layout, Internal Power (Layer 2) ................................................ TLK10xxx EVM USB Dongle Board Layout, Internal GND (Layer 3) ............................................... TLK10xxx EVM USB Dongle Board Layout, Bottom Signal (Layer 4 Top View) ................................. 60 51 52 53 54 55 56 57 58 59 60 SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 40 61 62 63 64 66 67 68 69 70 71 3 Introduction 1 www.ti.com Introduction The Texas Instruments (TI) TLK10022 and TLK10081 (hereafter in this document referred to as TLK10022/81) SERDES evaluation module (EVM) boards are used to evaluate the functionality and the performance of the TLK10022 and TLK10081 multi-rate link aggregation devices in a 144-pin PBGA package. The TLK10022 and TLK10081 are multi-rate link aggregators intended for use in high-speed bi-directional point-to-point data transmission systems. These devices’ intended purpose is to reduce the number of physical links by multiplexing lower speed serial links into higher speed serial links. The TLK10022/81 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock, recovered from the high-speed side. Other features of the TLK10022/81 include various PRBS, high, low, and mixed CRPAT, long and short generation, and verification for self test system-level support. Low-speed and high-speed side loopback modes are provided for self-test and system diagnostic purposes. Several high- and low-speed internal loopback modes are also possible for self-test and system diagnostic purposes. The TLK10022/81 has an integrated loss of signal (LOS) detection function on both high- and low-speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be cleared. Configuration of the TLK10022/81 is available by way of accessing a register space of control bits available through a two-wire access port called the Management Data Input/Output (MDIO) interface as defined in Clause 22 of the IEEE 802.3 Ethernet Specification. The TLK10022/81 EVM GUI provides access to all the registers of every device used on any of the TLK10022/81 boards through a standard USB 1.1 interface. The boards can be configured, if necessary, to accept or provide MDIO signals from or to an external source by installing and uninstalling certain resistors. The TLK10022/81 EVM board can be run from one 5-V power supply and all voltages needed are regulated down through on board LDO Regulators which can be adjusted to the appropriate minimum, nominal, and maximum values by changing a single resistor value. Voltage monitor circuits with LEDs are included for all voltage rails for easy debugging and identification of valid power rails through the use of the voltage monitor board. All Data I/O signals are broken out to connectors for easy and rapid prototyping and all control signals are easily controlled through the GUI or shunts on header blocks and dip switches. 2 EVM PCB and High-Speed Design Considerations The board can be used to evaluate device parameters in addition to acting as a guide for high-speed board layout. As the frequency of operation increases, the board designer must take special care to ensure that the highest signal integrity is maintained. To achieve this, the board's impedance is controlled to 50-Ω single-ended, or 100-Ω differential impedance for both the low and high-speed differential serial and clock connections. Vias are minimized and, when necessary, are designed to minimize impedance discontinuities along the transmission line. Care was taken to control trace length mismatch (board skew) to less than ±0.5 MIL. Overall, the board layout is designed and optimized to support high-speed operation. Thus, understanding impedance control and transmission line effects are crucial when designing high-speed boards. Some of the advanced features offered by this board include: • TLK10022/81 PCB (printed-circuit board) is designed for optimal high-speed signal integrity using Rogers material for the outer signal layers and FR-4 for the inner layers. All gigabit and clock signals are routed over the Rogers material for minimal signal loss. The FPGA and SMA breakout daughterboards use FR-4 for all layers. • SMA and header fixtures are easily connected to test equipment. • All input/output signals are accessible for rapid prototyping. • On-board capacitors provide AC coupling of differential transmit and receive signals. Zero-Ω resistors have been placed on the transmit pins so that external loopback tests can be implemented and only a single AC-coupling capacitor on the RX pins will be located in between the TX and RX signals. If the 4 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10022/81 EVM Kit Contents www.ti.com • • • • 3 TX signals need to be evaluated on their own, the 0-Ω resistors can be replaced with 0.1-µF capacitors. The high-speed signals of channel A have been routed to SFP+ modules for easy evaluation in systems that implement optical fiber configurations. The high-speed signals of channel B have been routed to edge launch SMA connectors for easy evaluation in systems that use standard test equipment. The low-speed signals of all four channels have been routed to Samtec SEAM/SEAF board-to-board connectors allowing for smaller EVM PCB size and additional options for evaluation of these signals. An SMA breakout board is optionally supplied that will allow for access to these low-speed signals. SMA cables can be connected from the input signals to the output signals to create an external loopback situation, or to standard lab test equipment. The pinout is compatible with the TLK10002 EVM FPGA daughterboard and any variety of custom interface boards could be created for use with the TLK10022/81 EVM motherboard. The MDIO data signals have been routed to the TLK10XXX and the bus continues to a 0.10” header allowing for multiple boards to be daisy chained on a single MDIO Bus. This board can operate in standalone mode using an external MDIO data controller and the hardware control pin settings, or through the USB Dongle interface. The use of the USB Dongle is recommended and the preferred mode of operation. All control pins of the TLK10XXX device have also been connected to TI’s TCA6424 I2C-to-GPIO device and when using the supplied TLK10XXX EVM GUI and USB interface, these control pins should be set to a high voltage or logic “1” in hardware and controlled through the GUI interface allowing the TCA6424 to pull the signals low, when needed. TLK10022/81 EVM Kit Contents The TLK10022/81 EVM kit contains the following: • TLK10022/81 EVM motherboard • USB Dongle board • Voltage monitor board • SMA breakout board (optional) • TLK10022/81 EVM User’s Guide (this document) • Banana jack power adapter cables • USB cable • CD-ROM containing user interface software 4 Power The TLK10022/81 EVM motherboard can be powered from one 5-V power supply. The 5-V power supply powers the board’s general logic IC’s and LDOs as well as the board’s LEDs. The power from the LDOs is split into the planes through 1210 0-Ω resistors that could be replaced with a ferrite bead or inductor of the user’s choice should the need arise to filter out any noise that may be present. A series of bulk decoupling capacitors are placed at the entry point of the split planes immediately following the 1210 0-Ω resistors. Additional local decoupling capacitors are placed near the power pins of the devices connected to the planes in order to source instantaneous switching current and help with noise filtering. The 5-V supply input should have a current ability of approximately 2.5 A if running in the heaviest power device configurations. The LDO regulators used on the EVM are TI’s TPS74401 and are adjustable using a resistor divider between the output and a feedback pin. Each regulator has been set to provide the appropriate voltage with a slightly higher margin at the source to account for IR drop across the board since there are no sense lines on these regulators. If more information on the use of these regulators is desired, please consult the regulator data sheets found at www.ti.com. Several power supplies such as VDDRA_LS/HS, VDDRB_LS/HS, and VDDO can be operated off of either 1.5 V or 1.8 V, depending upon your specific setup. The EVM is designed to allow either of these voltages to be selected for use with the previously mentioned TLK10022/81 supply rails, but will only allow either 1.5 V or 1.8 V to be selected at a time. Selection between 1.5 V and 1.8 V is performed by moving the jumper between the center pin and the respective 1p5V and 1p8V pins of JMP35. SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 5 Voltage Monitoring Board and Power Rail LEDs www.ti.com Refer to the Schematic Sections of this manual for more detailed information on the regulators and power distribution circuitry. 5 Voltage Monitoring Board and Power Rail LEDs The voltage monitoring board has window detection circuits that drive LEDs which provide quick indication that the voltage is within specification. The voltage monitor board draws power from the 5-V plane on the motherboard and a sense line to every power rail on the board is connected to the Samtec MEC1 connector. If the voltage on the sense line is within the minimum or maximum limit for that particular plane, the window detection circuit will cause the LED to turn on as an indicator that the plane is properly sourced. If the voltage is outside the minimum or maximum limits, then the LED will fail to light and the user will be informed that there is a problem with the power on that rail and the TLK10022/81 device may not function properly. Several of the power planes on the TLK10022/81 can be supplied from either 1p5V or 1p8V and a separate LED and monitor circuit have been supplied for each case to allow the user to determine whether the board is configured with the intended voltage. The voltage monitor board is not required for operation of the TLK10022/81 EVM motherboard and this board is supplied as a tool to be used full time or as a debug device. Hot swapping this board should not cause any damage to either the TLK10022/81 EVM motherboard or the voltage monitoring board. The LEDs should be used as a basic indication of the status of power on the board being within the acceptable min/max limits given in the data sheet, and not as a precise measurement tool as some LED circuits may turn off at slightly different voltages when approaching the limits due to the manufacturing tolerances and available resistor values. 6 Control and Output Status Signals All of the external control and status pins on the TLK10022/81 EVM have been consolidated to a single location on the board and broken out onto several header blocks and dip switches. LEDs have been added to the LOSA/B, LS_OK_OUT_A/B, and PRBS_PASS signals in addition to the headers for scope probes, to allow easy monitoring of the High/Low value on the lines. The LED will be ON when the line is a logic High, and the LED will be OFF when the line is a logic Low. All status pins and external control pins of the TLK10022/81 can also be monitored or set High/Low through the GUI. The preferred method of setting these control pins is through the GUI via the TCA6424 I2C-to-GPIO IC located on the board. If shunts are placed on the header for a particular control pin, or the dip switch setting set low, the signal will be physically tied low and software control will not be possible. Mixed use of the hardware and software setting of various control pins is discouraged. The I2C-based software control of the TLK10022/81 control pins can be disabled by placing a shunt on JMP100 which will disable the level shifter attached to the signals by setting the enable pins Low or by selecting the Disable Software Control of Pins radio button located on the front panel of the GUI. This will allow the onboard pullup resistors or shunts to ground on the header pins to set the High/Low status of the control pins. If external control is desired and a shunt is placed on JMP100, the Disable Software Control of Pins radio button on the GUI front panel should be de-selected as well, to disable the software portion of the interface. The TCA6424 device will respond to either I2C device address 0x22 or 0x23. When two boards are used and daisy chained together the I2C address must be changed on the one of the two boards so that there is individual control of both boards. Flipping the switch on SW11 will change the address from 0x22 to 0x23. See the TLK10022 (SLLSEE7) or TLK10081 (SLLSEE9 ) data sheet for a detailed description of the control signals. 7 MDIO The TLK1022/81 supports the Management Data Input/Output (MDIO) interface as defined in Clause 22 of the IEEE 802.3 Ethernet Specification. The MDIO allows register-based management and control of the serial links. Normal operation of the TLK10022/81 is possible without the use of this interface, however, most features are accessible only through the MDIO interface. The MDIO interface consists of a bi-directional data path (MDIO) and a clock reference (MDC). The port address is determined by control pins PRTAD[4:0] as described in the data sheet. 6 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback JTAG www.ti.com The top 4 control pins, PRTAD[4:1], determine the device port address and are set in hardware on the board. The two individual channels in TLK10022 are classified as 2 different ports. So for any PRTAD[4:1] value there will be 2 ports per TLK10022. The TLK10022 will respond if the 4 MSBs of PHY address field on MDIO protocol (PA[4:1]) matches PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which channel or port within the TLK10022 to control. If PA[0] = 0, TLK10xxx’s channel A will respond. If PA[0] = 1, TLK10xxx’s channel B will respond. Write transactions which address an invalid register or read only registers will be ignored. Read transactions of invalid registers will return a “0”. The TLK10022/81 requires either 1.5 V or 1.8 V I/O levels on the MDIO/MDC signals. Therefore, a bidirectional, on-board level shifter has been provided that level shifts the 3.3-V MDIO and MDC signals to the appropriate 1p5/8V levels. Should a different MDIO controller be used that already has 1.5-V or 1.8-V signal levels, resistors R298, R299, R451, and R491 should be removed, thus disconnecting the level shifter and resistors R293, R295, R634, and R635 can be installed which will connect the TLK10022/81 MDIO and MDC signal pins directly to the pins of JMP50. The USB Dongle implementing TI’s TUSB3210 microcontroller is the preferred method of controlling the TLK10022/81 register stack and is the only way to interface the GUI with the board. When the USB Dongle is connected to the EVM board through the Samtec MEC1 connector, the MDIO signals will be at 3p3V levels because the TUSB3210 is a 3p3V device with open drain architecture. The EVM board has TI’s TXS0108EPWR bi-directional level shifter to convert the MDIO signals to the 1p5/8V levels required by the TLK10022/81. Ensure that a shunt is placed on the 3p3V and MDIO_LS pins of JMP77 on the EVM board to ensure that the appropriate 3p3V voltage is used on the level shifter and pull-up resistors. The 2p5V voltage option is supplied for TI use only with a legacy MDIO controller. MDIO signals can be routed to either of the low-speed board-to-board connectors for use with the TLK10002 EVM FPGA daughterboard or other interface boards that may require MDIO communication on the same MDIO bus as the TLK10022/81. Currently this feature is not supported but will be available at a future time. Control over the relays used to route the MDIO bus without creating stub branches is done using switch SW11, or through the TCA6424 I2C interface and GUI. The MDIO PRTAD[4:1] is defaulted to 4b’0000. If this value is changed in hardware, it must also be changed in the GUI so that proper MDIO communication is possible. 8 JTAG The EVM also provides a separate connector to support the full five-pin JTAG interface of the TLK10022/81 with on-board level shifters to be compatible with most standard JTAG control interfaces to be used for manufacturing tests. The 3.3-V (header) side of the level shifter is connected to the header and the 1p5/8V side of the level shifter is connected to the TLK10022/81. If the level shifter is not needed, providing an external voltage of the appropriate signal level between pins 2 and 3 of JMP62 should allow the signals to pass to the TLK10022/81 correctly. 9 Reset The TLK10022/81 EVM comes configured for manual reset operations involving the pushbutton reset switch (SW10). When switch SW10 is pressed, the TLK10022/81 device RESET pin (RST_N) goes Low and the entire TLK10022/81 device is reinitialized. A TI TPS3125J18 ultra-low-voltage processor supervisory circuit is used to control the reset line. During power-on, the RESET pin of U12 is asserted when the supply voltage becomes higher than 0.75 V. Thereafter, the supply voltage supervisor monitors the voltage and keeps RESET output active as long as the voltage remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td = 180 ms, starts after the voltage has risen above the threshold voltage (VIT). SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 7 Test and Setup Configurations www.ti.com There is also a manual reset input to the supervisory circuit, MR, which accepts the input from the pushbutton switch SW10. A low level at MR causes RESET to become active, thus resetting the TLK10022/81 device whenever the pushbutton RESET is pressed. By placing a jumper on JMP42, the manual reset (MR) is tied hard to ground, causing the TLK10022/81 to be held in a constant state of Reset without the need to continually hold the reset pushbutton SW10. The supervisory circuit will release the Reset line to a HIGH 180 ms (td) from the time the MR line becomes greater than the threshold voltage (VIT). NOTE: In order to keep the GUI settings and the device settings synchronized during the evaluation of the TLK10022/81, all RESET commands should be issued through the GUI via the TCA6424 I2C-to-GPIO device connected to the signals. When the software Main Board Reset buttons are pressed, the GUI will adjust its memory settings of the various registers in order to match the new values the devices will reflect after the hardware RESET is performed. If the buttons are pressed on the board, the GUI will not reflect the devices true status and may result in erroneous results during testing because the device is not configured according to the GUI's displayed results. Depending upon the power down or GUI termination sequence followed, the USB device may need to be RESET to allow re-enumeration to occur in future tests. When the board is powered on and the USB connection is enumerated, the USB online LED (D4) should light on the USB Dongle board. If this LED fails to light, there may be a PC-related issue and the PC should be restarted. The LED should light once the PC error is fixed. If the USB connection is improperly disconnected or terminated, the USB SUSPEND light (D3) should light and is an indication the USB connection is not properly established. A reset pushbutton is located on the USB Dongle board and pressing this device will reset the TUSB3210 Microcontroller as well as momentarily disconnect the USB device from the PC’s USB bus causing the PC to re-enumerate the device after the reset is complete. 10 Test and Setup Configurations The TLK10022/81 EVM has an SPF+ optical module cage attached directly to the Channel A high-speed signals with approximately 3 inches of trace over Rogers low-dielectric material. Channel B’s high-speed signals are attached to edge launch SMA connectors with 0.1-µF AC-coupling capacitors on the RX lines, and 0-Ω resistors on the TX lines to facilitate an external loopback configuration with only a single set of capacitors in line. The caps or resistors should be carefully reworked as necessary to facilitate the test needs during evaluation. Placing two 0.1-µF AC-coupling capacitors can result in lower performance and greater numbers of bit errors. All low-speed signals on the input signals have 0.1-µF AC-coupling capacitors and are routed to a Samtec SEAF board-to-board connector that will mate with either an SMA breakout board for use in parametric and lab testing, or a Spartan-6 FPGA board for system-level evaluation. The output signals are connected to 0-Ω resistors allowing them to be connected to the AC-coupled input signals. These 0-Ω resistors could be easily re-worked with 0.1-µF capacitors for AC-coupled applications. The MDIO bus that is connected to the TLK10022/81 is also routed to the SEAF board-to-board connector and can be used to interface with either the FPGA or an external system board via the Post Level Shifter MDIO Signal header on the SMA Breakout board. 8 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback Test and Setup Configurations C619 C618 C617 C616 C74 U24 C71 R684 R687R686 R685 C671 +5V 1p5/8V JMP41 C138 C621 C620 C629 C628 C624 1p8V 1p5V U16 R703 C684 U12 BJ 5V PLUG C139 C140 P26 C46 C43 SEC_OSC TLK10xxxEVM MOTHER BOARD REGULATOR REV B DISABLE 6566789 EN C32 C29 1p5V REG 1p8V REG C127 C118 C108 C84 D28 C91 DIS 3P3V_CLK 3P3V 1P8V 1P5V 1P0V_D2 1P0V_D1 1P0V_A2 1P0V_A1 C89 C90 C115 C113 C114 C125 C123 C124 C101 C99 C100 C130 C128 C98 J104 C129 C627 U115 5V SW17 C97 D111 JMP104 C95 C93 R781R780 PRI_REF_IN_N R785 P1 P14 3p3V_CLK REG C625 R712 C683 R704 R713 C682 PRI_REF_IN_P R784 C693 R783 +5V JMP35 U100 R777 R782 C692 R696 R697 R695 R698 C674 C675 C676 C677 SW16 D110 J103 R699 PRI_OSC HIGH C681 C680 C679 C678 R701R700 C667 C668 C622 R689 R691 U105 R702 C654 C670 U114 C623 C672 R694R693 R690 R692 R688 LOW GND C626 REF_SEL SI_MODE0 SI_MODE1 C673 www.ti.com C94 STATUS 1/PIN0 D101 STATUS 1 EN D103 C67 CLKB SW18 PLL_LOCK (STATUS 0) CLK SYNCN D10 SW10 RST BTN U112 D109 RST/PWR D108 RST/PWR U110 U108 D107 SYNCN D106 SYNCN J41 D105 PDN D104 PDN 3p3V REG MAIN RESET RST SW13 SW19 PRI_REF (30.72MHZ) (31.25MHZ) D102 SEC_REF D11 GND SW14 U101 U22 CLK PDN J102 CLK RST/ SW15 PWR C600 SPI_MOSI/PIN1 CLKA C64 PRI_OSC SPI_MISO/PIN2 RESET DIS RESET SPI_LE1/PIN3 EXT SMA CLK BUFFER INPUT SEC_OSC CLK GEN SPI_CLK/PIN4 C604 SPI_LE2 1p0V_A2 REG JMP42 J44 R582 J43 J42 HSTXBn J100 VOLTAGE MONITOR DONGLE J6 REFCLK0n REF CLK1n REFCLK1p C107 C109 R581 U10 C110 C24 HSTXBp REF CLK0p C111 1p0V_D1 REG R5 74 R5 7 R5 76 R5 7 R5 78 R5 6 71 R5 73 R5 69 R5 75 R5 67 R5 77 J72 C247 R5 79 R5 R5 80 HSRXBp C22 TLK 10002 TLK 10232 J5 U1 J7 HSRXBn CLKOUTBn CLKOUTAp J45 2 J46 0 CLKOUTAn J47 8 CLKOUTBp 65 R5 R5 66 J48 C249 C121 C117 C120 J8 U8 JTAG C87 C85 HIGH GND Q100 R632 22 SW11 LOW PDTRXA PDTRXB M9 LOSB LOSA AMUXA JMP100 PRBS PASS AMUXB GND GND LS_OKINA LS_OKINB IN GND PRTAD0 JMP101 PRTAD4 PRTAD3 PRTAD2 PRTAD1 GND LOW R626 R625 U64 H10 PRBSEN TESTEN GPIO MDIO_B2B_RLY MDIO_CON_RLY I2C_GPIO_ADDR LOSB LOSA R627 R628 R629 JMP48 JMP77 3p3V JMP62 SW12 J101 GND JMP61 OUT JMP47 TRST MDIOV JMP103 C86 C15 D12 D13 D16 D15 D14 PRBS PASS TX DIS R548 LS_OK OUT_A U42 U41 12C_LS_EN JTAG_V TDO 2p5V R630 R631 3p3V USB DONGLE R633 D48 R539 D100 C607 U92 SFP+ TX_DIS LS_OK OUT_B D51 D52 RX_LOS R553 GND TX_FAULT R549 JMP36 MOD DETECT TCK TMS TDI U40 K3 C80 D50 D49 TX DIS SCL JMP102 I2C 2p5V MDC OUTPUT K1 MDIO R546 MDC INPUT MDIO SDA INT1 RESET1 K4 INT2 K2 RESET2 JMP50 C119 1p0V_D2 REG U102 C17 J73 1p0V_A1 REG C611 JMP105 HIGH 23 Figure 1. TLK10xxx EVM Motherboard SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 9 Copyright © 2013, Texas Instruments Incorporated OUTB0N / OUTA4N / CLKB0P J2 R 2 J20 R 19 R2 0 LS_OK_IN_A LS_OK_OUT_A LS_OK_IN_B LS_OK_OUT_B INB0P / INA4P / CLKA3N INA3N TLK10022 and TLK10081 Evaluation Module (EVM) OUTA3P J3 J4 J22 J21 JMP2 JMP1 J23 J5 GND GND INB0N / INA4N / CLKA3P INA3P R 1 10 JMP3 OUTB0P / OUTA4P / CLKB0N OUTA3N R INB1N / INA5N / CLKA2P 5 INB1P / INA5P / CLKA2N 24 J24 R 23 R J25 INA2N 30 29 J28 R R J29 J30 INA1N INA1P OUTA1P OUTA1N OUTB2P / OUTA6P / CLKB2N J13 J12 J26 INA2P INB2N / INA6N / CLKA1P INB2P / INA6P / CLKA1N OUTB2N / OUTA6N / CLKB2P J31 OUTA2P 11 12 J11 R R J10 J27 OUTA2N MDC MDIO OUTB1P / OUTA5P / CLKB1N J9 J8 OUTB1N / OUTA5N / CLKB1P J7 R 6 J6 R R 34 INA0N R 36 35 J34 J35 OUTA0P OUTA0N CHA_CLKOUTP / CLKA1P_IN J36 R TLK10xxx SMA BREAKOUT BRD 6568779 REV N/A J32 R 33 R J33 INA0P CHB_CLKOUTP / CLKB1N_IN J19 R 18 17 J37 CHA_CLKOUTN / CLKA1N_IN CHB_CLKOUTN / CLKB1P_IN J18 OUTB3P / OUTA7P / CLKB3N J17 J16 OUTB3N / OUTA7N / CLKB3P INB3N / INA7N / CLKA0P J15 R 16 15 J14 INB3P / INA7P / CLKA0N Test and Setup Configurations www.ti.com Figure 2. TLK10xxx EVM SMA Breakout Board SLLU187 – November 2013 Submit Documentation Feedback GND Test and Setup Configurations D4 VOLTAGE MONITOR 6568778 REV NA D3 3p3V D31 2p5V D30 1p8V 5V C16 C18 TLK10xxx C17 5p0V C15 D9 www.ti.com GND JMP1 D6 1p5V D5 1p0V_A1 D2 1p0V_A2 D1 1p0V_D1 U2 C2 U8 C3 U5 C1 U44 C19 D13 1p0V_D2 D12 VDDA D11 VDDT D10 VDDD DVDD 1p8V 1p5V U32 C11 U35 C12 U38 C13 U41 C14 VDDO D28 D29 D26 D27 D24 D25 D22 D23 D7 D8 VDDRA_LS VDDRA_HS U14 VDDRB_LS C5 U17 C6 U26 C9 U29 C10 D20 CLK_VDD_PLL D19 CLK_VDD_PLLA D18 CLK_VDD_OUTA D17 CLK_VDD_OUTB D16 CLK_VDD_IN D15 CLK_DVDD D14 D21 VDDRB_HS 3P3V_CLK CLK_VCC U23 C7 U20 C8 U11 C4 JN Figure 3. TLK10xxx EVM Voltage Monitor Board SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 11 Test and Setup Configurations www.ti.com J1 D2 D3 D4 USB RST RST SUSPND ONLINE D1 R41 C4 C3 ON SW2 C15 U2 R78 R66 R74 R75 R67 R68 R69 R70 R71 R72 R73 R49 R48 RST R58 R59 C13 R60 R61 SW1 R47 R46 R45 R44 R43 R42 C12 R57 R56 R93 R96 R55 R54 R53 R52 U4 R92 C16 ECS D 12.0 MHz Q1 R62 R63 R64 R65 R50 R51 C14 R91 R90 R17 R19 R21 R23 R25 R27 R29 R31 R33 R35 R37 R39 C1 R7 R9 R11 R13 R1 Figure 4. TLK10xxx EVM USB Dongle Board 12 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback Test and Setup Configurations www.ti.com C618 U24 C71 C616 C622 C74 C619 C617 C623 C672 C673 R684 R685 C671 C621 C620 C629 C628 C625 C624 C674 C675 C676 C677 R703 C684 U12 1p5V REG C84 PDN C604 C67 U101 J100 VOLTAGE MONITOR DONGLE REF CLK1n REFCLK1p C107 C109 C111 M12 1p0V_D1 REG J15 OUTB2P / OUTA6P / CLKB2N C22 4 16 J17 INB3N / INA7N / CLKA0P OUTB3P / OUTA7P / CLKB3N CHA_CLKOUTN / CLKA1N_IN J37 17 MDC MDIO R JMP3 GND CLKOUTAp R 18 R 35 J19 J36 2 R57 6 0 R57 R57 R56 R56 R56 R56 8 JMP2 J45 R56 J46 GND R57 8 R57 R57 0 6 3 A1 CLKOUTAn J47 J13 J18 LS_OK_IN_B LS_OK_OUT_B LS_OK_IN_A LS_OK_OUT_A CLKOUTBp J9 OUTB3N / OUTA7N / CLKB3P J16 CHB_CLKOUTN / CLKB1P_IN CLKOUTBn J48 J14 JMP1 HSRXBn C249 J12 OUTB1P / OUTA5P / CLKB1N R57 5 U1 7 A12 J7 R57 9 J72 C247 R57 R57 R58 HSRXBp INB3P / INA7P / CLKA0N J8 R + M1 TLK 10002 TLK 10232 J5 INB2N / INA6N / CLKA1P OUTB2N / OUTA6N / CLKB2P U10 C110 OUTB1N / OUTA5N / CLKB1P GND REF CLK0p REFCLK0n R581 J2 HSTXBp C24 J6 12 J11 INB1N / INA5N / CLKA2P INB0N / INA4N / CLKA3P J43 J42 R 6 36 D104 J44 R582 HSTXBn R J7 R PDN 15 SYNCN J41 D105 1p0V_A2 REG R D107 D106 3p3V REG MAIN RESET JMP42 J4 RST/PWR U108 SYNCN 2 D108 U110 R RST/PWR J3 D109 11 SW10 RST BTN U112 PRI_REF (30.72MHZ) (31.25MHZ) D102 SEC_REF D11 RST SW13 R C91 C90 U22 D10 GND SW14 J10 J6 5 CLK SYNCN CLK RST/ PWR INB2P / INA6P / CLKA1N INB1P / INA5P / CLKA2N INB0P / INA4P / CLKA3N SW15 C94 C600 D103 CLKB SW18 PLL_LOCK (STATUS 0) C95 + C64 D101 SW19 RESET ON 1 2 EN RESET PRI_OSC SPI_MOSI/PIN1 CLK PDN J102 ON SPI_MISO/PIN2 STATUS 1/PIN0 CLKA 1 2 DIS EXT SMA SPI_LE1/PIN3 STATUS 1 + CLK BUFFER INPUT SEC_OSC CLK GEN SPI_CLK/PIN4 C98 3P3V_CLK 3P3V 1P8V 1P5V 1P0V_D2 1P0V_D1 1P0V_A2 1P0V_A1 C89 C115 C114 C124 C113 C123 C99 C125 C101 C100 C129 C128 C130 C626 C627 U115 ON JMP104 SPI_LE2 5V D28 DIS R C108 OUTB0P / OUTA4P / CLKB0N C118 C97 J5 C127 D111 J104 OUTB0N / OUTA4N / CLKB0P SEC_OSC TLK10xxxEVM MOTHER BOARD REGULATOR Rev B DISABLE 6566789 EN C32 C29 SW17 R777 C46 C43 1p8V REG R781R780 PRI_REF_IN_N R785 C140 C93 D110 R712 C683 R704 R713 C682 1p8V C139 1 PRI_REF_IN_P U16 BJ 1p5V 5V PLUG P26 U100 R784 C693 R783 JMP41 C138 JMP35 + R782 C692 +5V 1p5/8V + HIGH J103 R696 R697 R695 R698 P1 3p3V_CLK REG R SW16 PRI_OSC R699 1 2 3 4 C681 C680 C679 C678 R701R700 C667 C668 R687R686 C654 C670 U114 +5V P14 1 2 3 4 5 6 7 8 REF_SEL SI_MODE0 SI_MODE1 R689 R691 U105 R702 LOW ON GND + R694R693 R690 R692 R688 CHB_CLKOUTP / CLKB1N_IN CHA_CLKOUTP / CLKA1P_IN 1 9 7 5 C121 C117 C120 J26 J30 J32 JTAG OUTA0N J35 34 J21 33 HIGH GND INA2P INA1P INA0N OUTA0P 30 R 24 23 R 29 J24 J28 R R628 TLK10xxx SMA BREAKOUT BRD 6568779 REV N/A J29 R OUTA3N OUTA3P R627 R625 R626 R632 J23 SW11 ON OUTA1P J25 22 LOW HIGH J22 Q100 MODE/REFCLK_SEL PRBSEN TESTEN GPIO MDIO_B2B_RLY MDIO_CON_RLY I2C_GPIO_ADDR PDTRXA PDTRXB ST/GPI1 LOSA LOSB JMP100 PRBS PASS AMUXA AMUXB GND LS_OKINA GND GND OUTA2P R629 U64 JMP48 IN 1 2 3 4 LS_OKINB PRTAD0 JMP61 J34 INA3P INA3N C607 C87 C86 R630 LOSA LOSB PRBS PASS LOW OUT JMP77 C85 C15 D12 D13 D16 D15 D14 LS_OK OUT_A LS_OK OUT_B PRTAD4 PRTAD3 PRTAD2 PRTAD1 ON JMP62 SW12 J101 JTAG_V JMP101 JMP47 GND 3p3V 20 J33 R U8 U92 U42 U41 12C_LS_EN GND MDIOV TDO 2p5V R633 R631 TRST TCK TMS TDI U40 USB DONGLE R J31 R D48 3p3V JMP103 J20 J27 D52 D51 TX_FAULT RX_LOS R553 R549 GND D50 D49 SFP+ TX_DIS MOD DETECT TX DIS TX DIS JMP36 R539 JMP102 K3 D100 1p0V_D2 REG C80 R548 SCL I2C 2p5V MDC OUTPUT K1 MDIO R546 MDC INPUT MDIO SDA RESET1 INT2 K4 RESET2 K2 INT1 JMP50 C611 + 19 1p0V_A1 REG U102 C17 + JMP105 J73 INA0P OUTA1N OUTA2N R J8 C119 1 2 3 4 5 6 7 8 9 10 INA2N INA1N 23 Figure 5. TLK10xxx EVM Motherboard and SMA Breakout Board for Channels A/B SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 13 JMP77 MDIOV GND JMP47 JTAG JTAG_V JMP62 HIGH LOW GND JMP61 U41 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated HIGH U42 J8 C117 C22 C110 12C_LS_EN GND JMP100 LOW C24 C600 C64 3p3V REG J5 R633 R631 R628 1p0V_A1 REG C611 C111 U10 C109 C107 U101 C604 C93 SW17 C620 C628 C671 R684 R687R686 R685 C673 REF_SEL SI_MODE0 SI_MODE1 C71 C618 C616 U24 C619 C617 C622 C74 C672 C623 3p3V_CLK REG U64 R626 C607 4 D111 Q100 D48 R627 R57 C91 C90 3P3V_CLK 3P3V 1P8V 1P5V 1P0V_D2 1P0V_D1 1P0V_A2 1P0V_A1 C621 C629 C674 C675 C676 C677 C683 D110 SW16 P14 R632 R625 2 R57 C67 R712 R704 R713 C682 C624 C32 MODE/REFCLK_SEL PRBSEN TESTEN GPIO MDIO_B2B_RLY MDIO_CON_RLY I2C_GPIO_ADDR U102 U22 C89 C115 R703 C684 P26 C625 1p5V REG C87 MAIN RESET C86 0 6 8 CLK BUFFER INPUT SW11 3p3V R57 R57 C114 C113 C125 C124 C123 C101 C100 C99 C130 C129 C128 C626 C627 R777 R781R780 C29 PDTRXA PDTRXB ST/GPI1 C17 JMP105 C85 C15 JMP36 PRBS PASS R57 R581 LOSB 8 R56 RESET RESET JMP104 LOSA U8 J6 AMUXA 0 SW10 AMUXB R58 RST GND 6 J45 R56 J72 LS_OKINB D12 D13 RST BTN LS_OKINA LOSB U108 LOSA C247 D16 D10 GND MOD DETECT D14 PDN PRBS PASS GND BJ 1p5V 5V PLUG JMP48 2p5V PDN IN D100 D105 D104 PRTAD0 I2C SFP+ TX_DIS LS_OK OUT_A U110 PRTAD4 PRTAD3 PRTAD2 PRTAD1 SW19 JMP101 J46 D15 CLKOUTAn LS_OK OUT_B J7 SW13 OUT SW12 J42 GND SYNCN TRST REF CLK1n U92 TLK 10002 TLK 10232 D106 TDO J73 GND J47 D51 CLKOUTBp D52 HSRXBp RX_LOS TX_FAULT J41 CLK PDN C108 1 3p3V SW14 C118 R57 JMP103 CLK SYNCN C46 3 R549 REF CLK0p R553 J102 C97 9 USB DONGLE D107 SYNCN GND R57 J48 CLK RST/ PWR 1p8V REG 5 D49 RST/PWR D50 D108 TX DIS J104 U12 R57 C249 TX DIS U112 R548 REFCLK0n R546 RST/PWR R539 C127 7 K3 D109 TCK TMS TDI U40 HSTXBn SW15 U16 R56 MDC INPUT MDIO JMP102 SEC_OSC R56 K4 CLKB SW18 C43 7 5 MDC OUTPUT K1 MDIO PRI_REF (30.72MHZ) (31.25MHZ) D102 SEC_REF EXT SMA U115 PRI_REF_IN_P U100 1p8V R57 R56 K2 PLL_LOCK (STATUS 0) 2p5V EN SCL HSTXBp R696 R697 R695 R698 9 JMP50 D103 CLKA SDA STATUS 1/PIN0 D101 INT1 DIS SEC_OSC CLK GEN SPI_LE1/PIN3 RESET1 SPI_MOSI/PIN1 INT2 SPI_MISO/PIN2 PRI_OSC SPI_CLK/PIN4 RESET2 STATUS 1 PRI_REF_IN_N R785 C681 C680 C679 C678 R57 J101 R688 J2 OUTB0N / OUTA4N / CLKB0P R 2 J20 R 19 R2 0 LS_OK_IN_A LS_OK_OUT_A LS_OK_IN_B LS_OK_OUT_B INB0P / INA4P / CLKA3N INA3N R784 R694R693 OUTA3P HIGH R699 C693 R783 PRI_OSC R701R700 J103 C654 C670 JMP2 J21 J3 J4 J22 INB0N / INA4N / CLKA3P JMP1 J23 J5 GND GND C667 C668 R702 R782 C692 U114 R689 R691 U105 INA3P R 1 14 LOW R690 R692 JMP3 OUTB0P / OUTA4P / CLKB0N OUTA3N R INB1N / INA5N / CLKA2P 5 INB1P / INA5P / CLKA2N 11 12 R J24 R 23 24 INA2N 29 J28 R R INA1N INA1P INA2P 30 OUTA1P OUTA2P J29 J30 J26 OUTA1N OUTB2P / OUTA6P / CLKB2N J13 J12 J31 J25 INB2N / INA6N / CLKA1P INB2P / INA6P / CLKA1N OUTB2N / OUTA6N / CLKB2P J11 R R J10 J27 OUTA2N MDC MDIO OUTB1P / OUTA5P / CLKB1N J9 J8 OUTB1N / OUTA5N / CLKB1P J7 R 6 J6 INB3P / INA7P / CLKA0N 15 OUTB3N / OUTA7N / CLKB3P R 17 R 18 34 INA0N R R 36 35 J34 J35 OUTA0P OUTA0N CHA_CLKOUTP / CLKA1P_IN J36 TLK10xxx SMA BREAKOUT BRD 6568779 REV N/A J32 R 33 R J33 INA0P CHB_CLKOUTP / CLKB1N_IN J19 J37 CHA_CLKOUTN / CLKA1N_IN J18 OUTB3P / OUTA7P / CLKB3N CHB_CLKOUTN / CLKB1P_IN J17 J16 INB3N / INA7N / CLKA0P J15 R 16 R J14 Test and Setup Configurations www.ti.com +5V P1 1p5/8V JMP35 JMP41 C138 C139 +5V C140 TLK10xxxEVM MOTHER BOARD REGULATOR Rev B DISABLE 6566789 EN C84 DIS D28 5V SPI_LE2 C98 C95 C94 D11 1p0V_A2 REG R582 J44 JMP42 J43 J100 VOLTAGE MONITOR DONGLE REFCLK1p 1p0V_D1 REG U1 HSRXBn CLKOUTBn CLKOUTAp C121 1p0V_D2 REG C120 C119 C80 R629 R630 22 23 Figure 6. TLK10xxx EVM Motherboard and SMA Breakout Board for Clock Channels SLLU187 – November 2013 Submit Documentation Feedback GND Test and Setup Configurations www.ti.com J103 R688 R694R693 R690 R692 R689 R691 U105 1p5V / 1p8V Selection R701R700 R699 1p8V P14 BJ 5V PLUG JMP35 1p5V GND 1p5/8V U12 C32 C139 Power Supply Banana Jack / Plug Selection JMP41 C138 C140 +5V SW17 P1 C93 D28 C95 +5V P26 5V C94 C98 TLK10xxxEVM MOTHER BOARD REV B 6566789 EN R56 9 R57 R57 5 R56 7 7 R57 R56 9 5 R57 DIS 1p0V_D1 REG R57 3 1 C121 1p0V_A2 REG C24 C74 3p3V_CLK REG U16 C29 3P3V_CLK 3P3V 1P8V 1P5V 1P0V_D2 1P0V_D1 1P0V_A2 1P0V_A1 REGULATOR DISABLE 3p3V REG U101 C604 C120 R630 C119 R629 1p0V_D2 REG R631 R628 R633 R627 C84 C91 C67 C64 C71 C46 C108 C90 C600 C22 1p5V REG C89 C117 C618 U24 C115 U22 U64 22 23 R625 R626 R632 C611 C619 C616 C118 MAIN RESET C114 U10 C607 C617 C622 C124 SW10 C107 C623 C620 C43 C97 RESET D11 2 C621 1p8V REG C130 C99 D10 4 C654 C670 C628 C129 GND R57 U102 H10 PRBSEN TESTEN GPIO MDIO_B2B_RLY MDIO_CON_RLY I2C_GPIO_ADDR C109 R57 C87 C111 PDTRXA PDTRXB M9 0 C110 C80 LOW HIGH JMP100 C85 C86 6 C667 C668 C681 C680 C679 C678 C629 C127 CLK PDN JMP42 RST RST BTN R57 R57 1p0V_A1 REG C15 U42 GND LOSA 12C_LS_EN LOSB C17 R696 R697 R695 R698 U100 CLK SYNCN SW13 PDN PDN AMUXA PRBS PASS U114 SEC_OSC J102 C624 C125 VOLTAGE MONITOR DONGLE 8 8 LOW R785 R784 D111 CLKA CLK BUFFER INPUT CLKB SW18 SW14 C625 C626 C128 RESET J100 R57 R56 PRI_OSC R782 C692 HIGH C693 R783 SPI_LE2 SPI_CLK/PIN4 SPI_LE1/PIN3 D101 CLK RST/ PWR U108 0 6 U41 U8 AMUXB SW11 C627 C113 GND Control Pin Configuration Clock Fanout Signals C123 R58 R56 C672 D105 D104 D12 C673 R687R686 SW15 SYNCN D13 R684 C671 C674 C675 C676 C677 U110 LOSB LOSA R685 C683 R703 C684 C100 LS_OKINA JMP48 D110 R712 R704 R713 C682 U112 J44 SYNCN GND LOSA/B PRBS PASS LEDs U115 EXT SMA D107 D106 J41 D16 LS_OKINB REF_SEL SI_MODE0 SI_MODE1 SW16 PRI_REF_IN_P C101 JMP61 IN DIS RST/PWR RST/PWR PLL_LOCK (STATUS 0) D108 D109 J43 REFCLK1p GND OUT Clock Generator I2C/ Pin Control Selection R781R780 SEC_OSC CLK GEN PRTAD0 LS_OK_IN/ OUT Header SPI_MISO/PIN2 PRI_OSC R777 PRI_REF_IN_N SW19 PRI_REF (30.72MHZ) (31.25MHZ) SEC_REF EN D103 D102 REF CLK1n J72 PRBS PASS JMP101 CLKOUTAp D15 D14 J45 SFP+ TX_DIS LS_OK OUT_B LS_OK OUT_A JMP36 JMP62 MOD DETECT U92 SPI_MOSI/PIN1 R582 J42 REF CLK0p RX_LOS D48 3p3V JTAG_V PRTAD4 PRTAD3 PRTAD2 PRTAD1 REFCLK0n GND TLK 10002 TLK 10232 U1 TX DIS JMP105 D51 CLKOUTAn TX_FAULT D52 R553 J46 R549 D50 R548 R539 STATUS 1/PIN0 J6 HSTXBn R581 HSTXBp D100 JMP47 LOW HIGH PRTAD Configuration GND J5 MDIOV JTAG GND JMP77 TX DIS D49 SW12 HSRXBp I2C 2p5V 3p3V R546 TCK TMS TDI U40 CLKOUTBp J47 J73 SCL JMP102 JTAG Header JTAG Level Shift Voltage C247 J48 RESET1 CLKOUTBn INT1 2p5V TDO J7 K4 USB DONGLE INT2 RESET2 SDA TRST HSRXBn C249 K2 K3 I2C Header STATUS 1 External Input for Clock Generator J104 JMP104 J8 MDC INPUT MDIO MDC OUTPUT K1 MDIO USB Dongle Channel A SFP+ TX Disable On-board/ External Reference Clock Selection Oscillator Enable JMP50 JMP103 J101 MDIO Level Shift Voltage Clock Generator Pin Control MDIO Input Header R702 MDIO Output Header Clock connections for external source Channel B HS TX/RX Signals Channel A/B Clock outputs Channel A HS TX/RX Signals Power Supply Connectors Q100 Channel A/B LS TX/RX Signals Voltage Monitor Main Board Reset Clock Generator Powerdown, Reset, and Sync Regulator Disable Figure 7. TLK10xxx EVM Board Features SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 15 TLK10xxx EVM Motherboard Schematics 11 www.ti.com TLK10xxx EVM Motherboard Schematics Figure 8 through Figure 22 show the EVM motherboard schematics. 5 4 3 2 1 REVISIONS NOTES: ECR NUMBER ECR DATE ------- xx/xx/xx 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS . 2. PLACE ALL PARTS OTHER THAN SMP CONNECTORS ON A 0 OR 90 DEGREE ORIENTATION . 3. SERIAL DATA SHOULD BE ROUTED AS SINGLE -ENDED 50 OHM TRANSMISSION LINES ON OUTSIDE LAYERS. ROUTING DISTANCE SHOULD BE 3 INCHES OR LESS. 4. USE ROGERS MATERIAL FOR OUTSIDE LAYERS AND FR 4-370 MATERIAL FOR INSIDE LAYERS . 5. SERIAL AND REFCLK NETS MUST MATCH WITHIN +/- 0.5 MILS D D 6. MATCH DIFFERENTIAL TRACE WIDTHS OF SERIAL AND REFCLK LINES WITH SMP /SMA PADS . 7. PLACE TI LOGO IN TOP SIDE METAL SCHEMATIC SHEET INDEX: SHEET 01: SHEET 02: SHEET 03: SHEET 04: SHEET 05: SHEET 06: SHEET 07: SHEET 08: SHEET 09: SHEET 10: SHEET 11: SHEET 12: SHEET 13: SHEET 14: SHEET 15: C TLK10XXX CHAR COVER SHEET AND NOTES 1P0V REGULATORS 1P5V, 1P8V, 2P5V, 3P3V REGULATORS POWER DISTRIBUTION VOLTAGE MONITORING DEVICE POWER AND GROUND GLOBAL SIGNALS MDIO,JTAG, AND I2C INTERFACE CLOCKS CLOCK CONTROL CRYSTAL OSCILLATORS LOW SPEED DATA SIGNALS HIGH SPEED DATA SIGNALS DATA BOARD TO BOARD CONNECTOR CLOCK BOARD TO BOARD CONNECTOR C B B TEXAS INSTRUMENTS A A SCHEMATIC TITLE TLK10XXX EVM MOTHER BOARD ENGINEER J. NERGER DATE 01/30/13 PAGE TITLE LAYOUT TLK10XXX DATA SHEET REVISION : x.x.x DFW TEST DATA SHEET LAST UPDATED ON : xx/xx/xx RELEASED J. NERGER 5 4 3 DATE 01/30/13 DATE 01/30/13 2 COVER PAGE AND NOTES SIZE DOCUMENT NUMBER REV B 6566789 NA 1 SHEET of 15 1 Figure 8. TLK10xxx EVM Schematic, Sheet 1 of 15 Cover Page and Index 16 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 2 1 1.0V ANALOG REGULATOR 2 1.0V ANALOG REGULATOR 1 U101 GND GND_PP 12 21 NC1 NC2 NC3 68uF 10uF 1uF C604 C606 1.13K TPS74401RGW TH6 TH5 C605 C602 R602 1uF 4.99K 4.7uF 100uF C601 C20 C600 1uF 68uF 10uF C18 R603 12 21 GND GND_PP C603 0.001uF 4.02K TH2 16 FB 2 3 4 R604 R52 TH1 D 13 14 17 NC4 NC5 NC6 SS 1P0V_A2 9 PG EN 15 1P0V_A2_REG_EN TPS74401RGW C21 0.001uF BIAS 11 1 18 19 20 OUT1 OUT2 OUT3 OUT4 4.02K NC1 NC2 NC3 1.13K 16 FB 2 3 4 C17 SS IN1 IN2 IN3 IN4 10 1P0V_A_REG_SS 1P0V_A_REG_SS C19 1P0V_A1_REG_EN 13 14 17 NC4 NC5 NC6 EN 15 9 PG 5 6 7 8 5V 1P0V_A1 R50 BIAS 11 1 18 19 20 OUT1 OUT2 OUT3 OUT4 1P0V_A_REG_ADJ 1uF 4.99K 10 R49 C16 C15 100uF D 4.7uF 5V IN1 IN2 IN3 IN4 1P0V_A_REG_ADJ U8 5 6 7 8 1P0V_A_REG1_TRIM R600 88.7 1P0V_A_REG2_TRIM R605 88.7 C C SW17 2 4 6 8 10 12 14 16 1 3 5 7 ON 9 11 13 15 1P5V_REG_EN 1P8V_REG_EN 3P3V_REG_EN 3P3V_CLK_REG_EN 3 3 3 3 Rocker Switch 8 position 1.0V DIGITAL REGULATOR 2 1.0V DIGITAL REGULATOR 1 GND GND_PP 16 12 21 TPS74401RGW C610 0.001uF TH8 1P0V_D1_REG_EN 2 3 4 FB NC1 NC2 NC3 GND GND_PP TH4 10uF 1uF C25 C27 16 12 21 MUST USE TPS74401 3A LDO TH3 1.13K 13 14 17 TPS74401RGW C28 0.001uF 1P0V_D_REG2_TRIM A NC4 NC5 NC6 SS B 68uF EN 9 1P0V_D1 C24 C26 15 PG 1 18 19 20 R67 1uF 4.99K R66 4.7uF C23 100uF C22 1uF C613 10uF C612 68uF 1.13K 11 OUT1 OUT2 OUT3 OUT4 BIAS R608 TH7 10 IN1 IN2 IN3 IN4 1P0V_D_REG_ADJ FB NC1 NC2 NC3 13 14 17 C611 NC4 NC5 NC6 SS 5V R69 2 3 4 EN 9 5 6 7 8 1P0V_D_REG_SS 1P0V_D2_REG_EN PG 1P0V_D2 R607 15 BIAS 1 18 19 20 1P0V_D_REG_ADJ 1uF 11 1P0V_D_REG_SS R606 10 C609 4.99K 4.7uF C608 C607 100uF B U10 OUT1 OUT2 OUT3 OUT4 4.02K 5V IN1 IN2 IN3 IN4 4.02K U102 5 6 7 8 R609 88.7 1P0V_D_REG1_TRIM R601 88.7 A TEXAS INSTRUMENTS PAGE TITLE 1P0V REGULATORS SIZE B 5 4 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 2 of 15 1 Figure 9. TLK10xxx EVM Schematic, Sheet 2 of 15 1p0V Regulators SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 17 TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 2 3.3V CLK REGULATOR 3.3V REGULATOR U22 12 21 TPS74401RGW C77 10pF TH10 2 3 4 FB NC1 NC2 NC3 GND GND_PP 16 12 21 TPS74401RGW C70 10pF TH12 TH11 C GND GND_PP C35 0.015uF 1P8V_REG_EN FB NC1 NC2 NC3 GND GND_PP 16 12 21 TPS74401RGW C49 0.015uF TH15 TH16 10uF 1uF C69 10uF 1uF C47 C48 SS B R120 TH14 2 2 3 4 9 13 14 17 3.57K PG NC4 NC5 NC6 EN 68uF 15 BIAS 1P8V C46 11 1 18 19 20 R118 1uF R117 C44 C45 4.99K 4.7uF 100uF C43 1uF C34 10uF 68uF 4.12K 12 21 TPS74401RGW TH13 10 OUT1 OUT2 OUT3 OUT4 16 FB NC1 NC2 NC3 C33 SS C32 13 14 17 R84 9 PG NC4 NC5 NC6 EN IN1 IN2 IN3 IN4 1P8V_REG_ADJ 1P5V_REG_EN B BIAS 5 6 7 8 5V 1P5V 1P8_VREG_SS 1P5V_REG_SS 2 3 4 1 18 19 20 OUT1 OUT2 OUT3 OUT4 1P5V_REG_EN_ADJ 15 68uF U16 IN1 IN2 IN3 IN4 4.53K 1uF C31 4.99K R83 100uF 4.7uF C30 C29 2 11 C68 C 1.8V REGULATOR U12 10 3 3 1.5V REGULATOR 5 6 7 8 R611 3P3V_REG_TRIM R610 3P3V_CLK_REG_TRIM 5V 3.57K NC4 NC5 NC6 SS D 9 13 14 17 C67 EN 3P3V R169 4.99K R168 1uF 4.7uF C65 C66 100uF C64 1uF 68uF 3.57K 10uF C75 C76 3P3V_REG_EN PG R188 TH9 2 15 BIAS 1 18 19 20 3P3VREG_ADJ GND GND_PP 11 OUT1 OUT2 OUT3 OUT4 R171 16 FB NC1 NC2 NC3 C74 NC4 NC5 NC6 SS 10 IN1 IN2 IN3 IN4 2.8K 2 3 4 EN 13 14 17 5 6 7 8 5V 3P3VREG_SS 3P3V_CLK_REG_EN 9 PG R186 15 BIAS 3P3V_CLK 3P3V_C_REG_ADJ 11 1 18 19 20 OUT1 OUT2 OUT3 OUT4 1.13K 4.99K R185 1uF 4.7uF C72 C73 100uF 10 3P3V_C_REG_SS 2 C71 D IN1 IN2 IN3 IN4 1.13K U24 5 6 7 8 5V 1 R613 R86 1P8V_REG_TRIM 1P5V_REG_TRIM R612 0 47 5V 2P5V R616 C614 1uF 2P5V_LED IN GND EN OUT NC 4 TLV70225 2P5V_EN GREEN 2 4.99K 5 C615 1uF A D100 1 2 3 R614 A 250 U103 1 3P3V TEXAS INSTRUMENTS R615 PAGE TITLE DNI_4.99K 1P5V, 1P8V, 2P5V, 3P3V REGULATORS PLACE NEAR MDIO LEVEL SHIFTER (U43) SIZE B 5 4 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 3 of 15 1 Figure 10. TLK10xxx EVM Schematic, Sheet 3 of 15 1p5V, 1p8V, 2p5V, and 3p3V Regulators 18 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 2 1 3P3V_CLK 3P3V_CLK CLK_VDD_PLL PLANE FILTERING / BULK DECOUPLING 1uF 0.1uF 0.01uF C632 C633 1P5/8V 1P0V_A1 L2 1P5V 1P8V 0.1uF C86 0.01uF 1uF C85 C87 10uF C80 1uF 0.1uF C95 0.01uF 10uF C93 C94 C98 0.01uF 0.1uF 0.1uF 0.01uF C101 1P0V_D2 0.01uF 0.1uF C110 C111 1uF 0.1uF C120 0.01uF 1uF INSTALL 0-OHM RESISTOR C121 10uF Ferrite Bead_1210 C119 0.01uF 0.1uF 1uF 2 C125 C124 C118 10uF DVDD 1 10uF Ferrite Bead_1210 C107 L7 VDDRB_HS INSTALL 0-OHM RESISTOR C109 0.01uF 0.1uF C114 INSTALL 0-OHM RESISTOR 2 C123 10uF 1 C Ferrite Bead_1210 L8 2 0.1uF VDDD 2 C117 1P5/8V C113 C108 CLK_VDD_OUTB L103 C623 C100 10uF Ferrite Bead_1210 1uF 1 INSTALL 0-OHM RESISTOR C622 L5 1 2 C115 1 10uF 10uF 0.1uF 2 C621 C620 1P0V_D1 VDDRB_LS 3 3P3V_CLK BLM15HD102SN1D Ferrite Bead_1210 INSTALL 0-OHM RESISTOR L6 JMP35 3 Pin Berg 1 VDDT 2 1P5/8V 1P5/8V C C99 C97 L102 2 L3 1 INSTALL 0-OHM RESISTOR BLM15HD102SN1D C91 C84 1P0V_A2 VDDRA_HS CLK_VDD_OUTA 1 Ferrite Bead_1210 2 Ferrite Bead_1210 3P3V_CLK 2 INSTALL 0-OHM RESISTOR L4 1 1uF 10uF 0.1uF C618 C619 1P5/8V C89 INSTALL 0-OHM RESISTOR 2 C90 10uF CLK_VDD_PLL_A L101 BLM15HD102SN1D VDDA 1 2 Ferrite Bead_1210 3P3V_CLK 1 L1 VDDRA_LS D 1 1uF 10uF C631 10uF C616 D C617 BLM15HD102SN1D 0.1uF 2 C630 L100 1 3P3V_CLK CLK_VDD_IN 1P5/8V L9 VDDO B 0.01uF 0.1uF INSTALL 0-OHM RESISTOR C130 C129 Ferrite Bead_1210 1uF 2 10uF 1 C127 10uF 0.1uF BLM15HD102SN1D C625 2 C624 1 C128 L104 B 3P3V_CLK CLK_DVDD L105 P1 GND 5V_BJ 1 NOTE: PLACE GND BANANA JACKS 750 MIL P14 1 CENTER TO CENTER SPACING WITH A POWER BANANA JACK LOCATED BETWEEN TWO POWER JACKS AND OFFSET DIAGONALLY. L14 JMP41 3 1uF 0.1uF 0.01uF C140 5V_BARREL 0.1uF 10uF C628 P26 SLEEVE 3 C629 BLM15HD102SN1D A INSTALL 0-OHM RESISTOR C139 3 Pin Berg BAT60A 10V, 3A C138 5V_DIODE Ferrite Bead_1210 2 2 10uF 1 L106 1 1 68uF 2 5V_SOURCE C137 CLK_VCC A 2 D9 3P3V_CLK 5V 1 5V_BJ C136 C626 10uF BLM15HD102SN1D 0.1uF 2 C627 1 1 TEXAS INSTRUMENTS PAGE TITLE TIP SHUNT 2 POWER DISTRIBUTION SIZE RAPC722 SILK = +5V 5 4 B 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 4 of 15 1 Figure 11. TLK10xxx EVM Schematic, Sheet 4 of 15 Power Distribution SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 19 TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 2 1 NOTE: 1P0V_A1 1P0V_A2 5V 1P0V_D1 1P0V_D2 D D NOTE: 1P5V 10uF 10uF C635 C636 10uF 10uF C634 PLACE DECOULING CAPS NEAR J100 CONNECTOR C637 1P8V 2P5V 3P3V VDDRA_HS VDDRB_LS VDDRB_HS 1.2K C R371 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 5V_L 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 2 VDDRA_LS 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 BLUE 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 5V D28 DVDD VDDO 2 4 6 8 10 12 14 16 18 20 1 VDDD J100B 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 MEC1-130-02-F-D-A Connector VDDT C J100A 1 3 5 7 9 11 13 15 17 19 MEC1-130-02-F-D-A Connector 5V VDDA 3P3V_CLK B B CLK_VDD_PLL CLK_VDD_PLL_A CLK_VDD_OUTA CLK_VDD_OUTB CLK_VDD_IN A A CLK_DVDD TEXAS INSTRUMENTS CLK_VCC PAGE TITLE VOLTAGE MONITORING SIZE B 5 4 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 5 of 15 1 Figure 12. TLK10xxx EVM Schematic, Sheet 5 of 15 Voltage Monitoring 20 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 2 1 NOTES: TLK10XXX DEVICE POWER / LOCAL DECOUPLING DECOUPLLING GENERAL GUIDELINES: VDDA 1. PLACE CAPACITORS SUCH THAT SMALLER VALUE CAPACITORS ARE NEARER THE DUT AND THEN SUCCESSIVELY PLACE LARGER VALUE CAPACITORS AS YOU MOVE AWAY FROM THE DUT. VDDO NOTE: PLACE CAPACITORS NOTE: PLACE CAPACITORS NEAR TLK10XXX DEVICE VDDO NEAR TLK10XXX DEVICE 0.1uF D C149 TLK10xxx 0.1uF K7 C7 0.1uF 0.1uF 0.1uF C145 C146 1P5_8V_VDDO1 1P5_8V_VDDO0 C147 0.1uF C144 U1S C148 0.1uF 0.1uF CDCM6208 DEVICE POWER / LOCAL DECOUPLING C142 D D2 F2 G2 J2 F11 G10 C143 1P0V_VDDA_LS_HS1 1P0V_VDDA_LS_HS2 1P0V_VDDA_LS_HS3 1P0V_VDDA_LS_HS4 1P0V_VDDA_LS_HS5 1P0V_VDDA_LS_HS6 0.1uF U1K C141 2. PLACE CAPACITORS NEAR VIAS AND CONNECTORS. THESE CAPACITORS SHOULD DECOUPLE THE DRIVER SUPPLY TO THE GROUND PLANE. IF A SIGNAL IS REFERENCED TO A POWER PLANE AND THIS POWER PLANE IS NOT ASSOCIATED WITH THE DRIVER SUPPLY, THEN THIS PLANE SHOULD ALSO BE DECOUPLED TO GROUND NEAR ALL ASSOCIATED VIAS AND CONNECTORS. VDDA TLK10xxx VDDT CLK_VDD_PLL VDDT 0.1uF C150 0.1uF NOTE: PLACE 0.1uF 0.1uF C168 E11 C163 0.1uF C167 TLK10xxx C CAPACITORS NEAR 1P5_8V_VDDRA_HS 0.1uF CLK_VDD_OUTA VDDRA_HS U1P 0.1uF C640 TLK10XXX DEVICE TLK10XXX DEVICE E6 E8 F6 H6 H8 1P0V_VDDD1 1P0V_VDDD2 1P0V_VDDD3 1P0V_VDDD4 1P0V_VDDD5 CDCM6208 DEVICE C639 0.1uF U1M NOTE: PLACE CAPACITORS NEAR CDCM6208 DEVICE VDDD NOTE: PLACE CAPACITORS NEAR 30 CDCM6208 NOTE: PLACE CAPACITORS NEAR CAPACITORS NEAR C166 0.1uF 0.1uF VDD_Y5 CDCM6208 NOTE: PLACE VDDRA_HS VDDD C164 38 39 VDD_PLL2 VDD_VCO C C152 27 CDCM6208 U100E U100H C3 C153 TLK10xxx VDD_Y4 CLK_VDD_PLL_A 1P5_8V_VDDRA_LS TLK10xxx CDCM6208 U100D CDCM6208 DEVICE 0.1uF 13 18 U1O C151 C638 VDD_Y0 VDD_Y1 NOTE: PLACE CAPACITORS NEAR CLK_VDD_PLL_A 1P0V_VDDT_LS_HS1 1P0V_VDDT_LS_HS2 1P0V_VDDT_LS_HS3 U100B F4 G4 F9 0.1uF 37 VDD_PLL1 CDCM6208 VDDRA_LS TLK10XXX DEVICE U1L 0.1uF U100I VDDRA_LS NOTE: PLACE CAPACITORS NEAR CLK_VDD_OUTA C165 CLK_VDD_PLL TLK10XXX DEVICE TLK10xxx VDDRB_LS DVDD NOTE: PLACE CAPACITORS NEAR K3 C169 0.1uF 0.1uF 0.1uF 0.1uF NOTE: PLACE CAPACITORS NEAR TLK10xxx TLK10XXX DEVICE VDDRB_HS 0.1uF C174 CLK_VDD_OUTB C173 TLK10xxx C171 VDDRB_HS C170 CDCM6208 DEVICE C642 C641 NOTE: PLACE CAPACITORS NEAR E7 F7 G6 G8 H7 1P0V_DVDD1 1P0V_DVDD2 1P0V_DVDD3 1P0V_DVDD4 1P0V_DVDD5 CDCM6208 1P5_8V_VDDRB_LS TLK10XXX DEVICE 0.1uF C646 C647 C645 0.1uF 0.1uF 7 10 VDD_PRI_REF VDD_SEC_REF C644 U100A 0.1uF DVDD U1N C172 0.1uF CLK_VDD_IN 0.1uF 0.1uF CLK_VDD_IN 0.1uF VDDRB_LS U1Q U1R 1P5_8V_VDDRB_HS J11 NOTE: PLACE B B CAPACITORS NEAR U100C CLK_DVDD 48 0.1uF DVDD TLK10xxx VDD_Y2 VDD_Y3 CLK_DVDD U100J CDCM6208 19 24 1P0V_VPP CDCM6208 U100F TLK10xxx VDD_Y6 C643 CDCM6208 DEVICE 31 D7 TLK10XXX DEVICE GROUND U1U VDD_Y7 A2 A5 A11 B3 B4 B7 B11 C1 C6 C12 D3 D5 D10 D11 E2 E4 F1 F5 F8 F10 F12 34 CDCM6208 NOTE: PLACE CAPACITORS NEAR CDCM6208 DEVICE CLK_VDD_OUTB CDCM6208 DEVICE GROUND 0.1uF 0.1uF 0.1uF 0.1uF C648 C650 C651 GND 49 C649 A U100K CDCM6208 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 G1 G3 G5 G7 G11 H2 H4 H11 J5 J12 K1 K6 K11 L3 L4 L7 L11 M2 M5 M12 A TEXAS INSTRUMENTS PAGE TITLE DEVICE POWER, GROUND, LOCAL DECOUPLING SIZE B TLK10xxx 5 4 TLK10XXX DEVICE U1T CDCM6208 U100G NOTE: PLACE CAPACITORS NEAR C188 DVDD 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 6 of 15 1 Figure 13. TLK10xxx EVM Schematic, Sheet 6 of 15 Device Power, Ground, and Local Decoupling SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 21 TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 VDDO 2 3P3V VDDO 100K 130 4 130 MAIN RESET TPS3125J18 3P3V BI-DIRECTIONAL 5 R466 I2C_MAIN_RESET 0 SW10 PUSHBUTTON 1 MAIN_RST_SIGNAL 2 3 LEVEL SHIFTER I2C_PRBSEN_LS I2C_LS_OK_IN_A/RXCTRL_0_LS I2C_LS_OK_IN_B/RXCTRL_1_LS I2C_PDTRXB_N I2C_ST/GPI1 I2C_MODE_SEL/REFCLK_SEL I2C_PRBSEN I2C_LS_OK_IN_A/RXCTRL_0 I2C_LS_OK_IN_B/RXCTRL_1 R258 C1 20K R259 C2 20K VDDO DNI_4.99K DNI_4.99K I2C_LOSB_LS I2C_PRBS_PASS_LS I2C_LS_OK_OUT_A/GPO0_LS I2C_LS_OK_OUT_B/GPO1_LS I2C_LS1_EN TXB0108PWR 11 11 20 19 18 17 16 15 14 13 12 11 I2C_LOSA I2C_LOSB RESISTOR R621 R622 PADS R625 R626 B1 VCCB B2 B3 B4 B5 B6 B7 B8 GND U42A 0 0 I2C_LOSA/MDIO_C_RLY I2C_LOSB/MDIO_B_RLY I2C_PRBS_PASS I2C_LS_OK_OUT_A/GPO0 I2C_LS_OK_OUT_B/GPO1 I2C_DIS_FET 1 2 3 4 5 6 7 8 R629 R630 P00 P01 P02 P03 P04 P05 P06 P07 MAIN_/RST_C 5 C I2C DISABLE HEADER JMP100 1 2 I2C_LS_EN 0 0 2 Pin Berg TCA6424 Q100 PRI_OSC_EN SEC_OSC_EN I2C_DIS_FETG R632 G 0 FDV301N JMP61 VDDO 1 3 5 7 LS_OK_IN_A/RXCTRL_0 LS_OK_IN_B/RXCTRL_1 2 4 6 8 LS_OK_OUT_A/GPO0 B LS_OK_OUT_B/GPO1 Header 4x2 FDV301N FDV301N Header 5x2 5 4 250 250 0 0 14 14 LS_OK_OUT_B_CONNECTOR 14 14 LS_OK_OUT_A_CONNECTOR LS_OK_IN_B_CONNECTOR R282 GREEN 2 D15 D15_2 R281 GREEN 2 D14 D14_2 R277 R274 Q5 G 1 D15_1 Q7 LS_OK_IN_A_CONNECTOR 3 FDV301N TEXAS INSTRUMENTS D 2 4 6 8 10 G S S AMUXA 1 3 5 7 9 R619 R620 D PRBS_PASS A S 1 D16_1 JMP48 LOSB AMUXB FDV301N MDIO_B2B_RELAY MDIO_CON_RELAY I2C_GPIO_ADDR 1 GPIO D14_1 TESTEN D PRBSEN 2 4 6 8 10 12 14 16 18 20 LS_OK_OUT_B_G MODE_SEL/REFCLK_SEL LS_OK_OUT_A_G R617 R618 R262 R263 ST/GPI1 G S S PDTRXB_N LOSA Q6 1 3 5 7 9 ON 11 13 15 17 19 PDTRXA_N 49.9K 49.9K R284 GREEN 2D16_2 D16 D13_1 D Q4 G G TLK10xxx 7,8 7,8 8 5V R254 R255 250 250 R280 RED D13 1 2D13_2 250 0 R279 2D12_2 RED 1 D12_1 LOSB_G D LOSA_G Q3 5V SW11 D12 R278 R273 A B10 L8 D9 H9 LS_OK_IN_A / RXCTRL_0 LS_OK_IN_B / RXCTRL_1 LS_OK_OUT_A / GPO0 LS_OK_OUT_B / GPO1 5V 0 0 5V DNI_4.99K DNI_4.99K DNI_4.99K DNI_4.99K 5V TLK10xxx 49.9K 49.9K U1E R275 B H5 A8 J4 M9 H10 B9 L10 J10 E9 K8 J9 C11 D4 PRBS_PASS_G RESET_N PDTRXA_N PDTRXB_N ST / GPI1 MODE_SEL / REFCLK_SEL PRBSEN TESTEN GPI0 LOSA LOSB PRBS_PASS AMUXA AMUXB R247 R248 R249 R250 R251 R252 R253 U1F A1 VCCA A2 A3 A4 A5 A6 A7 A8 OE R623 R624 1 2 3 4 5 6 7 8 9 10 I2C_LOSA_LS R256 R257 49.9K 49.9K 49.9K 49.9K 49.9K 49.9K 49.9K 0 0 0 0 0 I2C-TO-GPIO INPUT PINS 3 S R276 R283 R285 R286 R287 VDDA OVERLAP 2 ZXTD09N50DE6 DNI_4.99K DNI_4.99K VDDO C278 1uF E2 R627 R628 LEVEL SHIFTER U41 DNI_4.99K DNI_4.99K DNI_0 DNI_0 3P3V BI-DIRECTIONAL MAIN_RST_C B2 VDDO MDIO_B2B_RELAY MDIO_CON_RELAY VDDO C279 1uF 4 MAIN_/RST_B 1 B1 E1 TXB0108PWR 7,8 7,8 C 6 MAIN_RST_B TCA6424 I2C_LS0_EN D10 U38 P10 P11 P12 P13 P14 P15 P16 P17 1 I2C_MODE_SEL/REFCLK_SEL_LS B3U-1100P U42B 9 10 11 12 13 14 15 16 I2C_PDTRXA_N 0 I2C_ST/GPI1_LS C275 1uF 20 19 18 17 16 15 14 13 12 11 R633 I2C_PDTRXB_N_LS B1 VCCB B2 B3 B4 B5 B6 B7 B8 GND D LS_EN_FETD I2C_PDTRXA_N_LS A1 VCCA A2 A3 A4 A5 A6 A7 A8 OE 4.99K 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 R631 R459 R460 R461 R462 R463 R532 R533 I2C-TO-GPIO OUTPUT PINS U64 C274 1uF R246 R244 VDDO /MR GREEN 2 3 Pin Berg VDD D11 D /RST GND RST 5V MAIN_/RST_L MAIN_RST C190 1uF C189 0.1uF R242 1 2 3 MAIN_/RST R245 4.99K 49.9K AND RESET MONITOR U37 49.9 MAIN_RST_L R243 MAIN_RESET_HS SN74AVCH1T45DBV 3 VOLTAGE SUPERVISOR 2 MAIN_RST_DIR RED RESET_N_LS R240 DNI_4.99K VCCB DIR B 1 1 2 VCCA GND A R465 0 JMP42 RESET_N C283 1uF 6 5 4 U36 1 2 3 R241 4.99K R486 R239 4.99K 5V 3P3V MAIN_RESET D 10 C282 1uF 1 3P3V FDV301N PAGE TITLE GLOBAL SIGNALS SIZE B 2 DOCUMENT NUMBER 6566789 REV NA PAGE 7 of 15 1 Figure 14. TLK10xxx EVM Schematic, Sheet 7 of 15 Global and Control Signals 22 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 2 1 DNI_4.02K DNI_4.02K R290 R291 DNI_0 DNI_0 R298 R299 MDIO_LS_BY MDC_LS_BY DNI_0 DNI_0 20 19 18 17 16 15 14 13 12 11 R636 B1 VCCB B2 B3 B4 B5 B6 B7 B8 GND R637 A1 VCCA A2 A3 A4 A5 A6 A7 A8 OE MDC_PRE_LS MDIO_PRE_LS OVERLAP RESISTOR PADS R308, R309, R636, R637 R308 R309 0 0 MDC_USB MDIO_USB 18 20 22 24 26 28 30 32 34 36 38 40 TXS0108EPWR BI-DIRECTIONAL 49.9K R642 DNI_0 5V_USB J101A J101B 2 4 6 8 10 12 14 2 4 6 8 10 12 14 1 3 5 7 9 11 13 18 20 22 24 26 28 30 32 34 36 38 40 17 19 21 23 25 27 29 31 33 35 37 39 MEC1-120-02-F-D-A Connector MDIO_LS_EN R638 DNI_4.99K 3P3V 1uF 4.99K 2 U43 5V R640 USB INTERFACE 3P3V_USB LEVEL SHIFTER 1 3 5 7 9 11 13 17 19 21 23 25 27 29 31 33 35 37 39 C Q103 D S R643 MDIO_B2B_R_INV G 49.9K 1 2 3 4 5 6 7 8 9 10 MDC_POST_LS MDIO_POST_LS PRTAD0 4.99K R641 D 4.99K 3P3V FDV301N SPI CONTROL INTERFACE Q104 G 7 MDIO_B2B_RELAY S R645 2 4 6 8 3P3V 100 MDIO_B2B_R 2 1 100 1 3 ON 5 7 5V_USB 3P3V_USB DNI_0 MEC1-120-02-F-D-A Connector PRTAD1 4.02K 4.02K R296 R297 PRTAD2 3P3V R644 MDIO_CON_R 4.02K PRTAD3 C286 1uF D 3P3V R639 R306 R307 T1 CTRL 4 PRTAD4 JMP101 Header 2x1 3P3V 4 3 1 Header 2x2 1 Header T 4pin TLK10xxx 3P3V MDIO_LS VDDO SW12 1 T2 GND CTRL T1 K4 AQY221R2T C M8 J6 L9 G9 E10 MDC_CON R298, R299 JMP77 JMP50 4 2 MDIO_CON PADS R293, R295, 2P5V MDIO_LS 3P3V R634, R635 PRTAD ADDRESS MDC_DUT 3 4 MDIO_B2B_CON MDC_B2B_CON MDIO_DUT R300 R301 R302 R303 R304 1 2 GND T2 3 14 14 PRTAD4 PRTAD3 PRTAD2 PRTAD1 PRTAD0 J7 J8 RESISTOR PADS 4.99K 4.99K 4.99K 4.99K 4.99K U1I MDIO MDC MDC_BYPASS DNI_0 DNI_0 OVERLAP RESISTOR R296, R297, VDDO R451 R491 2 1 (LEVEL SHIFTED) K3 AQY221R2T 4.02K RESISTOR PADS R293 R295 MDIO_BYPASS OVERLAP OVERLAP MDIO BUS OUTPUT CONNECTOR MDC DNI_0 DNI_0 C302 DO NOT R634 R635 MDIO R305 3 CTRL T1 K2 AQY221R2T 0 0 0 0 MDC_OUT_POST_LS R292 R294 0 0 MDC_HDR Header 2x2 R288 4 3 MDIO_OUT_POST_LS T2 GND D MDIO INTERFACE MDIO_HDR 4 1 3 2 4 MDIO_LS T1 CTRL GND T2 K1 AQY221R2T JMP103 R289 2 1 VDDO MDIO_CON_R_INV D S G FDV301N FDV301N R646 D Q101 FOR USE WITH CLOCK CONFIGURATION JMP102 Q102 G EXT_I2C_SCL 7 EXT_I2C_SDA S MDIO_CON_RELAY EXT_I2C_RESET1 B FDV301N EXT_I2C_INT1 EXT_I2C_RESET2 EXT_I2C_INT2 1 3 5 7 9 11 SPI_LE2 SPI_MISO 2 4 6 8 10 12 SPI_MOSI SPI_CLK SPI_LE1 10 10 10 10 10 B 3P3V Header 2x6 I2C BUS CONNECTOR 3P3V 3P3V VDDO TRST_N TDO TDI TMS TCK A TLK10xxx JTAG_LS_EN B1 VCCB B2 B3 B4 B5 B6 B7 B8 GND 3 Pin Berg TDO_LS TDI_LS TMS_LS TCK_LS 1 3 5 7 9 2 4 6 8 10 7 I2C_GPIO_ADDR 26 VCCP VCCI SCL SDA ADDR RESET 25 33 Header 5x2 GND PP INT 31 0 0 0 0 0 0 DNI_4.99K DNI_4.99K USB I2C BUS 29 30 I2C_GPIO_SCL R508 R509 0 0 I2C_SCL_SOURCE I2C_SDA_SOURCE R659 R660 0 0 USB_I2C_SCL I2C_GPIO_SDA 28 I2C_GPIO_RESET R510 0 I2C_RESET_SOURCE R661 0 USB_I2C_RESET1 32 I2C_GPIO_INT R511 0 I2C_INT_SOURCE R662 0 USB_I2C_INT1 R649 R650 DNI_0 DNI_0 I2C_RESET2_SOURCE R663 R664 0 0 USB_RESET2 TCA6424 TXB0108PWR R647 DNI_4.99K U42D 27 JMP47 JTAG_LS_VCCB TRST_N_LS 3P3V C281 1uF C280 1uF 4.99K 20 19 18 17 16 15 14 13 12 11 3P3V R657 R658 R270 E5 D6 C8 B8 D8 A1 VCCA A2 A3 A4 A5 A6 A7 A8 OE 1 2 3 JTAG_LS_VCCB_3V R648 4.99K TRST_N TDO TDI TMS TCK 1 2 3 4 5 6 7 8 9 10 0 C303 1uF U40 U1J R269 R651 R652 R653 R654 R655 R656 JTAG INTERFACE C304 1uF DNI_0 R476 R477 R472 R473 R268 DNI_2K DNI_2K DNI_4.99K DNI_4.99K JMP62 VDDO I2C_INT2_SOURCE USB_I2C_SDA A USB_INT2 TEXAS INSTRUMENTS I2C-TO-GPIO CONTROL PINS BI-DIRECTIONAL DO NOT OVERLAP 0-OHM RESISTOR PADS. PLACE I2C DEVICE ADDRESS 0x22 OR 0x23 LEVEL SHIFTER 0-OHM RESISTORS AS CLOSE TOGETHER AS PAGE TITLE POSSIBLE AND AS CLOSE TO THE TCA6424 DEVICE MDIO, JTAG, AND I2C INTERFACE TO MINIMIZE THE STUBS ON THE I2C BUS. SIZE B 5 4 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 8 of 15 1 Figure 15. TLK10xxx EVM Schematic, Sheet 8 of 15 USB, MDIO, JTAG, and I2C Interface SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 23 TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 2 1 NOTE: 1. MATCH REFCLK0/1_P/N AND CLKOUT0/1_P/N TRACE LENGTHS TO EACHOTHER CLK_VCC CLK_VCC R669 83 PADS C191, C193 C193 DNI_0.1uF REFCLK0P_U0P DNI_150 PADS C203, C205 0.1uF C663 C664 CLKA2P_CON 15 CLKA2N_CON 15 CLKA3P_CON 15 CLKA3N_CON 15 CLKB0P_CON 15 CLKB0N_CON 15 CLKB1P_CON 15 CLKB1N_CON 15 CLKB2P_CON 15 CLKB2N_CON 15 CLKB3P_CON 15 CLKB3N_CON 15 0.1uF 0.1uF 150 150 150 150 GND THERMAL PAD C665 0.1uF CLKA3P C666 130 130 15 0.1uF CLKA3N C SW18 0.1uF 2 4 REFCLK1N_SMP CLK_VCC ON 1 3 SMA SURFACE 1uF 0.1uF 5 C670 R688 83 83 CLKOUTAP C674 C675 VCC 8 VAC_REF C671 0.1uF C676 C668 0.1uF 6 7 CLKB_IN_P0 CLKB_IN_N_Y7N CLKB_IN_N0 130 J46 CLKB_IN_N1 CLKB1P_IN_CON CLKB1N_IN_CON C672 0.1uF C673 0.1uF A C206 0.1uF CHB_CLKOUTP_CONNECTOR 14 CHB_CLKOUTN_CONNECTOR 14 DNI_150 CLKOUTBN DNI_150 C202 DNI_0.1uF C204 DNI_0.1uF CLKOUTBP R694 PADS C200, C202 R693 C200 0.1uF C678 C679 0.1uF 0.1uF CLKB2N GND THERMAL PAD C680 CDCLVP1204 0.1uF CLKB3P C681 130 15 15 SMA SURFACE R692 CLKOUTBP OVERLAP CAPACITOR 130 J47 CLKOUTBP_SMA TLK10xxx 1 17 R691 A9 A10 B CLKB2P 15 16 OUTP3 OUTN3 R690 R689 R686 SMA SURFACE 13 14 OUTP2 OUTN2 INP1 INN1 83 C9 C10 3 4 CLKB_IN_P1 0.1uF 11 12 OUTP1 OUTN1 CLK_VCC CLKOUTAN CLKOUTAN_SMA 83 PADS C196, C198 R687 U1G OVERLAP CAPACITOR 130 CDCM6208 C198 0.1uF INP0 INN0 C677 CLKB1N 150 150 0.1uF 150 150 C667 R699 R700 CLKB_IN_P_Y7P 150 150 14 36 35 R701 R702 U100U Y7_N Y7_P 9 10 OUTP0 OUTN0 150 150 R685 R684 CHA_CLKOUTN_CONNECTOR 14 0.1uF CLKB1P IN_SEL R697 R698 CLKOUTAN CHA_CLKOUTP_CONNECTOR 2 CLKB_IN_SEL R695 R696 CLKOUTAP OVERLAP CAPACITOR PADS C192, C194 C194 0.1uF C196 0.1uF 0.1uF CLKB0N VAC_REF_B SMA SURFACE C192 0.1uF 0.1uF CLKB0P U105 C669 4.99K Rocker Switch 2 position J45 CLKOUTBP CLKOUTBN CLKA1N_CON C205 J44 CLKOUTAP_SMA CLKOUTAP CLKOUTAN 15 CLKA2N CDCLVP1204 CLK_VCC B CLKA1P_CON 0.1uF CLKA2P 15 16 R682 R683 83 13 14 OUTP2 OUTN2 INP1 INN1 C662 11 12 OUTP1 OUTN1 83 1 17 0.1uF CLKA1N OUTP3 OUTN3 R671 R670 C657 0.1uF C658 0.1uF C203 DNI_0.1uF OVERLAP CAPACITOR REFCLK1N 3 4 CLKA_IN_P1 R672 CLKA1N_IN_CON 15 R673 CLKA1P_IN_CON CLKA0N_CON D 9 10 R680 R681 R665 15 15 DNI_150 C199 0.1uF INP0 INN0 CLK_VCC 130 130 R667 REFCLK1P REFCLK1N DNI_150 REFCLK1N REFCLK1N_U1N DNI_150 CLKA_IN_N0 CLKA_IN_N1 PADS C199, C201 REFCLK1P_U1P C201 DNI_0.1uF CDCM6208 6 7 CLKA_IN_P0 R674 K9 K10 REFCLK1P REFCLK1P_SMP OVERLAP CAPACITOR R496 0.1uF REFCLK0P REFCLK0N TLK10xxx R497 C653 IN_SEL OUTP0 OUTN0 CLKA_IN_N_Y5N U1H M10 M11 REFCLK0P SMA SURFACE 32 33 0.1uF REFCLK0N_SMP J43 U100T C652 CDCM6208 SMA SURFACE REFCLK1P C CLKA_IN_P_Y5P 15 CLKA1P 150 150 0.1uF REFCLK0N Y6_P Y6_N 2 150 150 C197 28 29 R668 DNI_150 DNI_150 R498 Y5_N Y5_P J42 REFCLK0N R499 U100S CLKA0P_CON 0.1uF CLKA0N 0.1uF R666 C195 DNI_0.1uF OVERLAP CAPACITOR PADS C195, C197 VAC_REF_A C661 REFCLK0N_U0N 0.1uF C656 CLKA_IN_SEL CDCM6208 8 VAC_REF R676 R677 26 25 R675 Y4_P Y4_N C660 VCC R678 R679 U100R 5 83 OVERLAP CAPACITOR D C191 0.1uF C659 CLKA0P U104 C655 4.99K REFCLK0P_SMP SMA SURFACE C654 REFCLK0P 1uF J41 0.1uF CLKB3N A OVERLAP CAPACITOR PADS C204, C206 CLKOUTBN_SMA J48 CLKOUTBN TEXAS INSTRUMENTS SMA SURFACE U100P 20 21 Y0_P Y0_N CDCM6208 5 4 CDCM6208 U100O U100Q U100N Y2_P Y2_N 14 15 Y3_P Y3_N CDCM6208 3 PAGE TITLE 23 22 Y1_P Y1_N 17 16 CLOCKS SIZE B CDCM6208 2 DOCUMENT NUMBER 6566789 REV NA PAGE 9 of 15 1 Figure 16. TLK10xxx EVM Schematic, Sheet 9 of 15 Clocks 24 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Motherboard Schematics www.ti.com 2 1 JMP104 VOLTAGE SUPERVISOR PDN_/RST_B 6 OUTPUT PINS 1 R726 DNI_0 3P3V_CLK B3U-1100P CLOCK PDN PUSHBUTTON R723 2 4 6 8 7 5 VDD 4 PDN_RESET 1 2 3 /RST GND RST /MR PDN_/RST R731 PDN_RST_B C685 1uF AND 1 2 3 0 A VCC B GND Y 5 4 4 PDN_RESET_AND 3 E2 5 AND ISOLATE MAIN RESET WITH CLOCK POWER DOWN TO RESET REGISTER MAP R748 R749 2D109_2 RED D109 1 5V 100 100 CLOCK /RESET LED 5V SYNCN_/RST_B 6 SYNCN_PB 4 VDD /MR /RST GND RST R736 1 2 3 E1 SYNCN_/RST R739 C2 100K SYNCN_RST_B SYNCN_RST 4 CLOCK RESET LED 4 /MR /RST GND RST 1 2 3 E1 CLK_/RST R747 C2 100K CLK_RST CLK_RST_B 4 1 D108_1 B1 R745 R744 R742 R743 C688 CLK_RST_PB VDD 2 3 D109_1 B2 TPS3125J18 E2 5 D106_1 CLOCK RESET ZXTD09N50DE6 A 2 3 D107_1 5 PAGE TITLE CLOCK CONTROL SIZE ZXTD09N50DE6 4 100K 49.9 0.1uF 4.99K 0 R741 RED D107 1 1 U112 5 B PUSHBUTTON 5 6 TEXAS INSTRUMENTS E2 CLOCK SYNCN CLK_/RST_B B2 TPS3125J18 B3U-1100P VOLTAGE SUPERVISOR B PUSHBUTTON R737 C687 R735 U110 2 3 B1 AND RESET MONITOR 5 1 C1 100K AND RESET MONITOR SW15 B3U-1100P C1 100K VOLTAGE SUPERVISOR 2D107_2 R740 0.1uF R738 A D106 1 U111 100K 0 49.9 3P3V_CLK GREEN 2D106_2 CLOCK /RESET LED 3P3V_CLK U113 R746 CLOCK RESET LED SYNCN 3P3V_CLK 4.99K GREEN 2D108_2 SN74LVC1G08-Q1DBV 3P3V_CLK R734 5V 5V ZXTD09N50DE6 AND GATE USED TO CONNECT I2C_RESET/PWR RESET/PWR I2C_SYNCN 1 D105_1 MAIN_RESET B SW14 100 2 B2 TPS3125J18 49.9 U107 C2 100K PDN_RST D104_1 C E1 U108 0 SW13 2 3 I2C-TO-GPIO C686 R724 R725 P20 P21 P22 P23 P24 P25 P26 P27 1 B1 CDCM6208 2 3 R733 100 C1 100K AND RESET MONITOR I2C_CLK_PDN 1 3 ON 5 7 U109 R730 D108 1 R720 R721 R722 SPI_LE1 SPI_CLK SPI_LE2 D104 1 3P3V_CLK R727 0 0 0 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K R714 R715 R716 R717 R718 R719 PDN 8 8 8 8 8 SPI_MOSI SPI_MISO 3P3V_CLK 5 TCA6424 SW16 SI_MODE1 SPI_LE2_SOURCE 0 0 0 0 0 3 PDN_SWITCH 17 18 19 20 21 22 23 24 I2C_SI_MODE1 SI_MODE0 SPI_LE1_SOURCE/PIN3 SPI_CLK_SOURCE/PIN4 100 I2C_STATUS1 I2C_REF_SEL REF_SEL SPI_MISO_SOURCE/PIN2 5V 2D105_2 CLK_SPI_CLK/PIN4 R765 R766 R767 R768 R769 SPI_MOSI_SOURCE/PIN1 2 ZXTD09N50DE6 I2C_SI_MODE0 6 1 47 43 44 42 DO NOT OVERLAP RESISTOR PADS R760 R761 R762 R763 R764 CLK_SPI_LE/PIN3 0 0 0 0 DNI_0 100K I2C_STATUS0 CLK_DVDD REF_SEL SI_MODE0 SI_MODE1 PDN RESET/PWR SYNCN DNI_0 DNI_0 DNI_0 DNI_0 DNI_0 4.99K 4.99K 4.99K 4.99K R750 R751 R752 R753 (STATUS 1) PRIMARY REFERENCE LED D102 GREEN 1 2 D102_2 R710 (STATUS 1) SECONDARY REFERENCE LED D103 YELLOW 1 2 D103_2 R711 D103_1 CLK_SPI_MISO/PIN2 U42C U100W D 5V B2 E2 C R754 R755 R756 R757 R758 CLK_SPI_MOSI/PIN1 R728 4 STATUS1_B 0 0 1 Header 6x2 SPI INTERFACE R729 REG_CAP C2 100K STATUS1/PIN0 R712 R713 2 3 4 5 SDI / SDA / PIN1 SDO / AD0 / PIN2 SCS / AD1 / PIN3 SCL / PIN4 0.1uF R709 C684 10uF U100V 2 4 6 8 10 12 CLOCK PDN LED E1 FDV301N FDV301N CDCM6208 EXT_SPI_LE2 CDCM6208 40 REG_CAP EXT_SPI_CLK/PIN4 B1 45 STATUS1/PIN0 EXT_SPI_LE1/PIN3 100 6 /STATUS1_B CLK_DVDD R732 C1 100K EXT_SPI_MISO/PIN2 D105 1 R708 G G EXT_SPI_MOSI/PIN1 DNI_4.99K 4.99K STATUS0_G D 0 U106 1 3 5 7 9 11 EXT_STATUS1/PIN0 S R704 S STATUS0 R706 46 TO "100" Q106 D ELF STATUS0 CDCM6208 REGISTER R3.12:10 Q105 41 INDICATOR REQUIRES SETTING D102_1 ELF U100X 4.99K 220pF D101_1 C683 PRIMARY/SECONDARY REFERENCE R707 1 R703 LOOP FILTER CLK_DVDD /STATUS1 0.022uF 4.99K C682 400 ELF_RC (STATUS 0) PLL LOCK LED D101 GREEN 2D101_2 R705 D CLK_DVDD DNI_0 RED R759 CLOCK /PDN LED GREEN 2D104_2 5V 250 3 5V 250 4 5V 250 5 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 10 of 15 1 Figure 17. TLK10xxx EVM Schematic, Sheet 10 of 15 Clock Control SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 25 TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 2 1 NOTE: 5V VCC_PRI CLK_VDD_IN R776 C689 1uF U114 C691 PLACE R780, AND R781 0.1uF AS CLOSE AS POSSIBLE C690 D TO THE PINS ON U2. THESE ARE TERMINATION 1 1uF 3P3V R781 TLV70233 PRI_EN DNI_49.9 4 NC DNI_49.9 5 OUT R780 0 IN GND EN GREEN 2 1 2 3 DNI_4.99K R770 P_BIAS PRI_LED R772 D R779 3.16K R778 5.49K 250 D110 3P3V RESISTORS R773 DNI_4.99K 1 PRI_STDBY STDBY GND 3 R777 PRI_XO 0 PRI_REFP PRI_REFN 2 8 9 PRI_REFP PRI_REFN CDCM6208 OVERLAP RESISTOR PADS NZ2016SA_30.72MHz OF R777 AND R784. R775 DNI_0 0 OUT DNI_0 R771 U100L 30.72 MHz VDD R785 4 DNI_4.99K R784 Y10 R774 DNI_4.99K 3P3V J103 C692 PRI_REF_IN_P PRI_REF_IN_P_SMP PRI_REF_IN_P C C693 J104 PRI_REF_IN_N PRI_REF_IN_N_SMP 0.1uF PRI_REF_IN_N 2 4 R782 Rocker Switch 2 position R783 1 ON 3 PRI_OSC_EN SEC_OSC_EN DNI_150 SW19 DNI_150 SMA SURFACE R786 R787 7 7 0.1uF SMA SURFACE 4.99K 4.99K C 5V VCC_SEC B 1 2 3 R790 R792 U115 IN GND EN 250 SEC_LED OUT NC 4 DNI_4.99K TLV70233 0 C695 SEC_EN D111 R788 B 5 ORANGE 2 C694 1uF 3P3V 1uF 1 3P3V R791 DNI_4.99K Y11 R793 DNI_4.99K R789 0 4 1 SEC_STDBY U100M 31.25 MHz VDD OUT STDBY GND 3 SEC_REFP 2 11 12 SEC_REFP SEC_REFN CDCM6208 NZ2016SA_31.25MHz R794 DNI_4.99K A A TEXAS INSTRUMENTS PAGE TITLE CRYSTAL OSCILLATORS SIZE B 5 4 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 11 of 15 1 Figure 18. TLK10xxx EVM Schematic, Sheet 11 of 15 Crystal Oscillators 26 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 3 2 1 NOTE: 1. MATCH LOW SPEED INPUT AND OUTPUT TRACE LENGTHS TO EACHOTHER 2. MATCH HIGH SPEED TRANSMIT AND RECEIVE TRACE LENGTHS TO EACHOTHER C210 0.1uF C211 INA3P C212 14 14 INB3/A7P_CONNECTOR INA3N_CONNECTOR 14 14 INB3/A7N_CONNECTOR 0.1uF INA3N D C214 C216 14 14 INB2/A6P_CONNECTOR INA2N_CONNECTOR 14 14 INB2/A6N_CONNECTOR 0.1uF C218 C220 U1C INA3P INA3N INA2P INA2N INA1P INA1N C INA0P INA0N OUTA3P OUTA3N OUTA2P OUTA2N OUTA1P OUTA1N OUTA0P OUTA0N D1 E1 14 14 INB1/A5P_CONNECTOR INA1N_CONNECTOR 14 14 INB1/A5N_CONNECTOR 0.1uF C222 C224 R565 R566 14 14 14 14 R568 OUTB2/A6P_CONNECTOR OUTA2N_CONNECTOR 14 14 OUTB2/A6N_CONNECTOR OUTA1P_CONNECTOR 14 14 OUTB1/A5P_CONNECTOR R576 R571 OUTA0P_CONNECTOR R572 OUTA0N_CONNECTOR 14 OUTB1/A5N_CONNECTOR 14 14 OUTB0/A4P_CONNECTOR 14 14 TLK10xxx 0 R577 0 R578 0 B OUTB1/A5N 14 R579 0 R580 0 OUTB0/A4P 0 OUTA0N OUTB0P / OUTA4P OUTB0N / OUTA4N OUTB1/A5P 0 OUTA0P OUTB1P / OUTA5P OUTB1N / OUTA5N J3 H3 OUTB2/A6N 0 OUTA1N_CONNECTOR K5 K4 OUTB2/A6P 14 OUTB2P / OUTA6P OUTB2N / OUTA6N 0 0 C OUTB3P / OUTA7P OUTB3N / OUTA7N L6 L5 OUTB3/A7N_CONNECTOR 14 OUTA1N INB0P / INA4P INB0N / INA4N M7 M6 0 OUTB3/A7N 0 R570 INB1P / INA5P INB1N / INA5N H1 J1 OUTB3/A7P_CONNECTOR 0 R569 0.1uF OUTB3/A7P OUTA2P_CONNECTOR OUTA1P INB2P / INA6P INB2N / INA6N K2 L2 INB0/A4N R575 OUTA2N INB3P / INA7P INB3N / INA7N L1 M1 0.1uF INB0/A4N_CONNECTOR 0 OUTA2P B 14 U1D M3 M4 INB0/A4P R574 OUTA3N_CONNECTOR TLK10xxx 14 0.1uF INB0/A4P_CONNECTOR 0 OUTA3N R567 0.1uF R573 OUTA3P_CONNECTOR A6 A7 14 0 OUTA3P C4 C5 C219 C225 INA0N_CONNECTOR B5 B6 14 0.1uF INA0N F3 E3 0.1uF C223 INA0P_CONNECTOR D INB1/A5N 0.1uF A4 A3 C217 C221 INA0P A1 B1 0.1uF INB1/A5P INA1P_CONNECTOR INA1N B2 C2 C215 INB2/A6N 0.1uF INA1P 0.1uF INB2/A6P INA2P_CONNECTOR INA2N C213 INB3/A7N 0.1uF INA2P 0.1uF INB3/A7P INA3P_CONNECTOR OUTB0/A4N OUTB0/A4N_CONNECTOR A A TEXAS INSTRUMENTS PAGE TITLE LOW SPEED DATA SIGNALS SIZE B 5 4 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 12 of 15 1 Figure 19. TLK10xxx EVM Schematic, Sheet 12 of 15 Low-Speed Data Signals SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 27 TLK10xxx EVM Motherboard Schematics www.ti.com 3 2 1 3P3V 4.99K R539 4.99K /MR 5 4 JMP36 1 2 DISABLE_SFP+_TX TPS3125J18 3P3V_RX 4.7uH D49 1 C1 100K 6 TX_DISABLE_/RST_B E1 THE MODULE. C2 100K 4 TX_DISABLE_RST_B 3 1 MOD_DEF2_SDA MOD_DEF1_SCL Header 2x2 6 3P3V 4.99K 4.99K 4 5 RATE_SEL_0 RATE_SEL_1 7 9 MOD-DEF2_SDA MOD-DEF1_SCL MOD-DEF0_ABS RATE_SEL_0 RATE_SEL_1 VEER1 VEER2 VEER3 2 R549 C1 44.2K 3 6 TX_FAULT_B 8 1 17 20 C2 44.2K 4 RX_LOS_B RX_LOS TX_FAULT_C B1 E1 R553 1 C 2 2 RX_LOS_L RED ZXTD09N50DE6 U94 TX_FAULT VEET1 VEET2 VEET3 D51 3P3V_RX 2 3P3V 3 RX_LOS_C B2 E2 10 11 14 5 ZXTD09N50DE6 3P3V 3P3V MODULE_DETECT_D R564 D MODULE_DETECT_G G R795 R796 S S G Q12 D R559 Q11 MOD_DEF0_MODULE_DETECT FDV301N R581 J5 HSTXBP 0 HSTXBP_SMA EDGE LAUNCH U1B HSTXBP HSTXBN A B 1 DNI_4.99K DNI_4.99K D48 4.99K B 4.99K 2 R560 R561 SFP_PLUS_CONN_WITH_CAGE ORANGE R562 R563 RX_LOS JMP105 4 2 3P3V_TX 100 TX_DISABLE 15 R551 TX_FAULT RDP RDN TLK10xxx 5 MODULE_DETECT_L HSRXAN 13 12 E2 16 YELLOW HSRXAP TX_DISABLE_RST_C D52 HSRXAP HSRXAN B12 A12 3 1 4.99K 4.99K VCCR 2 1 VCCT 4.99K TDP TDN R558 HSTXAN 18 19 4.99K HSTXAP R557 D12 E12 TX_DISABLE HSTXAP HSTXAN C 3P3V_RX J73A U1A 3P3V B2 3P3V_TX 3P3V TX_DISABLE_/RST_C B1 MODULE CAGE NEAR THE MIDDLE OF R548 1 RED R546 3P3V D50 0.1uF U93 D 1 ONE ON EACH SIDE OF OPTICAL C301 C299 COMMON PATH TO GROUND. PLACE 22uF RESISTORS ARE USED TO PROVIDE 1 C300 L16 2 0 0 0.1uF R542 R544 Header 1x2 100 49.9 VDD R547 R543 /RST GND RST 100 SFP_PLUS_CONN_WITH_CAGE 1 2 3 R545 TX_DISABLE_RST 2TX_FAULT_L C297 TX_DISABLE_/RST 100 100K R540 R541 3P3V C298 0.1uF U92 R538 0.1uF 22uF 1 C296 3P3V 3P3V_TX 4.7uH 100 3P3V_TX L15 2 R556 40 39 38 37 36 35 34 33 32 31 0.1uF 40 39 38 37 36 35 34 33 32 31 2TX_DISABLE_/RST_L D 21 22 23 24 25 26 27 28 29 30 C295 21 22 23 24 25 26 27 28 29 30 3P3V 3P3V_TX TX_DISABLE_RST_L 4 J73B GREEN 5 K12 L12 HSTXBP R582 0 J6 HSTXBN HSTXBN_SMA HSTXBN EDGE LAUNCH FDV301N THE HIGH SPEED TX LINES SHOULD BE AC COUPLED IN THE SYSTEM WITH 0.1uF CAPACITORS FOR PROPER OPERATION. ZERO OHM RESISTORS ARE INSTALLED ON THIS BOARD TO ALLOW FOR EXTERNAL LOOPBACK BETWEEN A THE HSTXB AND HSRXB UTILIZING THE AC CAPACITORS ON THE HSRXB PINS. THE ZERO OHM RESISTORS CAN BE HSRXBP HSRXBN H12 G12 HSRXBP HSRXBP_SMA J7 HSRXBP HSRXBN_SMA J8 HSRXBN REPLACED WITH 0.1uF CAPACITORS IF AC COUPLING CAPACITORS ARE NEEDED ON THESE SIGNALS. TEXAS INSTRUMENTS EDGE LAUNCH HSRXBN C247 0.1uF TLK10xxx PAGE TITLE HIGH SPEED DATA SIGNALS EDGE LAUNCH C249 SIZE 0.1uF B 5 4 3 2 DOCUMENT NUMBER 6566789 REV NA PAGE 13 of 15 1 Figure 20. TLK10xxx EVM Schematic, Sheet 13 of 15 High-Speed Data Signals 28 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 12 12 12 12 INB0/A4P_CONNECTOR INB0/A4N_CONNECTOR OUTB0/A4N_CONNECTOR OUTB0/A4P_CONNECTOR 12 12 D INB1/A5P_CONNECTOR INB1/A5N_CONNECTOR 12 12 OUTB1/A5N_CONNECTOR OUTB1/A5P_CONNECTOR 12 12 OUTB2/A6N_CONNECTOR OUTB2/A6P_CONNECTOR 12 12 12 12 INB2/A6P_CONNECTOR INB2/A6N_CONNECTOR OUTB3/A7N_CONNECTOR OUTB3/A7P_CONNECTOR 12 12 C INB3/A7P_CONNECTOR INB3/A7N_CONNECTOR 9 9 CHB_CLKOUTN_CONNECTOR CHB_CLKOUTP_CONNECTOR 7 LS_OK_IN_B_CONNECTOR 7 LS_OK_OUT_B_CONNECTOR A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 SEAF_ASP-134486-01 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 12 12 B K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 INA3N_CONNECTOR INA3P_CONNECTOR OUTA3P_CONNECTOR OUTA3N_CONNECTOR 12 12 INA2N_CONNECTOR INA2P_CONNECTOR 12 12 OUTA2P_CONNECTOR OUTA2N_CONNECTOR 12 12 OUTA1P_CONNECTOR OUTA1N_CONNECTOR 12 12 12 12 INA1N_CONNECTOR INA1P_CONNECTOR OUTA0P_CONNECTOR OUTA0N_CONNECTOR 12 12 INA0N_CONNECTOR INA0P_CONNECTOR A 9 9 7 7 CHA_CLKOUTP_CONNECTOR CHA_CLKOUTN_CONNECTOR LS_OK_IN_A_CONNECTOR LS_OK_OUT_A_CONNECTOR K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 SEAF_ASP-134486-01 5 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 SEAF_ASP-134486-01 J72J J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 2 SEAF_ASP-134486-01 8 MDIO_B2B_CON 8 MDC_B2B_CON E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 J72H H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 D C SEAF_ASP-134486-01 SEAF_ASP-134486-01 J72F F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 SEAF_ASP-134486-01 4 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 SEAF_ASP-134486-01 J72E J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 1 J72G J72D J72C C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 SEAF_ASP-134486-01 J72K 12 12 3 J72B J72A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 B J72I MOUNT1 MOUNT2 MOUNT3 MOUNT4 SEAF_ASP-134486-01 A TEXAS INSTRUMENTS PAGE TITLE DATA BOARD TO BOARD CONNECTOR SEAF_ASP-134486-01 3 1 2 3 4 2 SIZE DOCUMENT NUMBER REV B 6566789 NA PAGE 14 of 15 1 Figure 21. TLK10xxx EVM Schematic, Sheet 14 of 15 Data Board-to-Board Connector SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 29 TLK10xxx EVM Motherboard Schematics www.ti.com 5 4 J102A D C 9 9 9 9 CLKA3N_CON CLKA3P_CON 9 9 CLKB0P_CON CLKB0N_CON 9 9 CLKA2N_CON CLKA2P_CON 9 9 CLKB1P_CON CLKB1N_CON 9 9 CLKB2P_CON CLKB2N_CON 9 9 CLKA1N_CON CLKA1P_CON 9 9 CLKB3P_CON CLKB3N_CON 9 9 CLKA0N_CON CLKA0P_CON CLKB1P_IN_CON CLKB1N_IN_CON A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 SEAF_ASP-134486-01 B A 9 9 CLKA1P_IN_CON CLKA1N_IN_CON C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 J102J J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 SEAF_ASP-134486-01 2 SEAF_ASP-134486-01 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 J102H H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 SEAF_ASP-134486-01 SEAF_ASP-134486-01 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 D C SEAF_ASP-134486-01 J102F E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 SEAF_ASP-134486-01 4 1 J102G J102D D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 J102E E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 5 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 SEAF_ASP-134486-01 SEAF_ASP-134486-01 J102K K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 3 J102C J102B B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 B J102I SEAF_ASP-134486-01 A TEXAS INSTRUMENTS PAGE TITLE CLOCK BOARD TO BOARD CONNECTOR SEAF_ASP-134486-01 3 1 2 3 4 MOUNT1 MOUNT2 MOUNT3 MOUNT4 2 SIZE DOCUMENT NUMBER REV B 6566789 NA PAGE 15 of 15 1 Figure 22. TLK10xxx EVM Schematic, Sheet 15 of 15 Clock Board to Board Connector 30 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Motherboard Layout www.ti.com TLK10xxx EVM Motherboard Layout GND C618 C74 C71 C616 C622 U24 C619 C617 C623 SW10 U112 D109 RST/PWR D108 RST/PWR U110 U108 D107 SYNCN D106 SYNCN J41 D105 PDN D104 PDN RESET RST BTN SW19 C67 SW17 U101 3p3V REG MAIN RESET RST SW13 J N C600 GND SW14 + C94 D11 RESET CLKB SW18 D10 10uF 68uF C64 CLK SYNCN CLK RST/ SW15 PWR PLL_LOCK (STATUS0) PRI_REF (30.72MHZ) (31.25MHZ) D102 SEC_REF C91 C90 C115 C114 68uF U22 CLK PDN 5V 0.1uF C98 1uF 0.01uF C95 D28 DIS + EXT SMA SEC_OSC CLK GEN PRI_OSC D103 10uF 3P3V_CLK 3P3V 1P8V 1P5V 1P0V_D2 1P0V_D1 1P0V_A2 1P0V_A1 C84 10uF C89 C108 C113 C123 C124 C125 C101 C99 C100 C130 C129 C128 10uF C93 C620 C625 C626 C627 10uF C604 C621 C628 C674 C675 C676 C677 R781R780 C624 R712 10uF220pF R703 C684 0 0 R704 0 R713C682 400 0.022uF C683 C629 0.1uF 0.1uF C672 0.1uF R684 R685 R687R686 0.1uF C671 0.1uF D110 PRI_REF_IN_P R777 U115 C118 C97 10uF 3 Pin Berg REF_SEL SI_MODE0 SI_MODE1 SW16 0.1uF 0.1uF EN P26 TLK10xxxEVM MOTHER BOARD REGULATOR REV NA DISABLE 6566789 EN 0.1uF 1uF 0.01uF PRI_REF_IN_N 68uF C127 0.1uF 1uF 0.01uF D101 1 2 C140 1p5V REG 0.1uF 1uF 0.01uF SPI_MOSI/PIN1 STATUS1/PIN0 ON C139 3 Pin Berg 0.01uF C32 1p8V REG J102 ON SPI_MISO/PIN2 CLKA 1 2 DIS BJ 5V PLUG C29 CLK BUFFER INPUT SPI_LE1/PIN3 STATUS1 U12 68uF 0.1uF 1p5V + 3 Pin Berg 1p8V C46 0.1uF 1uF 0.01uF SPI_CLK/PIN4 +5V 1uF 0.1uF JMP41 C138 C43 10uF SPI_LE2 3267 1p5/8V U16 0.1uF 1uF 0.01uF 0.1uF J104 JMP104 5V_BJ P1 3267 JMP35 10uF 0.1uF10uF SEC_OSC D111 GND P14 3p3V_CLK REG + 0.1uF 0.1uF R785 + +5V ON 0.1uF C678 U100 R784 C693 R783 C680 0.1uF C679 R698 0.1uF HIGH J103 R782 C692 R696R697 R699 PRI_OSC R695 0.1uF 1 2 3 4 0.1uF 1uF C667 C668 0.1uF ON C681 0.1uF R701R700 U114 R689 R691 U105 R702 LOW R694R693 R690 R692 10uF 0.1uF10uF 0.1uF10uF 0.1uF10uF R688 C654 C670 0.1uF C673 68uF 1 2 3 4 5 6 7 8 12 1p0V_A2 REG JMP42 J44 R582 J43 J42 HSTXBn J100 VOLTAGE MONITOR DONGLE J6 REFCLK0n REF CLK1n 68uF REFCLK1p 0.1uF 1uF 0.01uF C111 M1 + U10 10uF C110 M12 J5 C107 C109 R581 C24 HSTXBp REF CLK0p 1p0V_D1 REG 74 R5 76 R5 78 R5 R5 73 R5 75 R5 77 R5 J72 C247 79 R5 80 C22 HSRXBp 0.1uF A12 U1 J7 A1 HSRXBn CLKOUTBn 72 10uF 68uF 1p0V_A1 REG U8 D52 JTAG C607 GND DNI_4.99K DNI_4.99K R628 R625 0 R632 PDTRXA PDTRXB ST/GPI1 MDIO_B2B_RLY MDIO_CON_RLY I2C_GPIO_ADDR 22 SW11 LOSA LOSB PRBS PASS AMUXA GND LS_OKINA LS_OKINB ON JMP48 1 2 3 4 2 Pin Berg LOW R626 C87 C86 R627 HIGH JMP100 IN LOW JMP61 GND JMP101 JMP62 PRTAD0 PRTAD4 PRTAD3 PRTAD2 PRTAD1 GND ON OUT JMP77 3p3V 3 Pin Berg SW12 J101 GND U64 GND MODE/REFCLK_SEL PRBSEN TESTEN LOSB PRBS PASS LOSA U42 U41 12C_LS_EN JTAG_V TRST JMP47 TDO MDIOV R629 Q100 D12 D13 D16 D15 D14 LS_OK OUT_A TX DIS TCK TMS TDI U40 2p5V C85 C15 U92 LS_OK OUT_B D51 RX_LOS GND TX_FAULT R549 R546 R553 D50 D49 TX DIS 4.99K R548 JMP102 USB DONGLE JMP103 R630 0 R631 3p3V 2p5V K3 D100 R633 D48 R539 SCL RESET1 SDA INT1 INT2 RESET2 I2C SFP+ TX_DIS MOD DETECT 10uF 0 4.99K 0 MDC OUTPUT K1 MDIO 100K 100K K4 JMP36 DNI_4.99K DNI_4.99K K2 MDC INPUT MDIO C80 0.1uF 1uF 0.01uF 44.2K 44.2K JMP50 C611 + C119 1p0V_D2 REG U102 C17 + JMP105 J73 GPIO 0.1uF 68uF J8 0.1uF C121 1uF C120 0.01uF C117 71 R5 70 R5 69 67 R5 R5 65 R5 R5 J45 R5 J46 68 CLKOUTAn CLKOUTAp J47 66 CLKOUTBp R5 J48 C249 1 2 3 4 5 6 7 8 9 10 HIGH 23 Figure 23. TLK10xxx EVM Layout, Top Signal (Layer 1) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 31 TLK10xxx EVM Motherboard Layout www.ti.com Figure 24. TLK10xxx EVM Layout, Internal Ground (Layer 2) 32 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM Motherboard Layout www.ti.com Figure 25. TLK10xxx EVM Layout, Internal Signal (Layer 3) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 33 TLK10xxx EVM Motherboard Layout www.ti.com Figure 26. TLK10xxx EVM Layout, Internal Ground (Layers 4, 6, 7, 9, 11, 13, 15) 34 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM Motherboard Layout 3P3V VDDD VDDT 3p3V_CLK CLK_VDD_OUTA CLK_VDD_PLL CLK_VDD_OUTB CLK_VDD_PLLA www.ti.com Figure 27. TLK10xxx EVM Layout, Internal Power (Layer 5) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 35 TLK10xxx EVM Motherboard Layout 3P3V_TX VDDRB_LS VDDRB_HS 3P3V_RX VDDO VDDRA_HS VDDRA_LS www.ti.com Figure 28. TLK10xxx EVM Layout, Internal 5-V Power (Layer 8) 36 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM Motherboard Layout www.ti.com Figure 29. TLK10xxx EVM Layout, Internal 5-V Power (Layer 10) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 37 www.ti.com VDDA VDDO DVDD CLK_VDD_IN 3P3V_CLK CLK_VCC CLK_DVDD TLK10xxx EVM Motherboard Layout Figure 30. TLK10xxx EVM Layout, Internal Power (Layer 12) 38 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM Motherboard Layout www.ti.com Figure 31. TLK10xxx EVM Layout, Internal Signal (Layer 14) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 39 TLK10xxx EVM Motherboard Layout www.ti.com C76 R610 C75 L101 R722 R721 R720 R787 C689 R772 R770 R773 R786 R186 C631 R188 C632 C77 R771 R774 L100 R185 C690 C73 C72 R775 C633 C630 R776 C137 Y10 + L103 C33 L14 D9 R86 C31 R612 C35 R83 L8 C34 R84 C30 C47 L4 L9 L104 C656 C136 L6 L2 R371 C655 C669 R665R666 R667R668 C659 C660 C658 C657 R765 R753 R766 R756 R757 R767 R768 R752 R758 R769 R677 R679 R676 R678 R673R672 R671R670 R675R674 R791 R788 R790 R793C694 C695 R792 R789 C647 C644 R669 C653 C652 R794 C48 R117 L106 R613 C49 C648 C651 C646 C645 C650 C649 Y11 C45 C638 C641 C691 R120 C640 C639 C642 R779 R778 R118 C44 R719 R717 R718 R716 R715 R714 C643 L102 L3 C661 C662 L105 U104 R683 R681 R682 R680 C69 R764 C606 C605 R603 R169 R725 R724 R723 R762 R171 R242 R755 R751 R760 R754 R750 * R705 C688 U38 C686 R706 R736 R738 R466 R243 U37 R486 U111 C189 C190 R245 R240 C282 C283 U109 R730 R732 R740 R707 R748 R710 U113 R731 R733 R726 R727 C685 R746 C602 C601 R465 R258 R244 R739 R741 U106 R708 R747 R749 R711 Q106 C66 C65 R259 R728 R709 R602 R729 C687 R241 R744 C603 R168 R737 R745 Q105 R734 R735 R742 R743 R759 R604 C70 R246 U107 R761 R605 R611 C68 C663 C664 C665 C666 R763 U36 R239 R496 R497 C636 C635 C637 C634 R499 R498 C27 C201 C203 C193 C195 C199 C205 C197 R67 R69 C28 C191 4 1 16 C 13 C2 17 C2 21 C2 25 C2 C174 3 14 7 16 C 2 17 C C192 C150 C147 C173 C146 C C152 C2 11 C2 23 5 16 C2 15 C C144 C145 C166 C163 C198 C200 C26 C151 C171 C170 C153 C168 22 C2 18 C2 C2 C2 10 C202 C204 C194 C196 14 C206 C23 C2 19 1 45 R 49 R R292 R294 C142 C141 R66 C169 C148 C188 C149 R601 C25 L5 C2 C2 C2 24 20 12 16 C2 L7 C300 R600 C18 R657 C295 C299 R542 C296 C613 C20 C612 R607 R608 R50 R52 R563 C21 C301 R655 R653 R651 R652 R654 R649 R510 R508 R509 R511 C274 C281 C275 Q3 R624 R648 R472 R476 R477 R473 C280 Q4 C278 C279 Q6 R263 R257 R622 R621 R284 R280 R463 R462 R461 R460 R459 R279 R273 R618 R276 R275 R617 R285 R283 R274 R286 R532 R533 R287 R277 C304 R270 C303 R300 R269 R255 R254 R253 R252 R251 R250 R619 R249 R248 R247 R620 U43 R638 R306 R307 Q5 R301 R302 R303 R304 R305 R637 R636 R309 R308 R640 R281 R268 R616 R647 R293 R290 R639 R288 R634 R296 Q7 C609 C608 Q12 C615 R289 R635 R297 C286 C302 R623 R564 R543 R541 R295 U103 R298 R282 U93 Q104 C610 R606 L1 C19 C16 R278 R262 R256 R551 Q11 R559 Q103 R299 R642 R291 R641 R538 R614 R615 C614 R544 R644 R643 R645 R558 R540 R557 Q102 R646 R656 U94 Q101 R49 R650 R556 C298 R545 R560 R561 R547 R795 R796 R658 L16 R609 R663 R661 R659 R660 C297 R662 R664 L15 R562 Figure 32. TLK10xxx EVM Layout, Bottom Signal (Layer 16 Top View) 40 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM Motherboard Layout www.ti.com Table 1. TLK10xxx EVM Mother Board Layer Construction Subclass Name TOP L2_GND L3_SIG2 L4_GND L5_PWR L6_GND L7_GND L8_PWR L9_GND L10_PWR L11_GND L12_PWR L13_GND L14_SIG3 L15_GND BOTTOM Type Material Thickness (MIL) Dielectric Constant SURFACE AIR CONDUCTOR COPPER 1.9 2.8 DIELECTRIC Rogers 5 3.6 PLANE COPPER 1.2 1 DIELECTRIC FR-4 5 4.1 CONDUCTOR COPPER 1.2 1 DIELECTRIC FR-4 10 4.1 PLANE COPPER 1.2 1 DIELECTRIC FR-4 5 4.1 CONDUCTOR COPPER 1.2 1 DIELECTRIC FR-4 5 4.1 PLANE COPPER 1.2 1 DIELECTRIC FR-4 5 4.5 PLANE COPPER 1.2 4.5 DIELECTRIC FR-4 5 4.5 PLANE COPPER 1.2 4.5 DIELECTRIC FR-4 5 4.5 PLANE COPPER 1.2 4.5 DIELECTRIC FR-4 5 4.1 CONDUCTOR COPPER 1.2 4.5 DIELECTRIC FR-4 5 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 5 4.1 CONDUCTOR COPPER 1.2 1 DIELECTRIC FR-4 5 4.1 PLANE COPPER 1.2 1 DIELECTRIC FR-4 10 4.1 CONDUCTOR COPPER 1.2 1 DIELECTRIC FR-4 5 4.1 PLANE COPPER 1.2 1 DIELECTRIC Rogers 5 3.6 CONDUCTOR COPPER 1.9 1 SURFACE AIR Width (MIL) Coupling Type / Spacing (MIL) 4.5 (Diff) 10.0 (Single) Edge / 4.0 (Diff) None/None (Single) 6.0 (Single) None/None (Single) 6.0 (Single) None/None (Single) 4.5 (Diff) 10.0 (Single) Edge / 4.0 (Diff) None/None (Single) 1 1 Note: The impedance is set to be slightly less than 50 Ω or 100 Ω on the traces in order to compensate for slight over-etching during the manufacturing process. The end impedance after etching should result in a 50- or 100-Ω impedance. Always consult with your board manufacturer for their process and design requirements to ensure the desired impedance is achieved. SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 41 TLK10xxx EVM SMA Breakout Board Schematics 13 www.ti.com TLK10xxx EVM SMA Breakout Board Schematics 5 4 3 2 1 REVISIONS NOTES: ECR NUMBER ECR DATE ------- xx/xx/xx 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS. 2. PLACE ALL PARTS OTHER THAN SMA CONNECTORS ON A 0 OR 90 DEGREE ORIENTATION. 3. SERIAL DATA SHOULD BE ROUTED AS 100 OHM DIFFERENTIALLY COUPLED OR SINGLE-ENDED 50 OHM TRANSMISSION LINES ON OUTSIDE LAYERS. ROUTING DISTANCE SHOULD BE 5 INCHES OR LESS. ALL OTHER DATA LINES SHOULD BE 50 OHM IMPEDIANCE ON INTERNAL OR EXTERNAL LAYERS. ROUTED POWER SHOULD BE A MINIMUM OF 40 MILS WIDE. D 4. USE FR4-370 MATERIAL FOR ALL LAYERS. D 5. SERIAL AND REFCLK NETS MUST MATCH WITHIN +/- 0.5 MILS 6. MATCH DIFFERENTIAL TRACE WIDTHS OF SERIAL AND REFCLK LINES WITH SMP/SMA PADS. 7. PLACE TI LOGO, BOARD NAME, JN COMBO LOGO, AND THE BOARD NUMBER IN TOP SIDE METAL. SCHEMATIC SHEET INDEX: C C SHEET 01: TLK10xxx EVM SMA BREAKOUT DAUGHTER BOARD COVER SHEET AND NOTES SHEET 02: CHB[3:0], CHA[7:4], CLKA/B SIGNALS SHEET 03: CHA[3:0], CLKA1_IN SIGNALS SHEET 04: COMMON SIGNALS B B TEXAS INSTRUMENTS A A SCHEMATIC TITLE ENGINEER J. NERGER DATE TLK10xxx EVM SMA BREAKOUT DAUGHTER BOARD 01/30/13 PAGE TITLE LAYOUT TLK10xxx DATA SHEET REVISION: x.x.x G. ROTH RELEASED DATA SHEET LAST UPDATED ON: xx/xx/xx 5 J. NERGER 4 3 DATE 01/30/13 DATE 01/30/13 COVER PAGE AND NOTES SIZE DOCUMENT NUMBER REV B 6568779 NA 2 1 SHEET of 4 1 Figure 33. TLK10xxx EVM SMA Breakout Board Schematic, Sheet 1 Cover Page and Index 42 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM SMA Breakout Board Schematics www.ti.com 5 4 3 2 1 J2 INB0P_INA4P_CLKA3N SMA SURFACE R1 R2 0 0 INB0P / INA4P / CLKA3N INB0P_INA4P_CLKA3N_SMA INB0N_INA4N_CLKA3P_SMA J3 INB0N_INA4N_CLKA3P SMA SURFACE INB0N / INA4N / CLKA3P J4 D D OUTB0N_OUTA4N_CLKB0P SMA SURFACE R3 R4 J1B C 0 0 OUTB0N / OUTA4N / CLKB0P OUTB0N_OUTA4N_CLKB0P_SMA OUTB0P_OUTA4P_CLKB0N_SMA J5 J1A B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 OUTB0P_OUTA4P_CLKB0N INB0P_INA4P_CLKA3N SMA SURFACE OUTB0P / OUTA4P / CLKB0N INB0N_INA4N_CLKA3P J6 INB1P_INA5P_CLKA2N SMA SURFACE R5 R6 OUTB0N_OUTA4N_CLKB0P OUTB0P_OUTA4P_CLKB0N 0 0 INB1P / INA5P / CLKA2N INB1P_INA5P_CLKA2N_SMA INB1N_INA5N_CLKA2P_SMA J7 INB1N_INA5N_CLKA2P INB1P_INA5P_CLKA2N SMA SURFACE J8 INB1N_INA5N_CLKA2P INB1N / INA5N / CLKA2P OUTB1N_OUTA5N_CLKB1P SMA SURFACE R7 R8 OUTB1N_OUTA5N_CLKB1P OUTB1P_OUTA5P_CLKB1N 0 0 OUTB1N / OUTA5N / CLKB1P OUTB1N_OUTA5N_CLKB1P_SMA OUTB1P_OUTA5P_CLKB1N_SMA J9 OUTB1P_OUTA5P_CLKB1N OUTB2N_OUTA6N_CLKB2P SMA SURFACE OUTB1P / OUTA5P / CLKB1N OUTB2P_OUTA6P_CLKB2N C INB2P_INA6P_CLKA1N INB2N_INA6N_CLKA1P J12 OUTB3N_OUTA7N_CLKB3P OUTB2N_OUTA6N_CLKB2P OUTB3P_OUTA7P_CLKB3N SMA SURFACE R9 R10 INB3P_INA7P_CLKA0N 0 0 OUTB2N / OUTA6N / CLKB2P OUTB2N_OUTA6N_CLKB2P_SMA OUTB2P_OUTA6P_CLKB2N_SMA J13 INB3N_INA7N_CLKA0P OUTB2P_OUTA6P_CLKB2N SMA SURFACE OUTB2P / OUTA6P / CLKB2N CHB_CLKOUTN_CLKB1P_IN J10 CHB_CLKOUTP_CLKB1N_IN INB2P_INA6P_CLKA1N JMP1 1 3 LS_OK_IN_B LS_OK_OUT_B SMA SURFACE 2 4 R11 R12 0 0 INB2P / INA6P / CLKA1N INB2P_INA6P_CLKA1N_SMA INB2N_INA6N_CLKA1P_SMA J11 Header 2x2 INB2N_INA6N_CLKA1P SMA SURFACE B B INB2N / INA6N / CLKA1P SEAM_ASP-134488-01 J16 SEAM_ASP-134488-01 OUTB3N_OUTA7N_CLKB3P SMA SURFACE R13 R14 0 0 OUTB3N / OUTA7N / CLKB3P OUTB3N_OUTA7N_CLKB3P_SMA OUTB3P_OUTA7P_CLKB3N_SMA J17 OUTB3P_OUTA7P_CLKB3N SMA SURFACE OUTB3P / OUTA7P / CLKB3N J14 INB3P_INA7P_CLKA0N SMA SURFACE R15 R16 0 0 INB3P / INA7P / CLKA0N INB3P_INA7P_CLKA0N_SMA INB3N_INA7N_CLKA0P_SMA J15 INB3N_INA7N_CLKA0P SMA SURFACE INB3N / INA7N / CLKA0P J18 CHB_CLKOUTN_CLKB1P_IN SMA SURFACE R17 R18 A 0 0 CHB_CLKOUTN / CLKB1P_IN CHB_CLKOUTN_CLKB1P_IN_SMA CHB_CLKOUTP_CLKB1N_IN_SMA A J19 CHB_CLKOUTP_CLKB1N_IN SMA SURFACE CHB_CLKOUTP / CLKB1N_IN TEXAS INSTRUMENTS PAGE TITLE CHB[3:0], CHA[7:4], CLKA/B SIGNALS 5 4 3 SIZE DOCUMENT NUMBER REV B 6568779 NA 2 PAGE 2 of 4 1 Figure 34. TLK10xxx EVM SMA Breakout Board Schematic, Sheet 2 Channel B and CLKA/B Signals SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 43 TLK10xxx EVM SMA Breakout Board Schematics www.ti.com 5 4 3 2 1 J20 INA3N SMA SURFACE R19 R20 0 0 INA3N INA3N_SMA INA3P_SMA J21 INA3P SMA SURFACE INA3P J22 D D OUTA3P SMA SURFACE R21 R22 OUTA3P OUTA3P_SMA OUTA3N_SMA J23 J1K J1J C 0 0 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 OUTA3N INA3N SMA SURFACE OUTA3N INA3P J24 INA2N SMA SURFACE R23 R24 OUTA3P OUTA3N 0 0 INA2N INA2N_SMA INA2P_SMA J25 INA2P INA2N SMA SURFACE J26 INA2P INA2P OUTA2P SMA SURFACE R25 R26 OUTA2P OUTA2N 0 0 OUTA2P OUTA2P_SMA OUTA2N_SMA J27 OUTA2N OUTA1P SMA SURFACE OUTA2N OUTA1N C INA1N INA1P J30 OUTA0P OUTA1P OUTA0N SMA SURFACE R27 R28 INA0N 0 0 OUTA1P OUTA1P_SMA OUTA1N_SMA J31 INA0P OUTA1N SMA SURFACE OUTA1N CHA_CLKOUTP_CLKA1P_IN J28 CHA_CLKOUTN_CLKA1N_IN INA1N JMP2 LS_OK_IN_A LS_OK_OUT_A 1 3 SMA SURFACE 2 4 R29 R30 0 0 INA1N INA1N_SMA INA1P_SMA J29 Header 2x2 INA1P SMA SURFACE B B INA1P SEAM_ASP-134488-01 SEAM_ASP-134488-01 J34 OUTA0P SMA SURFACE R31 R32 0 0 OUTA0P OUTA0P_SMA OUTA0N_SMA J35 OUTA0N SMA SURFACE OUTA0N J32 INA0N SMA SURFACE R33 R34 0 0 INA0N INA0N_SMA INA0P_SMA J33 INA0P SMA SURFACE INA0P J36 CHA_CLKOUTP_CLKA1P_IN SMA SURFACE R35 R36 A 0 0 CHA_CLKOUTP / CLKA1P_IN CHA_CLKOUTP_CLKA1P_IN_SMA CHA_CLKOUTN_CLKA1N_IN_SMA A J37 CHA_CLKOUTN_CLKA1N_IN SMA SURFACE CHA_CLKOUTN / CLKA1N_IN TEXAS INSTRUMENTS PAGE TITLE CHA[3:0], CLKA1_IN SIGNALS 5 4 3 SIZE DOCUMENT NUMBER REV B 6568779 NA 2 PAGE 3 of 4 1 Figure 35. TLK10xxx EVM SMA Breakout Board Schematic, Sheet 3 Channel A and CLKA1_IN Signals 44 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM SMA Breakout Board Schematics www.ti.com 5 4 3 2 1 D D J1H J1D C B D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 J1F H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 SEAM_ASP-134488-01 SEAM_ASP-134488-01 JMP3 J1E F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 SEAM_ASP-134488-01 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 MDIO_POST_LS 1 3 J1C 2 4 MDC_POST_LS Header 2x2 SEAM_ASP-134488-01 J1G C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 SEAM_ASP-134488-01 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 C B SEAM_ASP-134488-01 J1I MOUNT1 MOUNT2 MOUNT3 MOUNT4 I1 I2 I3 I4 A A SEAM_ASP-134488-01 TEXAS INSTRUMENTS PAGE TITLE COMMON CONTROL SIGNALS 5 4 3 SIZE DOCUMENT NUMBER REV B 6568779 NA 2 PAGE 4 of 4 1 Figure 36. TLK10xxx EVM SMA Breakout Board Schematic, Sheet 4 Common Control Signals SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 45 TLK10xxx EVM SMA Breakout Board Layout 14 www.ti.com TLK10xxx EVM SMA Breakout Board Layout INB1P / INA5P / CLKA2N R 11 R 5 OUTB0P / OUTA4P / CLKB0N J5 INB1N / INA5N / CLKA2P INB0N / INA4N / CLKA3P J4 J11 INB2N / INA6N / CLKA1P OUTB3N / OUTA7N / CLKB3P OUTB2N / OUTA6N / CLKB2P OUTB1N / OUTA5N / CLKB1P INB3P / INA7P / CLKA0N J12 J14 J9 J13 J15 J16 R 15 J8 J3 1 R J7 16 R R 2 INB0P / INA4P / CLKA3N 12 R J2 INB2P / INA6P / CLKA1N J10 6 R OUTB0N / OUTA4N / CLKB0P J6 J17 INB3N / INA7N / CLKA0P OUTB1P / OUTA5P / CLKB1N OUTB3P / OUTA7P / CLKB3N OUTB2P / OUTA6P / CLKB2N CHA_CLKOUTN / CLKA1N_IN CHB_CLKOUTN / CLKB1P_IN J37 36 R R GND GND GND 35 R JN 18 JMP3 R LS_OK_IN_A LS_OK_OUT_A MDC MDIO 17 J18 LS_OK_IN_B LS_OK_OUT_B J36 J19 JMP2 CHB_CLKOUTP / CLKB1N_IN CHA_CLKOUTP / CLKA1P_IN INA0P J27 J31 J33 J26 J30 J32 OUTA0N J35 34 J21 R R OUTA1N 20 R J20 19 OUTA2N R INA3P INA3N 33 J34 J22 J23 OUTA2P OUTA1P INA2P INA1P 30 R 24 R R 29 23 OUTA3N OUTA0P TLK10xxx SMA BREAKOUT BRD 6568779 REV N/A J29 R OUTA3P J25 INA0N J24 J28 INA2N INA1N Figure 37. TLK10xxx EVM SMA Breakout Board Layout, Top Signal (Layer 1) 46 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM SMA Breakout Board Layout www.ti.com Figure 38. TLK10xxx EVM SMA Breakout Board Layout, Internal Ground (Layer 2) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 47 TLK10xxx EVM SMA Breakout Board Layout www.ti.com Figure 39. TLK10xxx EVM SMA Breakout Board Layout, Internal GND (Layers 3, 4, 5) 48 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM SMA Breakout Board Layout www.ti.com Figure 40. TLK10xxx EVM SMA Breakout Board Layout, Bottom Signal (Layers 6) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 49 TLK10xxx EVM SMA Breakout Board Layout www.ti.com Table 2 shows the EVM SMA breakout board layer construction. Table 2. TLK10xxx EVM SMA Breakout Board Layer Construction Subclass Name TOP L2_GND L3_GND L4_GND BOTTOM Type Material Thickness (MIL) Dielectric Constant SURFACE AIR CONDUCTOR COPPER 2 1 DIELECTRIC FR-4 5 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 20 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 4 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 20 4.5 CONDUCTOR COPPER 2 1 SURFACE AIR Width (MIL) Coupling Type / Spacing (MIL) 6.00 (Diff) 9.5 (Single) Edge / 5.0 (Diff) None/None (Single) 6.50 (Single) None/None (Single) 6.00 (Diff) 9.5 (Single) Edge / 5.0 (Diff) None/None (Single) 1 Note: The impedance is set to be slightly less than 50 Ω or 100 Ω on the traces in order to compensate for slight over-etching during the manufacturing process. The end impedance after etching should result in a 50- or 100-Ω impedance. Always consult with your board manufacturer for their process and design requirements to ensure the desired impedance is achieved. 50 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM Voltage Monitor Board Schematics www.ti.com 15 TLK10xxx EVM Voltage Monitor Board Schematics Figure 41 through Figure 50 illustrate the EVM voltage monitor board schematics 5 4 3 2 1 REVISIONS NOTES: ECR NUMBER DATE ------- ECR xx/xx/xx 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS. 2. PLACE ALL PARTS ON A 0 OR 90 DEGREE ORIENTATION. 3. VOLTAGE SENSE LINES SHOULD BE ROUTED AS WIDE AS POSSIBLE TO REDUCE IR DROP. 4. USE FR4-370 MATERIAL FOR ALL LAYERS. 5. PLACE TI LOGO IN TOP SIDE METAL D D 6. PCB MUST BE 0.062 INCHES THICK 7. MATES WITH SAMTEC CONNECTOR (MEC1-130-02-F-D-A) SCHEMATIC SHEET INDEX: SHEET 01: SHEET 02: SHEET 03: SHEET 04: SHEET 05: SHEET 06: SHEET 07: SHEET 08: SHEET 09: SHEET 10: C TLK10xxx VOLTAGE MONITOR COVER SHEET AND NOTES 1P0V_D1, 1P0V_D2, 2P5V, 3P3V LEDS 1P0V_A1, 1P0V_A2, AND VDDRB_HS LEDS VDDA, VDDT, VDDD, AND DVDD LEDS CLK_DVDD/VCC/VDD_OUT_B/VDD_IN LEDS 3P3V_CLK, CLK_VDD_PLL_A/_OUTA/_PLL LEDS VDDRB_LS AND VDDRA_HS LEDS VDDRA_LS AND VDDO LEDS 1P5V, 1P8V, AND 5V LEDS EDGE CONNECTOR AND DECOUPLING C B B TEXAS INSTRUMENTS A A SCHEMATIC TITLE TLK10xxx VOLTAGE MONITOR BOARD ENGINEER J. NERGER DATE 01/30/13 PAGE TITLE LAYOUT TLK10xxx DATA SHEET REVISION: x.x.x J. NERGER DATA SHEET LAST UPDATED ON: xx/xx/xx RELEASED 5 J. NERGER 4 3 2 DATE 01/30/13 DATE 01/30/13 COVER PAGE AND NOTES SIZE B DOCUMENT NUMBER REV NA 6568778 1 SHEET of 10 1 Figure 41. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 1 of 10 Cover Page and Index SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 51 TLK10xxx EVM Voltage Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF1 5V 5V 4P096V_REF2 5V 5V U1 1.2K LM339A VCC GND 12 4 5V LM339A 14 R17 3.48K U2E 1P0V_D1_B 3 IN_N 3 OUT R14 1P0V_D1 + - 2 OUT 9.76K 1P0V_D1_0P85V_VREF 10 4 IN_P 4 IN_N 4 OUT C2 4P096V_REF2 U5D 9 ZXTD09N50DE6 8 LM339A 3P3V E2 3 IN_P 3 IN_N + - 3 OUT 14 R18 2K 13 11 10K 3P3V_3P0V_VREF 2 3 B2 1.65K 3P3V_3P6V_VREF R20 4 5V 1 B1 E1 R15 D4 BLUE D3 U6 3 LM339A + - 2 C1 5 1 + - 2 B2 BLUE 2 2 IN_P 2 IN_N U5E 11 105K R8 4 2P5V_2P3V_VREF 6 E2 3 IN_P 105K 9 10K 1 C LM339A B1 33.2K 8 5 R12 C1 C2 4P096V_REF1 U5C 3P3V_C U3 E1 1P0V_D1_1P15V_VREF 1 1 2 6 U2D 1 OUT 2P5V_C 2 OUT + - 2P5V_B + - 1 IN_N 3P3V_B 2 IN_N 1 IN_P 105K 2 IN_P 6 2P5V 5 ZXTD09N50DE6 R16 4 2 2 BLUE D2 1 1P0V_D2_0P85V_VREF 7 2P5V_2P7V_VREF LM339A 1P0V_D2_C 5 9.76K LM339A 6.04K R10 1.8K 1P0V_D2_B U2C 5V U5B R7 1 1 OUT 1 R6 1 IN_N + - 1P0V_D1_C 6 1P0V_D2 1 IN_P BLUE 7 105K 33.2K R9 3.48K R19 R4 1.2K 1.2K R3 U5A 3 4P096V_REF2 LM339A 2 U2B B 5V C1 0.47uF 5V 1P0V_D2_1P15V_VREF R13 REF2940 3P3V_L GND 1 2P5V_L VCC 5V VIN 12 1P0V_D1_L C2 0.47uF 2 GND LM339A 1P0V_D2_L 3 4P096V_REF1 R11 3 5V U2A REF2940 C VOUT R2 R1 1 VIN R5 U4 5V GND D1 3 1.2K 2 VOUT 10 4 IN_P 4 IN_N B LM339A + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE 1P0V_D1, 1P0V_D2, 2P5V, 3P3V LEDS SIZE B 5 4 3 DOCUMENT NUMBER 6568778 2 REV NA PAGE 2 of 10 1 Figure 42. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 2 of 10 1V_D1/D2, 2p5V, 3p3V LEDs 52 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Voltage Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF3 5V 4P096V_REF4 5V U7 5V 2 OUT 2 U9 C2 U8D LM339A 3 IN_N R35 1P0V_A1 3 OUT 14 R37 3.48K U8E 11 R39 9.76K 1P0V_A1_0P85V_VREF 10 4 IN_P 4 IN_N 1P0V_A1_B 8 + - 1.2K 2 OUT 2 U11D 9 8 LM339A ZXTD09N50DE6 VDDRB_HS E2 3 IN_P 3 IN_N + - 3 OUT 14 R38 2K U11E 13 R40 10K VDDRB_HS_1P675V_VREF 10 4 IN_P 4 IN_N BLUE D8 2 3 B2 12.4K VDDRB_HS_2P0V_VREF 1 C B1 4 5V 2VDDRB_HS_1P8V_L 2VDDRB_HS_1P5V_L C1 6 C2 R34 BLUE U12 E1 5 R24 R23 + - 3 11 4 OUT 2 IN_N 2 LM339A + - 2 IN_P D7 R28 4 LM339A 4P096V_REF4 E2 3 IN_P 105K 9 10K 1 B2 33.2K 1P0V_A1_1P15V_VREF B 4 5V 1 B1 E1 4P096V_REF3 5 R32 VDDRB_HS_1P35V_VREF C1 1 OUT 1 + - + - VDDRB_HS_1P8V_C 2 IN_N 1 IN_N R30 2K 1P0V_A1_C 2 IN_P 1 IN_P R36 4 6 R33 D6 1 1P0V_A2_0P85V_VREF LM339A U11C 1P0V_A2_C 9.76K VDDRB_HS LM339A 1P0V_A2_B 5 R31 2 6 R29 3.48K U8C 7 VDDRB_HS_1P5V_B 1 12 18K VDDRB_HS_1P625V_VREF 1 1 OUT R27 BLUE 2 + - R26 1 IN_N BLUE 1 IN_P GND U11B D5 6 1P0V_A2 LM339A VCC 5V LM339A 105K 7 U11A 4P096V_REF4 5V U8B 33.2K 1P0V_A2_1P15V_VREF 3 VDDRB_HS_1P8V_B 4P096V_REF3 5V C4 0.47uF 1 REF2940 VDDRB_HS_1P5V_C 12 105K GND 1 105K VCC 5V VIN LM339A 1P0V_A1_L 3 C3 0.47uF 2 GND R22 5V U8A REF2940 C 1.2K 1.2K R21 1 VIN 1P0V_A2_L GND R25 VOUT 3 5V 1.2K U10 2 VOUT 3 5V 5 ZXTD09N50DE6 B LM339A + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE 1P0V_A1, 1P0V_A2, AND VDDRB_HS LEDS SIZE B 5 4 3 DOCUMENT NUMBER 6568778 2 REV NA PAGE 3 of 10 1 Figure 43. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 3 of 10 1V_A1/A2, VDDRB_HS LEDs SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 53 TLK10xxx EVM Voltage Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF5 5V 5V 4P096V_REF6 5V 5V U13 U17A LM339A VCC GND U15 4 5V LM339A 3 OUT 105K + - 14 R58 3.48K U14E 2 IN_N + - 2 OUT 9.76K VDDD_0P85V_VREF 10 4 IN_P 4 IN_N 4 OUT R56 C1 LM339A VDDA_1P15V_VREF 9 8 VDDA 3 IN_N + - 3 OUT 14 R59 3.48K 13 11 R61 9.76K VDDA_0P85V_VREF 1.2K R45 2 3 B2 E2 3 IN_P 1 B1 33.2K ZXTD09N50DE6 D13 BLUE D12 U18 4 5V U17D LM339A + - 105K 4P096V_REF6 U17E 11 2 E1 5 BLUE 2 2 IN_P 3 B2 2 2 4 2 R55 VDDD 3 IN_N VDDT_0P85V_VREF C2 E2 3 IN_P VDDD_B 8 5 9.76K 1 C LM339A 6 33.2K 9 1 B1 C2 4P096V_REF5 U17C R53 C1 E1 VDDD_1P15V_VREF 1 OUT 1 2 6 U14D + - VDDA_C 2 OUT 1 IN_N VDDT_B + - 1 IN_P VDDA_B 2 IN_N LM339A VDDD_C 2 IN_P 6 105K 4 7 VDDT 5 ZXTD09N50DE6 R57 DVDD_0P85V_VREF VDDT_1P15V_VREF R51 3.48K DVDD_C 5 9.76K LM339A 33.2K R49 1 BLUE 1 D11 1 OUT DVDD_B U14C R60 12 5V U17B R48 1 + - R47 1 IN_N BLUE 6 DVDD 1 IN_P D10 7 105K 33.2K R50 3.48K B 3 4P096V_REF6 LM339A 2 U14B R54 5V C6 0.47uF VDDA_L REF2940 5V DVDD_1P15V_VREF R52 1.2K 1.2K R43 12 R44 GND 1 VDDT_L VCC 5V VIN DVDD_L LM339A GND 1 3 C5 0.47uF U14A 4P096V_REF5 C VOUT 3 VDDT_C REF2940 5V 2 VDDD_L 1 VIN R46 U16 5V GND R42 3 1.2K 2 VOUT 10 4 IN_P 4 IN_N B LM339A + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE VDDA, VDDT, VDDD, DVDD LEDS SIZE B 5 4 3 DOCUMENT NUMBER 6568778 2 REV NA PAGE 4 of 10 1 Figure 44. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 4 of 10 VDDA, VDDT, VDDD, DVDD LEDs 54 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Voltage Monitor Board Schematics www.ti.com 5 3 4 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 5V 4P096V_REF7 5V 5V 4P096V_REF8 5V U19 2 2 OUT 2 U21 C1 C2 LM339A 14 R78 2K U20E CLK_DVDD_B 3 OUT 105K + - R75 CLK_DVDD 3 IN_N 10K 1 CLK_VDD_IN_3P0V_VREF 4 2 IN_N 2 OUT R80 10K CLK_DVDD_3P0V_VREF 10 4 IN_P 4 IN_N + - 4 OUT U24 C1 6 4 5V 4P096V_REF8 U23D LM339A CLK_VDD_OUTB_3P6V_VREF 9 8 CLK_VDD_OUTB 3 IN_P 3 IN_N + - 3 OUT 14 R79 2K 11 13 10K CLK_VDD_OUTB_3P0V_VREF 10 4 IN_P 4 IN_N 1 2 BLUE D17 B1 2 3 B2 1.65K ZXTD09N50DE6 R81 R65 CLK_VDD_IN_L BLUE 2 E1 5 C LM339A + - 3 LM339A CLK_VDD_OUTB_L R64 2 IN_P U23E 11 1 2 R76 1.2K 1.2K 2 2 1 OUT 105K + - U23C 5 R73 B2 E2 3 IN_P 1 IN_N C2 1.65K 8 B 4 5V 4P096V_REF7 U20D 1 IN_P B1 E1 9 6 LM339A + - 7 CLK_VDD_IN R71 2K 6 CLK_DVDD_3P6V_VREF CLK_VDD_IN_3P6V_VREF 1 2 IN_N 5V LM339A 1.65K CLK_VDD_OUTB_C 2 IN_P 12 CLK_VDD_IN_B 4 GND CLK_VDD_OUTB_B 10K CLK_VCC_3P0V_VREF R74 BLUE 1 5 R72 D15 1 CLK_VCC_B U20C LM339A VCC U23B R68 1 1 OUT BLUE + - R67 1 IN_N R70 2K D14 6 CLK_VCC 1 IN_P 105K 7 U23A 4P096V_REF8 1.65K CLK_VCC_3P6V_VREF C LM339A 2 U20B R66 3 D16 5V 4P096V_REF7 5V C7 0.47uF REF2940 1 12 1 CLK_VDD_IN_C VIN R69 GND 5V GND 105K VCC 2 R77 LM339A VOUT 3 CLK_DVDD_L U20A CLK_VCC_L 3 C8 0.47uF REF2940 R63 .2K 1 5V CLK_DVDD_C 1 VIN R62 5V GND CLK_VCC_C 3 U22 K 1.2 VOUT E2 5 ZXTD09N50DE6 B LM339A + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE CLK_DVDD/VCC/VDD_OUT_B/VDD_IN LEDS SIZE B 5 4 3 2 DOCUMENT NUMBER 6568778 REV NA PAGE 5 of 10 1 Figure 45. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 5 of 10 CLK_DVDD/VCC/VDD_OUT_B/VDD_IN LEDs SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 55 TLK10xxx EVM Voltage Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 5V 4P096V_REF9 5V 5V 4P096V_REF10 5V U25 2 IN_N 2 OUT 2 U27 C1 6 U26D LM339A 105K 14 R95 CLK_VDD_PLL_A 3 IN_N 3 OUT R98 2K B U26E CLK_VDD_PLL_A_B 8 + - 1 R100 10K CLK_VDD_PLL_A_3P0V_VREF 10 4 IN_P 4 IN_N 4 OUT 2 IN_N LM339A + - 2 OUT 2 U30 C1 6 E1 U29D R96 LM339A ZXTD09N50DE6 9 8 3P3V_CLK E2 3 IN_P 3 IN_N + - 3 OUT 14 R99 2K 11 13 10K 3P3V_CLK_3P0V_VREF 10 4 IN_P 4 IN_N 3P3V_CLK_L 2 BLUE D21 1 2 3 B2 1.65K 3P3V_CLK_3P6V_VREF R101 4 5V 5 1 C B1 3 4P096V_REF10 E2 R85 R84 CLK_VDD_PLL_L 2 4 2 IN_P 2 LM339A + - BLUE 1 10K CLK_VDD_PLL_3P0V_VREF B2 1.2K 1.2K 2 U29C 5 R93 U29E 11 1 R89 1 OUT 105K + - C2 1.65K 3 IN_P 1 IN_P 1 IN_N B1 C2 4 5V 4P096V_REF9 9 7 6 CLK_VDD_PLL R91 2K E1 CLK_VDD_PLL_A_3P6V_VREF CLK_VDD_PLL_3P6V_VREF LM339A + - 5V LM339A 1.65K 3P3V_CLK_C 2 IN_P 12 CLK_VDD_PLL_B 4 GND 3P3V_CLK_B 10K CLK_VDD_OUTA_3P0V_VREF R94 BLUE 1 5 R92 D19 1 CLK_VDD_OUTA_B U26C LM339A VCC U29B R88 1 1 OUT BLUE + - R87 1 IN_N U29A 4P096V_REF10 D18 6 CLK_VDD_OUTA 1 IN_P 105K 7 R90 2K C R83 LM339A 2 U26B 1.65K CLK_VDD_OUTA_3P6V_VREF 3 D20 5V 4P096V_REF9 5V C10 0.47uF REF2940 CLK_VDD_PLL_C 12 105K GND 5V 1 R97 VCC 2 GND VIN CLK_VDD_PLL_A_L LM339A 3 CLK_VDD_PLL_A_C 3 U26A CLK_VDD_OUTA_L 5V C9 0.47uF REF2940 R82 1 VIN R86 VOUT 5V GND CLK_VDD_OUTA_C 3 U28 1.2K VOUT 1.2K 2 5 ZXTD09N50DE6 B LM339A + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE 3P3V_CLK, CLK_VDD_PLL_A/_OUTA/_PLL LEDS SIZE B 5 4 3 2 DOCUMENT NUMBER 6568778 REV NA PAGE 6 of 10 1 Figure 46. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 6 of 10 3P3V_CLK, CLK_VDD_PLL_A/_OUTA/_PLL LEDs 56 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Voltage Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF11 5V 5V 5V 4P096V_REF12 5V U31 2 IN_N 2 OUT 4P096V_REF11 U33 C1 6 LM339A 3 IN_N 3 OUT 105K + - 14 R115 VDDRB_LS 3 IN_P R118 2K U32E VDDRB_LS_1P8V_B 8 B 4 5V U32D 1 5 R113 10K VDDRA_HS_1P35V_VREF 4 2 IN_P 2 IN_N R120 10K VDDRB_LS_1P675V_VREF 10 4 IN_P 4 IN_N + - 2 OUT 4 OUT 2 U36 C1 6 E1 C2 4P096V_REF12 E2 U35D R116 LM339A 12.4K VDDRA_HS_2P0V_VREF ZXTD09N50DE6 9 8 VDDRA_HS 3 IN_P 3 IN_N + - 3 OUT 14 R119 2K 13 11 R121 4 5V 5 10K VDDRA_HS_1P675V_VREF 10 4 IN_P 4 IN_N 1 R105 VDDRA_HS_1P8V_L 2 BLUE D25 C B1 3 LM339A + - VDDRA_HS_1P5V_L LM339A 2 B2 1.2K 1.2K R104 U35C U35E 11 1 BLUE 1.2K 2 2 1 OUT D24 + - R109 1 IN_N 105K 1 IN_P B1 12.4K 9 BLUE 1 2 C2 VDDRB_LS_2P0V_VREF 6 LM339A + - 7 VDDRA_HS R111 2K E1 R114 VDDRA_HS_1P625V_VREF 1 2 IN_P 5V LM339A 18K VDDRA_HS_1P8V_C 4 12 VDDRA_HS_1P5V_B VDDRB_LS_1P35V_VREF GND VDDRA_HS_1P8V_B 5 10K D23 1 VDDRB_LS_1P5V_B U32C LM339A VCC U35B R108 1 1 OUT BLUE + - R107 1 IN_N U35A 4P096V_REF12 D22 6 VDDRB_LS 1 IN_P 105K 7 R110 2K R112 R103 LM339A 2 U32B 18K VDDRB_LS_1P625V_VREF 3 1 5V 5V C12 0.47uF REF2940 VDDRA_HS_1P5V_C 12 105K GND 5V 1 R117 VCC 2 GND VIN VDDRB_LS_1P8V_L LM339A 4P096V_REF11 C VOUT 3 VDDRB_LS_1P8V_C 3 U32A VDDRB_LS_1P5V_L 5V C11 0.47uF REF2940 R102 1 VIN R106 U34 5V GND VDDRB_LS_1P5V_C 3 1.2K 2 VOUT 2 3 B2 E2 5 ZXTD09N50DE6 B LM339A + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE VDDRB_LS AND VDDRA_HS LEDS SIZE B 5 4 3 DOCUMENT NUMBER 6568778 2 REV NA PAGE 7 of 10 1 Figure 47. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 7 of 10 VDDRB_LS AND VDDRA_HS LEDs SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 57 TLK10xxx EVM Voltage Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 5V 4P096V_REF13 5V 5V 4P096V_REF14 5V U37 2 IN_N 2 OUT U39 C1 6 U38D LM339A 3 OUT 105K + - 14 R138 2K U38E VDDRA_LS_1P8V_B 3 IN_N R135 VDDRA_LS 3 IN_P 1 5 R133 10K VDDO_1P35V_VREF 4 2 IN_P 2 IN_N + - 2 OUT R140 10K VDDRA_LS_1P675V_VREF 10 4 IN_P 4 IN_N 4 OUT C1 6 U41D R136 LM339A 9 VDDO_2P0V_VREF 8 VDDO E2 3 IN_P 3 IN_N + - 3 OUT 14 R139 2K 13 11 10K VDDO_1P675V_VREF 10 4 IN_P 4 IN_N R125 2 BLUE D29 2 3 B2 12.4K ZXTD09N50DE6 R141 4 5V 4P096V_REF14 1 B1 C2 E2 VDDO_1P8V_L VDDO_1P5V_L U42 E1 LM339A + - 2 3 5 C LM339A 2 B2 1.2K 1.2K R124 U41C U41E 11 1 BLUE 1.2K 2 2 1 OUT D28 + - R129 1 IN_N 105K 1 IN_P B1 12.4K 8 B 4 5V 4P096V_REF13 9 BLUE 1 2 C2 VDDRA_LS_2P0V_VREF 6 LM339A + - 7 VDDO R131 2K E1 R134 VDDO_1P625V_VREF 1 2 IN_P 5V LM339A 18K VDDO_1P8V_C 4 12 VDDO_1P5V_B VDDRA_LS_1P35V_VREF GND VDDO_1P8V_B 5 10K D27 1 VDDRA_LS_1P5V_B U38C LM339A VCC U41B R128 1 1 OUT BLUE + - R127 1 IN_N U41A 4P096V_REF14 D26 6 VDDRA_LS 1 IN_P 105K 7 R130 2K R132 R123 LM339A 2 U38B 18K VDDRA_LS_1P625V_VREF 3 1 5V 5V C14 0.47uF REF2940 VDDO_1P5V_C 12 105K GND 5V 1 R137 VCC 2 GND VIN VDDRA_LS_1P8V_L LM339A 4P096V_REF13 C VOUT 3 VDDRA_LS_1P8V_C 3 U38A VDDRA_LS_1P5V_L 5V C13 0.47uF REF2940 R122 1 VIN R126 U40 5V GND VDDRA_LS_1P5V_C 3 1.2K 2 VOUT 5 ZXTD09N50DE6 B LM339A + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE VDDRA_LS AND VDDO LEDS SIZE B 5 4 3 DOCUMENT NUMBER 6568778 2 REV NA PAGE 8 of 10 1 Figure 48. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 8 of 10 VDDRA_LS AND VDDO LEDs 58 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Voltage Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF15 5V 5V 2 1.2K VOUT 5V U44A LM339A VCC GND 12 4P096V_REF15 5V C1 6 4 U44D LM339A 3 IN_N 3 OUT 14 R149 2K U44E B 11 10K 1P8V_1P675V_VREF 5 ZXTD09N50DE6 R151 1P8V E2 + - 1P8V_B 8 3 IN_P 105K 9 3 B2 12.4K 1P8V_2P0V_VREF 2 D9 C2 5V 1 B1 E1 4P096V_REF15 R41 U45 5V_L 2 2 2 OUT 1P8V_C + - BLUE 2 IN_N 1P5V_C 2 IN_P 1 4 LM339A 1P5V_B 10K 1P5V_1P35V_VREF R150 1.2K C U44C 5 R148 BLUE 1 R143 2K 5V D31 1 1 1 OUT BLUE + - D30 1 IN_N R145 1P5V 1 IN_P 105K 7 6 R144 2 LM339A 2 U44B 18K 1P5V_1P625V_VREF C 1P8V_L 3 C19 0.47uF REF2940 R146 1 1P5V_L VIN R147 5V GND R142 1.2K U43 3 10 4 IN_P 4 IN_N LM339A + - 4 OUT B 13 A A TEXAS INSTRUMENTS PAGE TITLE 1P5V, 1P8V, AND 5V LEDS 5 4 3 SIZE DOCUMENT NUMBER REV B 6568778 NA 2 PAGE 9 of 10 1 Figure 49. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 9 of 10 1.5-, 1.8-, and 5-V LEDs SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 59 TLK10xxx EVM Voltage Monitor Board Schematics 5 www.ti.com 4 3 2 1 1P0V_A1 5V 1P0V_A2 5V 2 1P0V_D1 DNI-2 Pin Berg 1 10uF C17 10uF 10uF D JMP1 C18 10uF 1P8V C16 1P5V C15 1P0V_D2 D 2P5V 3P3V VDDD DVDD 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 VDDO VDDRA_LS VDDRA_HS VDDRB_LS VDDRB_HS P1B 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 MEC1-130-02-F-D-A EDGE CARD VDDT C P1A 1 3 5 7 9 11 13 15 17 19 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 2 4 6 8 10 12 14 16 18 20 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 C MEC1-130-02-F-D-A EDGE CARD 5V VDDA 3P3V_CLK B B CLK_VDD_PLL CLK_VDD_PLL_A CLK_VDD_OUTA CLK_VDD_OUTB CLK_VDD_IN A A CLK_DVDD TEXAS INSTRUMENTS CLK_VCC PAGE TITLE VOLTAGE MONITOR BOARD CONNECTOR SIZE B 5 4 3 2 DOCUMENT NUMBER 6568778 REV NA PAGE 10 of 10 1 Figure 50. TLK10xxx EVM Voltage Monitor Board Schematic, Sheet 10 of 10 Edge Connector 60 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM Voltage Monitor Board Layout, Top Signal Layer www.ti.com D4 VOLTAGE MONITOR 6568778 REV NA D3 3p3V D31 2p5V D30 1p8V C16 C17 C18 TLK10xxx C15 5p0V 5V TLK10xxx EVM Voltage Monitor Board Layout, Top Signal Layer D9 16 GND JMP1 D6 1p5V D5 1p0V_A1 D2 1p0V_A2 D1 1p0V_D1 U2 C2 U8 C3 U5 C1 U44 C19 D13 1p0V_D2 D12 VDDA D11 VDDT D10 VDDD DVDD 1p8V 1p5V U32 C11 U35 C12 U38 C13 U41 C14 VDDO D28 D29 D26 D27 D24 D25 D22 D23 D7 D8 VDDRA_LS VDDRA_HS U14 VDDRB_LS C5 U17 C6 U26 C9 U29 C10 D21 3P3V_CLK D20 CLK_VDD_PLL D19 CLK_VDD_PLLA D18 CLK_VDD_OUTA D17 CLK_VDD_OUTB D16 CLK_VDD_IN D15 CLK_DVDD D14 VDDRB_HS CLK_VCC U23 C7 U20 C8 U11 C4 JN Figure 51. TLK10xxx EVM Voltage Monitor Board Layout, Top Signal Layer SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 61 TLK10xxx EVM Voltage Monitor Board Layout, Top Signal Layer www.ti.com Figure 52. TLK10xxx EVM Voltage Monitor Board Layout, Internal Ground (Layer 2) 62 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM Voltage Monitor Board Layout, Top Signal Layer www.ti.com Figure 53. TLK10xxx EVM Voltage Monitor Board Layout, Internal Power (Layer 3) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 63 TLK10xxx EVM Voltage Monitor Board Layout, Top Signal Layer www.ti.com R41 U6 R4 R3 R147 U45 R146 U9 R22 R35 R8 R16 R145 R151 R31 R39 R12 R20 R144 R150 R13 R25 R33 R7 U7 R149 U1 R18 R5 R37 U3 R17 R9 R21 R2 R143 R26 R19 R10 R14 R11 R29 R6 R15 R142 R148 U43 U4 R1 U18 R45 R44 U15 R43 R107 R115 R109 R117 R127 R135 R129 R137 R112 R120 R113 R121 R132 R140 R133 R141 R57 R87 R52 R60 R53 R61 R92 R102 U33 R103 R46 R54 R48 R56 R86 R23 U12 R24 R95 R97 R89 R101 R100 R93 R98 R59 R58 R94 R88 R96 U28 U25 U16 R99 R49 R105 R91 R55 U36 R136 U40 R90 R47 R104 R51 R123 R50 U39 U13 R134 R128 U37 R122 R139 R116 R126 U34 U31 R131 R114 R108 R138 R125 R130 R124 R119 U42 R111 R118 R110 R106 R42 R85 R84 R75 R28 R36 R80 R32 R40 R76 R66 R74 R27 U19 R38 U22 R78 R79 R68 R30 R67 R72 R70 U30 U27 R77 R81 R71 R83 R69 R73 R34 U10 R82 U24 R65 R64 U21 R63 R62 Figure 54. TLK10xxx EVM Voltage Monitor Board Layout, Bottom Signal (Layer 4) 64 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM Voltage Monitor Board Layout, Top Signal Layer www.ti.com Table 3 shows the EVM voltage monitor board layer construction. Table 3. TLK10xxx EVM Voltage Monitor Board Layer Construction Subclass Name TOP L2_GND L3_PWR BOTTOM Type Material Thickness (MIL) Dielectric Constant SURFACE AIR CONDUCTOR COPPER 2 1 DIELECTRIC FR-4 5 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 45 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 5 4.5 CONDUCTOR COPPER 2 1 SURFACE AIR Width (MIL) Coupling Type / Spacing (MIL) 8.5 (Single) None/None (Single) 8.5 (Single) None/None (Single) 1 Note: The impedance is set to be slightly less than 50 Ω or 100 Ω on the traces in order to compensate for slight over-etching during the manufacturing process. The end impedance after etching should result in a 50- or 100-Ω impedance. Always consult with your board manufacturer for their process and design requirements to ensure the desired impedance is achieved. SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 65 TLK10xxx EVM USB Dongle Board Schematics 17 www.ti.com TLK10xxx EVM USB Dongle Board Schematics Figure 55 through Figure 56 are illustrations of the USB Dongle board schematics. 5 4 3 2 1 REVISIONS NOTES: ECR NUMBER DATE ------- ECR xx/xx/xx 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS. 2. PLACE ALL PARTS ON A 0 OR 90 DEGREE ORIENTATION. 3. SERIAL DATA SHOULD BE ROUTED AS SINGLE-ENDED 50 OHM TRANSMISSION LINES ON OUTSIDE LAYERS. 4. USE FR4-370 MATERIAL FOR ALL LAYERS. 5. PCB MUST BE 0.062 IN THICK D D 6. MATES WITH SAMTEC CONNECTOR (MEC1-120-02-F-D-A) C C SCHEMATIC SHEET INDEX: SHEET 01: CIF USB DONGLE COVER SHEET AND NOTES SHEET 02: SCHEMATIC B B TEXAS INSTRUMENTS A A SCHEMATIC TITLE CIF GENRIC USB DONGLE ENGINEER J. NERGER DATE 11/11/11 PAGE TITLE LAYOUT G. ROTH RELEASED J. NERGER 5 4 3 2 DATE 11/11/11 DATE 11/11/11 COVER PAGE Size Document Number Rev B 6542126 NA Sheet of 2 1 1 Figure 55. TLK10xxx EVM USB Dongle Board Schematic, Sheet 1 of 2 Cover Page and Index 66 TLK10022 and TLK10081 Evaluation Module (EVM) SLLU187 – November 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TLK10xxx EVM USB Dongle Board Schematics www.ti.com 3 DP_CON C15 1M 1 USB Type B-mini Conn 61 60 22pF EE_SCL 52.3K 0 10uF 0.1uF R5 C5 .1uF C6 C7 .1K 30 R6 4.99K R41 TPS73701DRB 5V 3P3V 3P3V 3P3V 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 2K 2K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 3P3V R1 C1 1uF P3.0 R58 R59 R60 R61 R62 R63 R64 R65 R50 R51 R52 R53 R54 R55 R56 R57 P3.1 R42 R43 R44 R45 R46 R47 R48 R49 DNI_0 P3.6 P3.7 P0.7 P0.6 43 44 45 46 47 48 49 50 P0.0 P0.5 P0.1 P0.4 P0.2 P1.5 P0.3 P1.4 P0.4 P1.1 P0.5 P1.0 P0.6 P2.7 P0.7 P2.6 P2.5 31 32 33 34 35 36 40 41 S2 4.99K 5 21 24 42 59 12 11 EE_SCL_S EE_SDA P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 /VREN S2 S3 GND1 GND2 GND3 GND4 GND5 R7 R9 R11 R13 0 0 0 0 P7 R17 R19 R21 R23 R25 R27 R29 R31 R33 R35 R37 R39 0 0 0 0 0 0 0 0 0 0 0 0 P17 SCL SDA P1A 1 3 5 7 9 11 13 P9 P11 P13 17 19 21 23 25 27 29 31 33 35 37 39 P19 P21 P23 P25 P27 P29 P31 P33 P35 P37 P39 1 3 5 7 9 11 13 C 17 19 21 23 25 27 29 31 33 35 37 39 ETCH ON PCB EDGE P1.0 P1.1 NO PHYSICAL CONNECTOR 3P3V P1.2 P1.3 P1.4 R2 DNI_0 P1.5 P1.6 P1.7 C2 1uF 22 23 25 26 27 28 29 30 P2.1 P2.2 P3.2 P2.3 P3.3 P2.4 P3.4 P2.5 P3.5 R8 R10 R12 R14 0 0 0 0 R18 R20 R22 R24 R26 R28 R30 R32 R34 R36 R38 R40 0 0 0 0 0 0 0 0 0 0 0 0 P8 P10 P12 P14 P2.6 P2.7 P0.3 P0.2 P0.0 58 57 56 55 54 53 52 51 P3.0 P1.7 P3.1 P1.6 P3.2 P1.3 P3.3 P1.2 P3.4 P2.3 P3.5 P2.2 P3.6 P2.1 P3.7 P2.0 B P1B 2 4 6 8 10 12 14 P2.0 P0.1 P3.0/S0/RXD P3.1/S1/TXD P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 5V_CONN K 100 R77 USB_ONLINE_C D 100 TEST0 TEST1 TEST2 RSV1 RSV2 NC1 NC2 NC3 NC4 NC5 NC6 38 8 9 /VREN R98 4.99K 4.99K R96 R105 R106 R107 R97 DNI_4.99K 1.5K 1.5K EEPROM 24LC512-I/SM X1 X2 USB PROGRAMMING SWITCH SW2 1 PIN DIP SMD 1 2 WP FB 18 20 22 24 26 28 30 32 34 36 38 40 P18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38 P40 2 4 6 8 10 12 14 18 20 22 24 26 28 30 32 34 36 38 40 ETCH ON PCB EDGE A NO PHYSICAL CONNECTOR 14 15 20 1 4 2 3 6 7 63 64 A2 VCC A0 A1 WP A2 SCL VSS SDA 8 7 6 5 3 2 6 7 X2 4.99K 0.1uF 0.1uF 0.1uF C19 C18 C17 DNI_4.99K DNI_4.99K DNI_4.99K R99 R100 R101 A1 1 2 3 4 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 R92 C16 S3 U2 NC1 NC2 NC3 2 R93 R95 DNI_4.99K DNI_4.99K DNI_4.99K R94 12.00 MHZ 3P3V A0 TUSB3210 3P3V X1 R87 FB GND GPAD P2.4 X1 22pF 3P3V USB_ONLINE_L EN 0 MEC1-120-02-F-D-A EDGE CARD DM 33 33 4 9 3P3V R4 MEC1-120-02-F-D-A EDGE CARD R15 R16 PUR DP DM 5 EN 1 4.99K 4.99K DM_CON B TUSB3210 TEXAS INSTRUMENTS R108 R74 R75 R102 R103 R104 4.99K 4.99K 4.99K P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 C14 17 18 19 PUR 100 OUT 3P3V_CONN 3 R86 0 0.1uF 100K R91 1 2 PUR_R DP S2 S3 5V DM DP x GND 1 2 3 4 5 1.5K 16 1p8VDD 9 8 S1 S4 R89 6 7 USB INTERFACE Q1 MMBT4401LT1 13 USB_SUSPENDED 100K 0.1uF R90 C13 0.1uF 0.1uF PUR_EN 15K /RST 1P8VDD C9 10uF R88 VCC1 VCC2 VCC3 SUSP 37 100 3 4.99K 10 39 62 5V_USB C10 1uF MMBT4401LT1 USB_RST_N U1 C12 C11 C A 49.9 100K 3P3V B3U-1100P J1 R81 R82 R85 IN 3p3V_REG DNI_4.99K DNI_4.99K 4.99K 4.99K DNI_4.02K DNI_4.02K 4.99K 4.99K R79 R80 USB_/RST USB_RST USB_ONLINE TPS3125J18 USB_/MR 1 2 3 /RST GND RST /MR 2 4.99K 1 VDD R83 4 USB_RST_L USB ONLINE LED D4 GREEN 1 2 Q2 1USB_SUSP_B U4 5 0.1uF R78 SW1 2 3 3P3V AND RESET MONITOR C8 USB RESET PUSHBUTTON USB_SUSP_C RED USB SUSPEND LED D3 1 2 USB_SUSP_L 8 0 ORANGE ZXTD09N50DE6 3P3V USB RESET LED D2 2 1 (5V TO 3.3V) U3 5V R3 USB_RST_C 5 100K 100K E2 VOLTAGE SUPERVISOR 5V_USB 100 10uF 3 B2 D 3P3V R84 0.1uF 2 1 ADJUSTABLE LDO REGULATOR 3P3V USB_/RST_L GREEN C2 4 2 USB /RESET LED D1 2 B1 E1 USB_RST_B 1 USB_/RST_C R66 R67 R68 R69 R70 R71 R72 R73 C1 6 USB_/RST_B 1 C4 U5 C3 4 R76 5 5 PAGE TITLE CIF GENERIC USB DONGLE SCHEMATIC 4 3 SIZE DOCUMENT NUMBER REV B 6542126 NA 2 PAGE 2 of 2 1 Figure 56. TLK10xxx EVM USB Dongle Board Schematic, Sheet 2 of 2 Schematics SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 67 TLK10xxx EVM USB Dongle Board Layout 18 www.ti.com TLK10xxx EVM USB Dongle Board Layout Figure 57 through Figure 60 are illustrations of the USB Dongle board layout. J1 D2 D3 D4 USB RST RST SUSPND ONLINE D1 R41 C4 C3 SW2 R78 C16 C15 U2 R66 R74 R75 R67 R68 R69 R70 R71 R72 R73 R49 R48 R58 R59 C13 R60 R61 SW1 R47 R46 R45 R44 R43 R42 C12 R57 R56 R93 R96 R55 R54 R53 R52 U4 RST Q1 R92 R62 R63 R64 R65 R50 R51 C14 R91 R90 R17 R19 R21 R23 R25 R27 R29 R31 R33 R35 R37 R39 C1 R7 R9 R11 R13 R1 Figure 57. TLK10xxx EVM USB Dongle Board Layout, Top Signal Layer 68 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM USB Dongle Board Layout www.ti.com 5V 5V_USB 3p3V Figure 58. TLK10xxx EVM USB Dole Board Layout, Internal Power (Layer 2) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 69 TLK10xxx EVM USB Dongle Board Layout www.ti.com Figure 59. TLK10xxx EVM USB Dongle Board Layout, Internal GND (Layer 3) 70 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback TLK10xxx EVM USB Dongle Board Layout www.ti.com R87 R86 R85 R84 C10 C9 R76 Q2 R77 R80 R79 USB R15 R16 U5 C6 C7 R88 R4 C18 C17 R105 R108 R106 R107 C11 R83 C5 R5 R3 R98 R95 R94 R97 R99 R102 R100 R103 R101 R104 C19 R6 U3 U1 R89 R81 C8 R82 NJ R2 R40 R38 R36 R34 R32 R30 R28 R26 R24 R22 R20 R18 R14 R12 R10 R8 C2 Figure 60. TLK10xxx EVM USB Dongle Board Layout, Bottom Signal (Layer 4 Top View) SLLU187 – November 2013 Submit Documentation Feedback TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated 71 TLK10xxx EVM USB Dongle Board Layout www.ti.com Table 4 is the USB dongle board layer construction for this EVM. Table 4. TLK10xxx EVM USB Dongle Board Layer Construction Subclass Name TOP L2_GND L3_PWR BOTTOM Type Material Thickness (MIL) Dielectric Constant SURFACE AIR CONDUCTOR COPPER 2 1 DIELECTRIC FR-4 5 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 45 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 5 4.5 CONDUCTOR COPPER 2 1 SURFACE AIR Width (MIL) Coupling Type / Spacing (MIL) 8.5 (Single) None/None (Single) 8.5 (Single) None/None (Single) 1 Note: The impedance is set to be slightly less than 50 Ω or 100 Ω on the traces in order to compensate for slight over-etching during the manufacturing process. The end impedance after etching should result in a 50- or 100-Ω impedance. Always consult with your board manufacturer for their process and design requirements to ensure the desired impedance is achieved. 72 TLK10022 and TLK10081 Evaluation Module (EVM) Copyright © 2013, Texas Instruments Incorporated SLLU187 – November 2013 Submit Documentation Feedback EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety programs, please visit www.ti.com/esh or contact TI. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. REGULATORY COMPLIANCE INFORMATION As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal Communications Commission (FCC) and Industry Canada (IC) rules. For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. General Statement for EVMs including a radio User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization. For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant Caution This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and receiver. • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consult the dealer or an experienced radio/TV technician for help. For EVMs annotated as IC – INDUSTRY CANADA Compliant This Class A or B digital apparatus complies with Canadian ICES-003. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. Concerning EVMs including radio transmitters This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concerning EVMs including detachable antennas Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada. Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de l'utilisateur pour actionner l'équipement. Concernant les EVMs avec appareils radio Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER 【Important Notice for Users of EVMs for RF Products in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product, or Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. 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It is intended solely for use for preliminary feasibility evaluation in laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end product. Your Sole Responsibility and Risk. You acknowledge, represent and agree that: 1. 2. 3. 4. You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees, affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes. 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Any loads applied outside of the specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please be aware that these devices may be very warm to the touch. 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