CY7C1338G 4-Mbit (128 K × 32) Flow-Through Sync SRAM 4-Mbit (128 K × 32) Flow-Through Sync SRAM Features first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:D], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. ■ 128 K × 32 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output times ❐ 8.0 ns (100-MHz version) ■ Provide high-performance 2-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ Offered in Pb-free 100-pin TQFP package ■ “ZZ” sleep mode option The CY7C1338G allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Functional Description The CY7C1338G is a 128 K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.0 ns (100-MHz version). A 2-bit on-chip counter captures the The CY7C1338G operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. For a complete list of related documentation, click here. Logic Block Diagram ADDRESS REGISTER A0, A1, A A[1:0] MODE BURST Q1 COUNTER AND LOGIC Q0 CLR ADV CLK ADSC ADSP DQD BYTE DQD BYTE BWD WRITE REGISTER WRITE REGISTER DQC BYTE DQC BYTE BWC WRITE REGISTER WRITE REGISTER DQB BYTE DQB BYTE BWB MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs WRITE REGISTER WRITE REGISTER DQA BYTE WRITE REGISTER DQA BYTE BWA WRITE REGISTER BWE INPUT REGISTERS GW ENABLE REGISTER CE1 CE2 CE3 OE ZZ SLEEP CONTROL Cypress Semiconductor Corporation Document Number: 38-05521 Rev. *N • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 10, 2014 CY7C1338G Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Pin Definitions .................................................................. 4 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Single Write Accesses Initiated by ADSP ................... 6 Single Write Accesses Initiated by ADSC ................... 6 Burst Sequences ......................................................... 6 Sleep Mode ................................................................. 6 Interleaved Burst Address Table ................................. 7 Linear Burst Address Table ......................................... 7 ZZ Mode Electrical Characteristics .............................. 7 Truth Table ........................................................................ 8 Partial Truth Table for Read/Write .................................. 9 Maximum Ratings ........................................................... 10 Operating Range ............................................................. 10 Electrical Characteristics ............................................... 10 Capacitance .................................................................... 11 Thermal Resistance ........................................................ 11 AC Test Loads and Waveforms ..................................... 11 Switching Characteristics .............................................. 12 Timing Diagrams ............................................................ 13 Ordering Information ...................................................... 17 Ordering Code Definitions ......................................... 17 Package Diagrams .......................................................... 18 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Errata ............................................................................... 20 Part Numbers Affected .............................................. 20 Product Status ........................................................... 20 Ram9 Sync ZZ Pin Issues Errata Summary .............. 20 Document History Page ................................................. 21 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support ....................... 23 Products .................................................................... 23 PSoC® Solutions ...................................................... 23 Cypress Developer Community ................................. 23 Technical Support ..................................................... 23 Errata: For information on silicon errata, see "Errata" on page 20. Details include trigger conditions, devices affected, and proposed workaround. Document Number: 38-05521 Rev. *N Page 2 of 23 CY7C1338G Selection Guide Description 100 MHz 8.0 205 40 Maximum access time Maximum operating current Maximum standby current Unit ns mA mA Pin Configurations A A 44 45 46 47 48 49 50 A A A A A A A 40 VSS 43 39 NC/9M 38 NC/72M NC/36M 42 37 A0 41 36 A1 VDD 35 A NC/18M 34 81 82 83 84 BWE GW OE ADSC ADSP ADV 85 86 87 CLK 89 88 VDD VSS 91 90 BWA CE3 93 92 BWC BWB BWD 96 94 CE2 97 95 A CE1 98 A 99 31 VSSQ VDDQ DQD DQD NC 33 VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1338G A BYTE D DQC DQC VSSQ VDDQ DQC DQC NC VDD NC A BYTE C 32 VDDQ VSSQ DQC DQC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A NC DQC DQC 100 Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1] NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC BYTE B VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA BYTE A VSSQ VDDQ DQA DQA NC Note 1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 20. Document Number: 38-05521 Rev. *N Page 3 of 23 CY7C1338G Pin Definitions Name I/O Description A0, A1, A InputAddress inputs used to select one of the 128 K address locations. Sampled at the rising edge of synchronous the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. BWA, BWB, BWC, BWD InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled synchronous on the rising edge of CLK. GW InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write synchronous is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE). BWE InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted synchronous LOW to conduct a byte write. CLK Input-clock CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. OE InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance input signal, sampled on the rising edge of CLK. When asserted, it automatically synchronous increments the address in a burst cycle. ADSP InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, synchronous addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ[2] InputZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” asynchronous condition with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an internal pull-down. Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Note 2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 20. Document Number: 38-05521 Rev. *N Page 4 of 23 CY7C1338G Pin Definitions (continued) Name DQs VDD I/O Description I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a tri-state condition. Power supply Power supply inputs to the core of the device. Ground Ground for the core of the device. VDDQ I/O power supply Power supply for the I/O circuitry. VSSQ I/O ground Ground for the I/O circuitry. VSS MODE Inputstatic NC NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M, NC/1G Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode pin has an internal pull-up. No connects. Not Internally connected to the die. – No connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to the die. Document Number: 38-05521 Rev. *N Page 5 of 23 CY7C1338G Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t C0) is 8.0 ns (100-MHz device). The CY7C1338G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. appropriate data will be latched and written into the device. Byte writes are allowed. During byte writes, BWA controls DQA and BWB controls DQB. BWC controls DQC, and BWD controls DQD. All I/Os are tri-stated during a byte write.Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[A:D]) indicate a write access. ADSC is ignored if ADSP is active LOW. Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] will be written into the specified address location. Byte writes are allowed. During byte writes, BWA controls DQA, BWB controls DQB, BWC controls DQC, and BWD controls DQD. All I/Os are tri-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Single Read Accesses Burst Sequences A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. The CY7C1338G provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BW[A:D]) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:D]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the Document Number: 38-05521 Rev. *N Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 6 of 23 CY7C1338G Interleaved Burst Address Table Linear Burst Address Table (MODE = Floating or VDD) (MODE = GND) First Address A1:A0 00 01 10 11 Second Address A1:A0 01 00 11 10 Third Address A1:A0 10 11 00 01 Fourth Address A1:A0 11 10 01 00 First Address A1:A0 00 01 10 11 Second Address A1:A0 01 10 11 00 Third Address A1:A0 10 11 00 01 Fourth Address A1:A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V tZZS Device operation to ZZ ZZ > VDD – 0.2 V tZZREC ZZ recovery time ZZ < 0.2 V tZZI ZZ active to sleep current tRZZI ZZ inactive to exit sleep current Document Number: 38-05521 Rev. *N Min Max Unit – 40 mA – 2tCYC ns 2tCYC – ns This parameter is sampled – 2tCYC ns This parameter is sampled 0 – ns Page 7 of 23 CY7C1338G Truth Table The truth table for CY7C1338G follows. [3, 4, 5, 6, 7] Cycle Description Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected cycle, power-down None H X X L X L X X X L–H Tri-state Deselected cycle, power-down None L L X L L X X X X L–H Tri-state Deselected cycle, power-down None L X H L L X X X X L–H Tri-state Deselected cycle, power-down None L L X L H L X X X L–H Tri-state Deselected cycle, power-down None X X X L H L X X X L–H Tri-state Sleep mode, power-down None X X X H X X X X X X Tri-state Q Read cycle, begin burst External L H L L L X X X L L–H Read cycle, begin burst External L H L L L X X X H L–H Tri-state Write cycle, begin burst External L H L L H L X L X L–H D Read cycle, begin burst External L H L L H L X H L L–H Q Read cycle, begin burst External L H L L H L X H H L–H Tri-state Read cycle, continue burst Next X X X L H H L H L L–H Read cycle, continue burst Next X X X L H H L H H L–H Tri-state Read cycle, continue burst Next H X X L X H L H L L–H Read cycle, continue burst Next H X X L X H L H H L–H Tri-state Write cycle, continue burst Next X X X L H H L L X L–H D Write cycle, continue burst Next H X X L X H L L X L–H D Read cycle, suspend burst Current X X X L H H H H L L–H Q Read cycle, suspend burst Current X X X L H H H H H L–H Tri-state Read cycle, suspend burst Current H X X L X H H H L L–H Read cycle, suspend burst Current H X X L X H H H H L–H Tri-state Write cycle, suspend burst Current X X X L H H H L X L–H D Write cycle, suspend burst Current H X X L X H H L X L–H D Q Q Q Notes 3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more byte write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 38-05521 Rev. *N Page 8 of 23 CY7C1338G Partial Truth Table for Read/Write The partial truth table for Read/Write for CY7C1338G follows. [8, 9] GW BWE BWD BWC BWB BWA Read Function H H X X X X Read H L H H H H Write byte A H L H H H L Write byte B H L H H L H Write bytes B, A H L H H L L Write byte C H L H L H H Write bytes C, A H L H L H L Write bytes C, B H L H L L H Write bytes C, B, A H L H L L L Write byte D H L L H H H Write bytes D, A H L L H H L Write bytes D, B H L L H L H Write bytes D, B, A H L L H L L Write bytes D, B H L L L H H Write bytes D, B, A H L L L H L Write bytes D, C, A H L L L L H Write all bytes H L L L L L Write all bytes L X X X X X Notes 8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document Number: 38-05521 Rev. *N Page 9 of 23 CY7C1338G Maximum Ratings DC input voltage ................................. –0.5 V to VDD + 0.5 V Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, method 3015) ......................... > 2001 V Latch-up current ................................................... > 200 mA Operating Range Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD Range Ambient Temperature DC voltage applied to outputs in tri-state ..........................................–0.5 V to VDDQ + 0.5 V Commercial 0 °C to +70 °C VDD VDDQ 3.3 V5% / 2.5 V – 5% to + 10% VDD Electrical Characteristics Over the Operating Range Parameter [10, 11] Description Test Conditions Min Max Unit VDD Power supply voltage 3.135 3.6 V VDDQ I/O supply voltage 2.375 VDD V VOH Output HIGH voltage for 3.3 V I/O, IOH = –4.0 mA 2.4 – V for 2.5 V I/O, IOH = –1.0 mA 2.0 – V for 3.3 V I/O, IOL = 8.0 mA – 0.4 V for 2.5 V I/O, IOL = 1.0 mA – 0.4 V VOL VIH VIL IX Output LOW voltage Input HIGH voltage for 3.3 V I/O 2.0 VDD + 0.3 V for 2.5 V I/O 1.7 VDD + 0.3 V for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O –0.3 0.7 V Input leakage current except ZZ GND VI VDDQ and MODE –5 5 µA Input current of MODE Input = VSS –30 – µA Input = VDD – 5 µA Input = VSS –5 – µA Input = VDD – 30 µA Input LOW voltage [10] Input current of ZZ IOZ Output leakage current GND VI VDDQ, output disabled –5 5 µA IDD VDD operating supply current VDD = Max, IOUT = 0 mA, f = fMAX= 1/tCYC 10-ns cycle, 100 MHz – 205 mA ISB1 Automatic CE power-down current – TTL inputs 10-ns cycle, Max VDD, device deselected, VIN VIH or VIN VIL, f = fMAX, 100 MHz inputs switching – 80 mA ISB2 Automatic CE power-down current – CMOS inputs 10-ns cycle, Max VDD, device deselected, VIN VDD – 0.3 V or VIN 0.3 V, 100 MHz f = 0, inputs static – 40 mA ISB3 Automatic CE power-down current – CMOS inputs Max VDD, device deselected, 10-ns cycle, VIN VDDQ – 0.3 V or VIN 0.3 V, 100 MHz f = fMAX, inputs switching – 65 mA ISB4 Automatic CE power-down current – TTL inputs Max VDD, device deselected, 10-ns cycle, VIN VDD – 0.3 V or VIN 0.3 V, 100 MHz f = 0, inputs static – 45 mA Notes 10. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 11. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ VDD. Document Number: 38-05521 Rev. *N Page 10 of 23 CY7C1338G Capacitance Parameter [12] Description CIN Input capacitance CCLK Clock input capacitance CI/O Input/Output capacitance 100-pin TQFP Max Test Conditions Unit 5 pF 5 pF 5 pF Test Conditions 100-pin TQFP Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 30.32 °C/W 6.85 °C/W TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 3.3 V Thermal Resistance Parameter [12] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 VT = 1.5 V 2.5 V I/O Test Load (a) INCLUDING JIG AND SCOPE OUTPUT RL = 50 Z0 = 50 VT = 1.25 V (a) GND 5 pF R = 351 10% (c) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE 1 ns (b) GND 5 pF 90% 10% 90% 1 ns R = 1667 2.5 V OUTPUT ALL INPUT PULSES VDDQ R =1538 (b) 10% 90% 10% 90% 1ns 1ns (c) Note 12. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05521 Rev. *N Page 11 of 23 CY7C1338G Switching Characteristics Over the Operating Range Parameter [13, 14] Description -100 Unit Min Max VDD(typical) to the first access [15] 1 – ms tCYC Clock cycle time 10 – ns tCH Clock HIGH 4.0 – ns tCL Clock LOW 4.0 – ns tPOWER Clock Output Times tCDV Data output valid after CLK rise – 8.0 ns tDOH Data output hold after CLK rise 2.0 – ns 0 – ns – 3.5 ns – 3.5 ns 0 – ns – 3.5 ns [16, 17, 18] tCLZ Clock to low Z tCHZ Clock to high Z [16, 17, 18] tOEV OE LOW to output valid tOELZ tOEHZ OE LOW to output low Z [16, 17, 18] OE HIGH to output high Z [16, 17, 18] Setup Times tAS Address set-up before CLK rise 2.0 – ns tADS ADSP, ADSC set-up before CLK rise 2.0 – ns tADVS ADV set-up before CLK rise 2.0 – ns tWES GW, BWE, BWX set-up before CLK rise 2.0 – ns tDS Data input set-up before CLK rise 1.5 – ns tCES Chip enable set-up 2.0 – ns tAH Address hold after CLK rise 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.5 – ns tWEH GW, BWE, BWX hold after CLK rise 0.5 – ns Hold Times tADVH ADV hold after CLK rise 0.5 – ns tDH Data input hold after CLK rise 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – ns Notes 13. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 14. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted. 15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 16. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage. 17. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 18. This parameter is sampled and not 100% tested. Document Number: 38-05521 Rev. *N Page 12 of 23 CY7C1338G Timing Diagrams Figure 3. Read Cycle Timing [19] tCYC CLK t tADS t CL CH tADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 t WES t WEH GW, BWE,BW [A:D] tCES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst. OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t OELZ tCDV t CHZ tDOH Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 38-05521 Rev. *N Page 13 of 23 CY7C1338G Timing Diagrams (continued) Figure 4. Write Cycle Timing [20, 21] t CYC CLK t tADS t CH CL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BW[A:D] t t WES WEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t OEHZ t DS DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 20. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 21. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW. Document Number: 38-05521 Rev. *N Page 14 of 23 CY7C1338G Timing Diagrams (continued) Figure 5. Read/Write Timing [22, 23, 24] tCYC CLK t CH tADS tADH tAS tAH t CL ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) t t WES WEH BWE, BW[A:D] tCES tCEH CE ADV OE tDS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH tOELZ D(A3) tCDV Q(A2) Back-to-Back READs Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 23. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 24. GW is HIGH. Document Number: 38-05521 Rev. *N Page 15 of 23 CY7C1338G Timing Diagrams (continued) Figure 6. ZZ Mode Timing [25, 26] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 26. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05521 Rev. *N Page 16 of 23 CY7C1338G Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 100 Package Diagram Ordering Code CY7C1338G-100AXC Part and Package Type 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Operating Range Commercial Ordering Code Definitions CY 7 C 1338 G - 100 A X C Temperature Range: C = Commercial Pb-free Package Type: A = 100-pin TQFP Speed Grade: 100 MHz Process Technology: G 90 nm Part Identifier: 1338 = FT, 128 Kb × 32 (4 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05521 Rev. *N Page 17 of 23 CY7C1338G Package Diagrams Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *E Document Number: 38-05521 Rev. *N Page 18 of 23 CY7C1338G Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius EIA Electronic Industries Alliance MHz megahertz I/O Input/Output µA microampere JEDEC Joint Electron Devices Engineering Council mA milliampere OE Output Enable mm millimeter SRAM Static Random Access Memory ms millisecond TQFP Thin Quad Flat Pack mV millivolt TTL Transistor-Transistor Logic nm nanometer ns nanosecond ohm % percent Document Number: 38-05521 Rev. *N Symbol Unit of Measure pF picofarad V volt W watt Page 19 of 23 CY7C1338G Errata This section describes the Ram9 Sync ZZ pin issue. Details include trigger conditions, the devices affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions. Part Numbers Affected Density & Revision Package Type Operating Range 4Mb-Ram9 Synchronous SRAMs: CY7C133*G 100-pin TQFP Commercial Product Status All of the devices in the Ram9 4Mb Sync family are qualified and available in production quantities. Ram9 Sync ZZ Pin Issues Errata Summary The following table defines the errata applicable to available Ram9 4Mb Sync family devices. Item 1. Issues ZZ Pin Description Device When asserted HIGH, the ZZ pin places device in a “sleep” condition with data integrity preserved.The ZZ pin currently does not have an internal pull-down resistor and hence cannot be left floating externally by the user during normal mode of operation. 4M-Ram9 (90nm) Fix Status For the 4M Ram9 (90 nm) devices, there is no plan to fix this issue. 1. ZZ Pin Issue ■ PROBLEM DEFINITION The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the SRAM. ■ TRIGGER CONDITIONS Device operated with ZZ pin left floating. ■ SCOPE OF IMPACT When the ZZ pin is left floating, the device delivers incorrect data. ■ WORKAROUND Tie the ZZ pin externally to ground. ■ FIX STATUS For the 4M Ram9 (90 nm) devices, there is no plan to fix this issue. Document Number: 38-05521 Rev. *N Page 20 of 23 CY7C1338G Document History Page Document Title: CY7C1338G, 4-Mbit (128 K × 32) Flow-Through Sync SRAM Document Number: 38-05521 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 224369 See ECN RKF New data sheet. *A 278513 See ECN VBL Updated Features (Removed 66 MHz frequency related information). Updated Selection Guide (Removed 66 MHz frequency related information). Updated Electrical Characteristics (Removed 66 MHz frequency related information). Updated Switching Characteristics (Removed 66 MHz frequency related information). Updated Ordering Information (Updated part numbers (Added Pb-free BGA package), changed TQFP package to Pb-free TQFP package, added comment on the BGA Pb-free package availability below the table). *B 333626 See ECN SYT Updated Features (Removed 117 MHz frequency related information). Updated Selection Guide (Removed 117 MHz frequency related information). Updated Pin Configurations (Modified Address Expansion balls in the pinouts for 100-pin TQFP and 119-ball BGA Packages as per JEDEC standards). Updated Pin Definitions. Updated Functional Overview (Updated ZZ Mode Electrical Characteristics (Replaced ‘Snooze’ with ‘Sleep’)). Updated Truth Table (Replaced ‘Snooze’ with ‘Sleep’). Updated Electrical Characteristics (Updated test conditions for VOL and VOH parameters, removed 117 MHz frequency related information). Updated Thermal Resistance (Replaced TBD’s for JA and JC to their respective values). Updated Ordering Information (By shading and unshading MPNs as per availability, removed comment on the availability of BGA Pb-free package). *C 418633 See ECN RXU Changed status from Preliminary to Final. Changed address of Cypress Semiconductor Corporation from “3901 North First Street” to “198 Champion Court”. Updated Electrical Characteristics (Removed IOS parameter and its details, updated Note 11 (Changed test condition from VIH < VDD to VIH VDD), changed “Input Load Current except ZZ and MODE” to “Input Leakage Current except ZZ and MODE”). Updated Ordering Information (Updated part numbers, replaced Package Name column with Package Diagram in the Ordering Information table). Updated Package Diagrams. *D 480368 See ECN VKN Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND). Updated Ordering Information (Updated part numbers). *E 2896584 03/20/2010 NJY Updated Ordering Information (Removed obsolete part numbers). Updated Package Diagrams. *F 3036754 09/23/2010 NJY Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. *G 3365114 09/07/2011 PRIT Updated Package Diagrams. Document Number: 38-05521 Rev. *N Page 21 of 23 CY7C1338G Document History Page (continued) Document Title: CY7C1338G, 4-Mbit (128 K × 32) Flow-Through Sync SRAM Document Number: 38-05521 Orig. of Change Rev. ECN No. Issue Date Description of Change *H 3589101 05/10/2012 *I 3751125 09/21/2012 PRIT No technical updates. Completing sunset review. NJY / PRIT Updated Features (Removed 133 MHz frequency related information, removed 119-ball BGA package related information). Updated Functional Description (Removed the Note “For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.” and its reference, removed 133 MHz frequency related information). Updated Selection Guide (Removed 133 MHz frequency related information). Updated Pin Configurations (Removed 119-ball BGA package related information). Updated Functional Overview (Removed 133 MHz frequency related information). Updated Operating Range (Removed Industrial Temperature Range). Updated Electrical Characteristics (Removed 133 MHz frequency related information). Updated Capacitance (Removed 119-ball BGA package related information). Updated Thermal Resistance (Removed 119-ball BGA package related information). Updated Switching Characteristics (Removed 133 MHz frequency related information). Updated Package Diagrams (Removed 119-ball BGA package related information). *J 3984870 05/02/2013 PRIT Added Errata. *K 4039556 06/25/2013 PRIT Added Errata Footnotes. Updated in new template. *L 4050044 07/04/2013 PRIT Minor updates only (Correction in revision in footer). *M 4150660 10/08/2013 PRIT Updated Errata. *N 4592746 12/09/2014 PRIT Added related documentation hyperlink in page 1. Updated package diagram Document Number: 38-05521 Rev. *N Page 22 of 23 CY7C1338G Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05521 Rev. *N Revised December 10, 2014 Page 23 of 23 Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.