CY7C1444AV33 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Features Functional Description ■ Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O power supply ■ Fast clock-to-output times ❐ 3.4 ns (for 167-MHz device) ■ Provide high-performance 3-1-1-1 access rate ■ User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ CY7C1444AV33 available in JEDEC-standard Pb-free 100-pin TQFP package ■ “ZZ” sleep mode option The CY7C1444AV33 SRAM integrates 1 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. This part supports byte write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The CY7C1444AV33 operates from a +3.3 V core power supply while all outputs operate with a +3.3 V or a +2.5 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Description 167 MHz Unit Maximum access time 3.4 ns Maximum operating current 375 mA Maximum CMOS standby current 120 mA Cypress Semiconductor Corporation Document Number: 38-05352 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 14, 2012 CY7C1444AV33 Logic Block Diagram – CY7C1444AV33 ADDRESS REGISTER A0,A1,A 2 A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP BWD DQD,DQPD BYTE WRITE REGISTER DQD,DQPD BYTE WRITE DRIVER BWC DQc,DQPC BYTE WRITE REGISTER DQc,DQPC BYTE WRITE DRIVER DQB,DQPB BYTE WRITE REGISTER DQB,DQPB BYTE WRITE DRIVER BWB BWA BWE GW CE1 CE2 CE3 OE ZZ Document Number: 38-05352 Rev. *J SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQPA DQPB DQPC DQPD E DQA,DQPA BYTE WRITE DRIVER DQA,DQPA BYTE WRITE REGISTER ENABLE REGISTER MEMORY ARRAY PIPELINED ENABLE INPUT REGISTERS SLEEP CONTROL Page 2 of 23 CY7C1444AV33 Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Single Write Accesses Initiated by ADSP ................... 6 Single Write Accesses Initiated by ADSC ................... 6 Burst Sequences ......................................................... 6 Sleep Mode ................................................................. 7 Interleaved Burst Address Table ................................. 7 Linear Burst Address Table ......................................... 7 ZZ Mode Electrical Characteristics .............................. 7 Truth Table ........................................................................ 8 Truth Table for Read/Write .............................................. 9 Maximum Ratings ........................................................... 10 Operating Range ............................................................. 10 Electrical Characteristics ............................................... 10 Document Number: 38-05352 Rev. *J Capacitance .................................................................... 11 Thermal Resistance ........................................................ 11 AC Test Loads and Waveforms ..................................... 11 Switching Characteristics .............................................. 12 Switching Waveforms .................................................... 13 Ordering Information ...................................................... 17 Ordering Code Definitions ......................................... 17 Package Diagram ............................................................ 18 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support ....................... 23 Products .................................................................... 23 PSoC Solutions ......................................................... 23 Page 3 of 23 CY7C1444AV33 Pin Configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1444AV33 (1 M × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 NC/72M A VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout Document Number: 38-05352 Rev. *J Page 4 of 23 CY7C1444AV33 Pin Definitions Name I/O Description A0, A1, A InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit counter. BWA, BWB, BWC, BWD InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. synchronous Sampled on the rising edge of CLK. GW InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE). BWE InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted synchronous LOW to conduct a byte write. CLK Inputclock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. OE InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, asynchronous the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it synchronous automatically increments the address in a burst cycle. ADSP InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted synchronous LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs, DQPs I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. VDD Power supply Power supply inputs to the core of the device. VSS Ground Ground for the core of the device. VSSQ I/O ground Ground for the I/O circuitry. VDDQ I/O power supply Power supply for the I/O circuitry. MODE Inputstatic NC – Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode pin has an internal pull-up. No Connects. Not internally connected to the die. Document Number: 38-05352 Rev. *J Page 5 of 23 CY7C1444AV33 Pin Definitions (continued) Name NC/72M, NC/144M, NC/288M, NC/576M, NC/1G I/O Description – No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are address expansion pins are not internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1444AV33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous chip selects CE1, CE2, CE3 and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. The CY7C1444AV33 is a double-cycle deselect part. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately after the next clock rise. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into Document Number: 38-05352 Rev. *J the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BWX signals. The CY7C1444AV33 provides byte write capability that is described in the Write Cycle Description table. Asserting the byte write enable input (BWE) with the selected byte write input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1444AV33 is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1444AV33 is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will tri-state the output drivers. As a safety precaution, DQX are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1444AV33 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable Page 6 of 23 CY7C1444AV33 through the MODE input. Both read and write burst operations are supported. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1:A0 00 01 10 11 Second Address A1:A0 01 00 11 10 Third Address A1:A0 10 11 00 01 Fourth Address A1:A0 11 10 01 00 Third Address A1:A0 10 11 00 01 Fourth Address A1:A0 11 00 01 10 Linear Burst Address Table (MODE = GND) First Address A1:A0 00 01 10 11 Second Address A1:A0 01 10 11 00 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ inactive to exit sleep current Document Number: 38-05352 Rev. *J Test Conditions ZZ > VDD– 0.2 V ZZ > VDD – 0.2 V ZZ < 0.2 V This parameter is sampled This parameter is sampled Min – – 2tCYC – 0 Max 100 2tCYC – 2tCYC – Unit mA ns ns ns ns Page 7 of 23 CY7C1444AV33 Truth Table The truth table for CY7C1444AV33 follows. [1, 2, 3, 4, 5, 6] Operation Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect cycle, power-down None H X X L X L X X X L–H Tri-state Deselect cycle, power-down None L L X L L X X X X L–H Tri-state Deselect cycle, power-down None L X H L L X X X X L–H Tri-state Deselect cycle, power-down None L L X L H L X X X L–H Tri-state Deselect cycle, power-down None L X H L H L X X X L–H Tri-state Sleep mode, power-down None X X X H X X X X X X Tri-state Read cycle, begin burst External L H L L L X X X L L–H Q Read cycle, begin burst External L H L L L X X X H L–H Tri-state Write cycle, begin burst External L H L L H L X L X L–H D Read cycle, begin burst External L H L L H L X H L L–H Q Read cycle, begin burst External L H L L H L X H H L–H Tri-state Read cycle, continue burst Next X X X L H H L H L L–H Read cycle, continue burst Next X X X L H H L H H L–H Tri-state Read cycle, continue burst Next H X X L X H L H L L–H Read cycle, continue burst Next H X X L X H L H H L–H Tri-state Write cycle, continue burst Next X X X L H H L L X L–H Write cycle, continue burst Next H X X L X H L L X L–H D Read cycle, suspend burst Current X X X L H H H H L L–H Q Read cycle, suspend burst Current X X X L H H H H H L–H Tri-state Q Q D Read cycle, suspend burst Current H X X L X H H H L L–H Read cycle, suspend burst Current H X X L X H H H H L–H Tri-state Q Write cycle, suspend burst Current X X X L H H H L X L–H D Write cycle, suspend burst Current H X X L X H H L X L–H D Notes 1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. CE1, CE2, and CE3 are available only in the TQFP package. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 38-05352 Rev. *J Page 8 of 23 CY7C1444AV33 Truth Table for Read/Write The truth table for Read/Write for CY7C1444AV33 follows. [7, 8] Function (CY7C1444AV33) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write byte A – (DQA and DQPA) H L H H H L Write byte B – (DQB and DQPB) H L H H L H Write bytes B, A H L H H L L Write byte C – (DQC and DQPC) H L H L H H Write bytes C, A H L H L H L Write bytes C, B H L H L L H Write bytes C, B, A H L H L L L Write byte D – (DQD and DQPD) H L L H H H Write bytes D, A H L L H H L Write bytes D, B H L L H L H Write bytes D, B, A H L L H L L Write bytes D, C H L L L H H Write bytes D, C, A H L L L H L Write bytes D, C, B H L L L L H Write all bytes H L L L L L Write all bytes L X X X X X Notes 7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active. Document Number: 38-05352 Rev. *J Page 9 of 23 CY7C1444AV33 Maximum Ratings DC input voltage ................................. –0.5 V to VDD + 0.5 V Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, method 3015) ......................... > 2001 V Latch-up current ................................................... > 200 mA Operating Range Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD Range Ambient Temperature VDD VDDQ DC voltage applied to outputs in tri-state ..........................................–0.5 V to VDDQ + 0.5 V Commercial 0 °C to +70 °C 3.3 V– 5% / + 10% 2.5 V – 5% to VDD Electrical Characteristics Over the Operating Range Parameter [9, 10] Description VDD Power supply voltage VDDQ I/O supply voltage VOH VOL VIH VIL IX Output HIGH voltage Output LOW voltage Input HIGH voltage [9] Test Conditions Min Max Unit 3.135 3.6 V for 3.3 V I/O 3.135 VDD V for 2.5 V I/O 2.375 2.625 V for 3.3 V I/O, IOH =4.0 mA 2.4 – V for 2.5 V I/O, IOH =1.0 mA 2.0 – V for 3.3 V I/O, IOL =8.0 mA – 0.4 V for 2.5 V I/O, IOL = 1.0 mA – 0.4 V for 3.3 V I/O 2.0 VDD + 0.3 V V for 2.5 V I/O 1.7 VDD + 0.3 V V for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O –0.3 0.7 V Input leakage current except ZZ GND VI VDDQ and MODE –5 5 µA Input current of MODE Input = VSS –30 – µA Input = VDD – 5 µA Input = VSS –5 – µA Input = VDD – 30 µA Input LOW voltage [9] Input current of ZZ IOZ Output leakage current GND VI VDDQ, output disabled –5 5 µA IDD VDD operating supply current VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 6-ns cycle, 167 MHz – 375 mA ISB1 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, VIN VIH or VIN VIL, f = fMAX = 1/tCYC 6-ns cycle, 167 MHz – 225 mA ISB2 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, 6-ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 167 MHz f=0 – 120 mA Notes 9. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 10. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 38-05352 Rev. *J Page 10 of 23 CY7C1444AV33 Electrical Characteristics (continued) Over the Operating Range Parameter [9, 10] Test Conditions Min Max Unit ISB3 Automatic CE power-down current – CMOS inputs Description VDD = Max, device deselected, or 6-ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 167 MHz f = fMAX = 1/tCYC – 200 mA ISB4 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, VIN VIH or VIN VIL, f = 0 6-ns cycle, 167 MHz – 135 mA Capacitance Parameter [11] 100-pin TQFP Max Unit 6.5 pF 3 pF 5.5 pF Test Conditions 100-pin TQFP Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 25.21 C/W 2.28 C/W Description CIN Input capacitance CCLK Clock input capacitance CI/O Input/output capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V Thermal Resistance Parameter [11] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 351 VT = 1.5 V INCLUDING JIG AND SCOPE (a) ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1 ns 1 ns (c) (b) 2.5 V I/O Test Load R = 1667 2.5 V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 1538 VT = 1.25 V (a) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% 1 ns 1 ns (c) Note 11. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05352 Rev. *J Page 11 of 23 CY7C1444AV33 Switching Characteristics Over the Operating Range Parameter [12, 13] Description -167 Unit Min Max VDD(typical) to the first access [14] 1 – ms tCYC Clock cycle time 6 – ns tCH Clock HIGH 2.4 – ns tCL Clock LOW 2.4 – ns tPOWER Clock Output Times tCO Data output valid after CLK rise – 3.4 ns tDOH Data output hold after CLK rise 1.5 – ns 1.5 – ns tCLZ Clock to low Z [15, 16, 17] [15, 16, 17] tCHZ Clock to high Z tOEV OE LOW to output valid tOELZ OE LOW to output low Z [15, 16, 17] tOEHZ OE HIGH to output high Z [15, 16, 17] – 3.4 ns – 3.4 ns 0 – ns – 3.4 ns Set-up Times tAS Address set-up before CLK rise 1.5 – ns tADS ADSC, ADSP set-up before CLK rise 1.5 – ns tADVS ADV set-up before CLK rise 1.5 – ns tWES GW, BWE, BWX set-up before CLK rise 1.5 – ns tDS Data input set-up before CLK rise 1.5 – ns tCES Chip enable set-up before CLK rise 1.5 – ns Hold Times tAH Address hold after CLK rise 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.5 – ns tADVH ADV hold after CLK rise 0.5 – ns tWEH GW, BWE, BWX hold after CLK rise 0.5 – ns tDH Data input hold after CLK rise 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – ns Notes 12. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 13. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted. 14. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 15. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ± 200 mV from steady-state voltage. 16. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 17. This parameter is sampled and not 100% tested. Document Number: 38-05352 Rev. *J Page 12 of 23 CY7C1444AV33 Switching Waveforms Figure 3. Read Cycle Timing [18] tCYC CLK tCH tCL tADS tADH ADSP tADS tADH ADSC tAS ADDRESS tAH A1 A2 A3 Burst continued with new base address tWES tWEH GW, BWE,BW X Deselect cycle tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t Data Out (DQ) CLZ t OEHZ Q(A1) High-Z tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t CO Single READ BURST READ DON’T CARE Burst wraps around to its initial state UNDEFINED Note 18. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 38-05352 Rev. *J Page 13 of 23 CY7C1444AV33 Switching Waveforms (continued) Figure 4. Write Cycle Timing [19, 20] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t t DS DH Data in (D) High-Z t OEHZ D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document Number: 38-05352 Rev. *J Page 14 of 23 CY7C1444AV33 Switching Waveforms (continued) Figure 5. Read/Write Cycle Timing [21, 22, 23] tCYC CLK tCL tCH tADS tADH tAS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) tWES tWEH BWE, BWX tCES tCEH CE ADV OE tDS tCO Data In (D) tOELZ High-Z tCLZ Data Out (Q) tDH High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) Q(A2) Q(A4) BURST READ Single WRITE DON’T CARE Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 22. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 23. GW is HIGH. Document Number: 38-05352 Rev. *J Page 15 of 23 CY7C1444AV33 Switching Waveforms (continued) Figure 6. ZZ Mode Timing [24, 25] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 24. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 25. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05352 Rev. *J Page 16 of 23 CY7C1444AV33 Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 167 Package Diagram Ordering Code CY7C1444AV33-167AXC Part and Package Type 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Operating Range Commercial Ordering Code Definitions CY 7 C 1444 A V33 - 167 A X C Temperature range: C = Commercial Pb-free Package Type: A = 100-pin TQFP Frequency Range: 167 MHz V33 = 3.3 V Process Technology: A 90 nm Part Identifier: 1444 = DCD, 1 Mb × 36 (36 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05352 Rev. *J Page 17 of 23 CY7C1444AV33 Package Diagram Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *D Document Number: 38-05352 Rev. *J Page 18 of 23 CY7C1444AV33 Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C degree Celsius EIA electronic industries alliance MHz megahertz I/O input/output µA microampere JEDEC joint electron devices engineering council mA milliampere LSB least significant bit mm millimeter MSB most significant bit ms millisecond OE output enable mV millivolt SRAM static random access memory nm nanometer TQFP thin quad flat pack ns nanosecond TTL transistor-transistor logic ohm % percent Document Number: 38-05352 Rev. *J Symbol Unit of Measure pF picofarad V volt W watt Page 19 of 23 CY7C1444AV33 Document History Page Document Title: CY7C1444AV33, 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Document Number: 38-05352 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 124419 03/04/03 CGM New data sheet. *A 254910 See ECN SYT Updated Logic Block Diagram – CY7C1444AV33. Updated Logic Block Diagram – CY7C1445AV33. Updated Identification Register Definitions (Added Note “Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.” and referred the same in Device Depth (28:24)). Added Boundary Scan Order related information. Updated Electrical Characteristics (Updated values of IDD, IX and ISB parameters). Updated Switching Characteristics (Added tPOWER parameter and its details). Updated Switching Waveforms. Updated Package Diagram (Removed 119-ball PBGA package, changed 165-ball FBGA package from BB165C (15 × 17 × 1.20 mm) to BB165 (15 × 17 × 1.40 mm)). *B 303533 See ECN SYT Updated Electrical Characteristics (Changed Test Condition from VDD = Min. to VDD = Max for VOL parameter, changed maximum value of IDD from 450 mA, 400 mA, and 350 mA to 475 mA, 425 mA, and 375 mA for 250 MHz, 200 MHz, and 167 MHz frequencies respectively, changed maximum value of ISB1 parameter from 190 mA, 180 mA, and 170 mA to 225 mA for 250 MHz, 200 MHz, and 167 MHz frequencies respectively, changed maximum value of ISB2 parameter from 80 mA to 100 mA for all frequencies, changed maximum value of ISB3 from 180 mA, 170 mA, and 160 mA to 200 mA for 250 MHz, 200 MHz, and 167 MHz respectively, changed maximum value of ISB4 parameter from 100 mA to 110 mA for all frequencies). Updated Capacitance (Changed value of CIN, CCLK and CI/O to 6.5 pF, 3 pF, and 5.5 pF from 5 pF, 5 pF, and 7 pF for 100-pin TQFP Package). Updated Thermal Resistance (Replaced values of JA and JC parameters from TBD to respective Thermal Values for all Packages). Updated Switching Characteristics (Changed maximum value of tCO parameter from 3.0 ns to 3.2 ns for 200 MHz frequency, changed minimum value of tDOH parameter from 1.3 ns to 1.5 ns for 200 MHz frequency). Updated Ordering Information (Added lead-free information for 100-pin TQFP and 165-ball FBGA packages). *C 331778 See ECN SYT Updated Pin Configurations (Modified Address Expansion balls in the pinouts for 165-ball FBGA Package as per JEDEC standards). Updated Pin Definitions. Updated Operating Range (Added Industrial Temperature Range). Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH parameters, changed maximum value of ISB2 and ISB4 parameters from 100 mA and 110 mA to 120 mA and 135 mA respectively). Updated Capacitance (Changed value of CIN, CCLK and CI/O to 7 pF, 7 pF, and 6 pF from 5 pF, 5 pF, and 7 pF for 165-ball FBGA Package). Updated Ordering Information (By shading and Unshading MPNs as per availability). Document Number: 38-05352 Rev. *J Page 20 of 23 CY7C1444AV33 Document History Page (continued) Document Title: CY7C1444AV33, 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Document Number: 38-05352 Rev. ECN No. Submission Date Orig. of Change Description of Change *D 417509 See ECN RXU Changed status from Preliminary to Final. Changed address of Cypress Semiconductor Corporation from “3901 North First Street” to “198 Champion Court”. Updated Electrical Characteristics (Updated Note 10 (Modified test condition from VIH < VDD to VIH VDD), changed “Input Load Current except ZZ and MODE” to “Input Leakage Current except ZZ and MODE”, changed minimum value of IX corresponding to Input current of MODE (Input = VSS) from –5 A to –30 A, changed maximum value of IX corresponding to Input current of MODE (Input = VDD) from 30 A to 5 A respectively, changed minimum value of IX corresponding to Input current of ZZ (Input = VSS) from –30 A to –5 A, changed maximum value of IX corresponding to Input current of ZZ (Input = VDD) from 5 A to 30 A). Updated Ordering Information (Replaced Package Name column with Package Diagram in the Ordering Information table). Updated Package Diagram (spec 51-85050 (changed revision from *A to *B)). *E 473229 See ECN VKN Updated TAP AC Switching Characteristics (Changed minimum value of tTH, tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV parameter from 5 ns to 10 ns). Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND). Updated Ordering Information (Updated part numbers). *F 2898663 03/24/2010 NJY Updated Ordering Information (Removed inactive parts). Updated Package Diagram. *G 3042209 09/29/2010 NJY Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. *H 3263545 05/23/2011 NJY Updated Package Diagram. *I 3363203 09/05/2011 PRIT Updated in new template. Document Number: 38-05352 Rev. *J Page 21 of 23 CY7C1444AV33 Document History Page (continued) Document Title: CY7C1444AV33, 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Document Number: 38-05352 Rev. ECN No. Submission Date Orig. of Change Description of Change *J 3616631 05/14/2012 PRIT Updated Features (Removed 250 MHz, 200 MHz frequencies related information, removed CY7C1445AV33 related information, removed 165-ball FBGA package related information). Updated Functional Description (Removed CY7C1445AV33 related information, removed the Note “For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.” and its reference). Removed Logic Block Diagram – CY7C1445AV33. Updated Pin Configurations (Removed CY7C1445AV33 related information, removed 165-ball FBGA package related information). Updated Pin Definitions (Removed JTAG related information). Updated Functional Overview (Removed CY7C1445AV33 related information). Updated Truth Table (Removed CY7C1445AV33 related information). Removed Truth Table for Read/Write (Corresponding to CY7C1445AV33). Removed IEEE 1149.1 Serial Boundary Scan (JTAG). Removed TAP Controller State Diagram. Removed TAP Controller Block Diagram. Removed TAP Timing. Removed TAP AC Switching Characteristics. Removed 3.3 V TAP AC Test Conditions. Removed 3.3 V TAP AC Output Load Equivalent. Removed 2.5 V TAP AC Test Conditions. Removed 2.5 V TAP AC Output Load Equivalent. Removed TAP DC Electrical Characteristics and Operating Conditions. Removed Identification Register Definitions. Removed Scan Register Sizes. Removed Instruction Codes. Removed Boundary Scan Order. Updated Operating Range (Removed Industrial Temperature Range). Updated Electrical Characteristics (Removed 250 MHz, 200 MHz frequencies related information). Updated Capacitance (Removed 165-ball FBGA package related information). Updated Thermal Resistance (Removed 165-ball FBGA package related information). Updated Switching Characteristics (Removed 250 MHz, 200 MHz frequencies related information). Document Number: 38-05352 Rev. *J Page 22 of 23 CY7C1444AV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2003-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05352 Rev. *J Revised May 14, 2012 Page 23 of 23 i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.