IF Modulator/Demodulator IC Technical Data HPMX-5002 Features Plastic TQFP-48 Package • Use with HPMX-5001 Up/Down Converter Chip for DECT Telephone Applications X– HPM 3 943 5 643 • 2.7– 5.5 V Single Supply Voltage • >75 dB RSSI Range 2 500 019 • Internal Data Slicer • On-chip LO Generation, Including VCO, Prescalers and Phase/ Frequency Detector • Flexible Chip Biasing, Including Standby Mode Pin Configuration 48 1 • Supports Reference Crystal Frequencies of 9, 12, and 16 Times the DECT Bit Rate (1.152 MHz) • IF Input Frequency Range up to 250 MHz • TQFP-48 Surface Mount Package 37 36 HPMX–5002 9433 6435 12 13 019 25 24 Applications • DECT, Unlicensed PCS and ISM Band Handsets, Basestations and Wireless LANs 7-105 Description The Hewlett-Packard HPMX-5002 IF Modulator/Demodulator provides all of the active components necessary for the demodulation of a downconverted DECT signal. Designed specifically for DECT, the HPMX-5002 contains a down-conversion mixer (to a 2nd IF), limiting amplifier chain, discriminator/data slicer, lock detector, and RSSI circuits. The LO2 generation is also included on-chip, via a VCO, dividers, and phase/frequency detector. The divide ratios are programmable to support reference frequencies of either 9, 12, or 16 times the DECT bit rate of 1.152␣ MHz allowing the use of common, low cost crystals. The LO2 VCO can also be utilized in transmit mode by directly modulating the external VCO tank. An AGC loop in the buffered VCO output suppresses harmonics and reduces signal level variability. The HPMX-5002 is designed to meet the size and power demands of portable applications. Battery cell count and cost are reduced due to the 2.7 V minimum supply voltage. The TQFP-48 package, combined with the high level of integration, means smaller footprints and fewer components. Flexible chip biasing takes full advantage of the power savings inherent in time-duplexed systems such as DECT. 5965-9106E 3 2 1 5 6 7 8 100 kΩ 4 100 kΩ = connector 100 kΩ 0.1 µ 0.01 µ 0.01 µ 10 Ω 0.01 µ 100 p 0.01 µ 0Ω 3 to 10 p 0.01 µ DATOP LOCK DET LKFIL LKDET DC1A 1F1P1 VEE2 VCC2 XLO DC1B OSCOPB 0.01 µ D1V3 D1V2 D1V1 51.1 Ω 24 4400 p 330 p Figure 1. HPMX-5002 Test Board Schematic Diagram. 7-106 120 n 10 kΩ 22 p 0Ω 1000 p 1 kΩ 4.7 kΩ 3.3 kΩ 0.01 µ 0Ω 3.9 p 0.01 µ 0.01 µ 4 3 1000 p 5 2 0.01 µ 6 1 10 Ω 0.01 µ 0Ω 1 kΩ 1000 p 8.2 p 220 nH 8.2 p 1000 p 20 kΩ 20 kΩ 25 VEE3 0Ω 0Ω 270 nH VCOB 10 Ω 0.01 µ 0.01 µ VCOADJ CHARGE PUMP 12 13 22 p 8.2 p 0.01 µ 270 nH OSCOP 9/12/16 VCC3 49.9 Ω VSUB 90/216 REF 100 nH 1p 10 p 10 Ω IPDC AGC 1000 p 0.01 µ 0.01 µ VCC5 φ Freq. Det. RSS1 0Ω VEE5 VCOA 1000 p 10 p 3.9 µH 68 p IP1 0.01 µ 1 kΩ 0.01 µ 1 kΩ DATA SLICER TCSET 0Ω R S S I BUF2 TCNT 0.01 µ 20 kΩ RX VCC1 VEE4 0.01 µ BUF1 VCC4 4.7 kΩ IF1 VEE1 PFD 68 p DMOD DMODOP NC 0.01 µ 4.7 kΩ 1.2 k Ω 1p NC NC 49.9 Ω 36 1 0Ω 3.9 µH 37 IFOP1 22 p 1000 p 48 0.01 µ 100 p 1 kΩ 0Ω 0.01 µ 22 p PLL 3.9 p 6 kΩ NC NC 15 µH 2.7 µH 0.01 µ BGR 0.01 µ = terminal DC post 10 p 0.01 µ 10 kΩ 0.01 µ HPMX-5002 Functional Block Diagram IFIP1 DMOD IFOP1 IF1 DMODOP BUF2 TCSET BUF1 DATA SLICER IP1 DATAOP RSSI RSSI OSCOP 90/216 OSCOPB VCOADJ VCOB VCOA φ FREQ. DET. DIV2 9/12/16 DIV1 REF BIAS CONTROL CHARGE PUMP LOCK DET. PFD LKDET PLL DIV3 BGR XLO RX HPMX-5002 Absolute Maximum Ratings[1] Symbol Parameter Units Min. Max. V V mW °C °C -0.2 -0.2 Pdiss VCC Supply Voltage Voltage at any Pin[4] Power Dissipation[2,3] Junction Temperature Storage Temperature 7.5 VCC + 0.2 200 +110 +125 TSTG -55 Thermal Resistance [2]: θjc = 80°C/W Notes: 1. Operation of this device in excess of any of these parameters may cause permanent damage. 2. Tcase = 25°C 3. Derate at 10 mW/°C for Tcase > 90°C 4. Except CMOS logic inputs, see Summary Characterization Information Table. HPMX-5002 Guaranteed Electrical Specifications Unless otherwise noted, all parameters are guaranteed under the following conditions: 2.7 V < VCC < 5.5 V. Test results are based upon use of networks shown in test diagram (see Figure 1). fin = 110.592 MHz. Typical values are for VCCX = 3.0 V, TA = 25°C. Symbol Parameters and Test Conditions Units Min. Typ. Max. Iccx GIF1 VDATOP VDATOP Total Vccx supply current (PLL locked) (PLL locked) Charge pump current Charge pump current Mixer power gain from IP1 to IF1, external load impedance of 600 Ω Data slicer output level Data slicer output level RX mode mA 21 27 PLL mode TX “flywheel” mode Standby mode high current mode low current mode input matched to 50 Ω mA mA µA µA µA dB 16 9 400 30 5 20 11.5 100 1000 100 V V Vccx -0.3 Logic ‘0’ Logic ‘1’ 7-107 550 50 8 0.3 HPMX-5002 Summary Characterization Information Typical values measured on test board shown in Figure 1 at Vccx = 3.0 V, TA = 25°C, fin = 110.592 MHz, fLO2 = 103.68 MHz, unless otherwise noted. Symbol Parameters and Test Conditions Units Typ. V ≥ Vcc -0.8 CMOS input low voltage V ≤ 1.0 CMOS input high current µA <50 CMOS input low current µA > - 50 Mode switching time µS <1 VIH CMOS input high voltage (can be pulled up as high as Vcc+7V) VIL IIH IIL P1 dB IIP3 NFIF1 ZinIP1 Mixer input 1 dB compression point matched to 50 Ω source dBm -23 Mixer input IP3 matched to 50 Ω source dBm -17 dB 12 50 MHz < fin < 250 MHz Ω 100 RSSI dynamic range Note 1 (for signal input at IFIP1; RSSI output measured with 6 bit ADC) dB 75 mV/dB 17 V 0.88 1.48 2.04 kΩ 30 MHz 45 Mixer SSB noise figure (see test diagram Fig. 1) input matched to 50 Ω source, 600 Ω load at output Mixer input impedance RSSI voltage change RSSI output voltage. Vccx = 3 V, VRSSI is monotonic ZoutRSSI RSSI output impedance IF2f3 dB IF2 limiter bandwidth AVIF2 IF2 limiter voltage gain Note 1 2 IF limiter input level: - 90 dBm -50 dBm -20 dBm Prior to limiting, Note 2 dB 57 Note 2 Ω 600 mVp-p 335 ZinIFIP1 IF2 limiter input impedance at pin IFIP1 VoutLO2 LO2 output buffer differential amplitude >1.5 kΩ differential load, (between OSCOP and OSCOPB) fvco =103.68 MHz, VCC =3 V Bit slicer time constant ratio LO2 VCO output buffer noise floor (@ 4 MHz offset) TCSET =0 vs. TCSET = 1 tank circuit Q = 35 dBc/Hz PLL charge pump leakage current ILKDET Lock detector current sink 80:1 Logic ‘0’ (unlocked) -142 pA <100 mA 1.1 Notes: 1: RSSI signal is monotonic over stated dynamic range, but not necessarily linear. Voltage change is defined in the linear region of the transfer curve. 2: IF2 frequency in the range 1 MHz < f < 45 MHz, with 10 nF capacitors from DC1A and DC1B to ground. 7-108 HPMX-5002 Pin Description No. 1 Mnemonic IFOP1 I/O Type Analog O/P Description Output of IF amplifier, feeds quadrature network for discriminator 2 DMOD Analog I/P Input to discriminator mixer, driven by output of quadrature network 3 DMODOP Analog O/P Output of discriminator mixer, drives external low-pass data filter 4 BUF1 Analog I/P Noninverting input of buffer amplifier that drives the data slicer 5 BUF2 Analog O/P Output of buffer amplifer that drives the data slicer 6 TCNT Analog DC External capacitor connection which sets time constant for data slicer 7 TCSET CMOS I/P Data slicer time constant select 8 DATOP CMOS O/P Output bit stream from data slicer 9 RSSI Analog O/P Receive Signal Strength Indicator output 10 LKFIL Analog DC External capacitor connection which sets time constant for lock detector 11 LKDET CMOS O/P Indicates that LO2 PLL is in lock status 12 REF Analog I/P Reference signal for LO2 PLL 13 VCC3 DC Supply PLL supply voltage 14 VEE3 Ground 15 DIV1 CMOS I/P Controls divide ratio for reference frequency input to the LO2 PLL 16 DIV2 CMOS I/P Controls divide ratio for reference frequency input to the LO2 PLL 17 DIV3 CMOS I/P Controls divide ratio for VCO frequency input to the LO2 PLL 20 PFD Analog O/P 21 VEE4 Ground 22 VCC4 DC Supply LO2 VCO supply voltage 23 AGC Analog DC External capacitor connection to compensate LO2 VCO AGC loop 24 VCOA Analog I/P VCO tank force line 25 VCOB Analog O/P VCO tank sense line 26 VCOADJ Analog I/P Controls amplitude of buffered LO2 VCO output 27 OSCOP Analog O/P Buffered LO2 output (+) 28 OSCOPB Analog O/P Buffered LO2 output (-) 29 VCC5 DC Supply 1st IF supply voltage 30 VEE5 Ground 31 IPDC Analog DC External capacitor connection for decoupling 1st IF bias point 32 IP1 Analog I/P 1st IF input signal 33 VCC1 DC Supply IF limiting amplifier supply voltage 34 VEE1 Ground 35 IF1 Analog O/P Downconverted signal from front-end mixer, drives external filter (hi-Z output, open collector) 37 IFIP1 Analog I/P Input to IF limiting amplifier, driven by external filter (600 Ω impedance, internally set) 38 DC1A Analog DC External capacitor connection for decoupling IF limiting amplifier 39 VCC2 DC Supply IF limiting amplifier supply voltage 40 VEE2 Ground PLL ground LO2 PLL phase/frequency detector charge pump output LO2 VCO ground 1st IF ground IF limiting amplifier ground IF limiting amplifier ground 7-109 HPMX-5002 Pin Description, continued No. Mnemonic I/O Type Description 41 DC1B Analog DC External capacitor connection for decoupling IF limiting amplifier 42 VSUB Ground 43 XLO CMOS I/P Controls bias to VCO and PLL components in conjunction with PLL pin 44 PLL CMOS I/P Controls bias to VCO and PLL components in conjunction with XLO pin 45 RX CMOS I/P Controls bias to receive signal path, RSSI, data slicer 47 BGR Analog DC External capacitor connection for decoupling bandgap reference voltage 18,19, 36, 46, 48 N/C Not connected All unconnected pins should be connected to a low-noise ground Substrate connection Table 1: HPMX-5002 Mode Control Table 2: HPMX-5002 PLL Divider Programming (CMOS Logic Levels) (CMOS Logic Levels) Mode PLL TX RX STBY “flywheel” PLL 1 0 1 1 XLO 0 0 0 1 see text RX 1 1 0 1 REF divide by: 9 12 16 Not defined LO2 divide by: 90 216 7-110 DIV1 1 0 0 1 DIV2 0 0 1 1 DIV3 X X X X X X X X 0 1 IFIP1 DMOD DMODOP IFOP1 IF1 BUF2 TCSET BUF1 DATA SLICER IP1 RSSI RSSI OSCOP 90/216 OSCOPB VCOADJ VCOB VCOA DATAOP φ FREQ. DET. DIV2 9/12/16 DIV1 CHARGE PUMP LOCK DET. PFD LKDET BIAS CONTROL PLL DIV3 REF BGR XLO RX Figure 2. HPMX-5002 Detailed Block Diagram. Functional Description Please refer to Figure 2, Detailed Block Diagram, above. Figure 2 contains a graphical representation of all 32 active signal pins of the HPMX-5002. For clarity, the supply, ground, and substrate pins are deleted. Modes of Operation The HPMX-5002 supports four basic modes of operation. The logic states necessary to program each mode are listed in Table 1, Mode Programming. The modes are: Receive mode (RX), which is used during the receive time slot in DECT systems. All blocks are powered on in this mode. LO2 synthesis mode (PLL), which enables the IC to achieve phase lock without biasing the receive signal path, thus saving power. This is very useful for DECT blind-slot applications. Transmit mode (TX), designed for use when the LO2 VCO is directly modulated by the DECT data stream for subsequent up-conversion to the channel frequency (with the HPMX-5001 DECT Upconverter/Downconverter). In this mode, only the VCO and LO2 output buffer are biased and operational. In order to use the LO2 VCO as a modulation source, it is necessary to first program the HPMX-5002 in PLL mode. Once the loop has achieved lock, the PLL is then disabled by setting the PLL pin to a logic 0. This puts the VCO into “flywheel” operation, preventing the PLL from interfering with the modulation of the VCO. Leakage in the tank circuit shown in Figure 3 allows the VCO to drift at a rate of 2.5 kHz per mS, well within the DECT specs of 13 kHz per mS. 7-111 Standby mode, where all blocks are powered down. This mode allows the system designer to effectively turn the IC off without having to use battery control, and also allows the IC to change quickly to an active mode. Detailed Circuit Description PLL Section The PLL section of the HPMX-5002 contains three major sections: a set of reference and LO2 dividers, a phase/frequency detector with charge pump, and a lock detector. The dividers for both the reference and LO2 signals in the PLL section are programmable to accomodate the most popular DECT reference frequencies and also to enable the use of higher 1st IF frequencies if desired. Figure␣ 3 illustrates the logic states necessary to program both the reference and LO2 dividers. The reference divider ratios were selected to conform to the three most popular DECT reference frequencies of 10.368 MHz, 13.824␣ MHz, and 18.432 MHz. The LO2 divider values allow the use of either a 110.592 MHz or 112.32␣ MHz 1st IF with a divide value of 90 (which yields a LO2 of 103.68 MHz). In addition, the divide by 216 value permits the use of a much higher 1st IF (222.91␣ MHz, with a corresponding LO2 of 248.832 MHz), which enables the use of much smaller SAW filters and relaxes the image filtering requirements. The phase/frequency detector also incorporates a lock detection feature. The user must supply a decoupling capacitor (recommended value of 1 nF) from the LKFIL pin to ground. If the loop is not in phase lock, the LKDET pin will sink up to 1 mA. This open collector output is utilized so that this signal can be wire-ORed with other lock detection circuits, such as from the 1LO portion of the system. The pullup resistor can also be tied to the CMOS positive supply, thus eliminating potential problems with CMOS logic high voltages when different positive supplies are used between the radio and the baseband processor. When the PLL loop phase error is less than approximately 0.3␣ radians, the LKDET current sink goes to zero. VCO Section The VCO section has two major components, a sustaining amplifier and a buffered external output. The sustaining amplifer is designed to be used with an external tank circuit, and incorporates a force (VCOA) and sense (VCOB) architecture to reduce the effects of package parasitics. As described earlier, the VCOB pin may be overdriven by an external LO, in which case the on-chip sustaining amplifier acts as a buffer stage before the downconverting mixer. The buffered external output is a differential signal (OSCOP, OSCOPB). The buffer also incorporates an AGC loop in order to provide a sinusoidal output signal with constant amplitude which is insensitive to variations in tank Q and loading. This helps to suppress harmonics and eliminates therefore the need for an upconversion filter if the HPMX-5002 is used in a system together with the 2.5 GHz upconverter/downconverter HPMX-5001. The AGC requires an external compensation capacitor (recommended value 1 nF) from the AGC pin to ground. Signal Path The input to the HPMX-5002 is an AC-coupled IF signal (IP1). The input buffer before the downconverting mixer requires a decoupling capacitor from the IPDC pin to ground (recommended value 10 pF). The buffered input is then mixed with the LO2, and the output of the mixer (IF1) drives an off-chip bandpass filter centered at the IF2 frequency (6.9 MHz for a 110.592 MHz 1IF). The filtered signal is then fed to the IFIP1 pin, which is the input to the limiting amplifier chain. The limiting amplifier requires two external decoupling capacitors from pins DC1A and DC1B to ground (recommended value 10 nF). 7-112 The limiting amplifier chain also feeds the Received Signal Strength Indicator (RSSI) block. The RSSI signal is monotonic over a 75 dB dynamic range, and in its linear range varies at 17 mV/dB. The RSSI signal is designed to be digitized by the CMOS burst mode controller. The output of the limiting amplifier (IFOP1) drives the discriminator circuit. This signal is fed directly to one of the input ports of a Gilbert cell mixer, and it also drives an external quadrature network (with a recommended Q of 8 for optimum performance). The output of the external quadrature network is then fed into the other input port of the Gilbert cell (via the DMOD pin). The output of the Gilbert cell is taken at the DMODOP pin, which drives an external lowpass filter. To aid in the construction of the filter, a buffer stage is included on-chip. The BUF1 pin is the noninverting input of the buffer, and BUF2 is the output, which is also connected to the input of the data slicer. The data slicer operates on a dual time constant architecture, controlled via the TCSET pin. During the preamble portion of a DECT timeslot (with TCSET set to 1), the data slicer quickly acquires the midpoint voltage of the incoming data stream, correcting any DC offsets that may have occurred due to frequency deviations within the DECT specification. The value of this initial time constant is determined by an external capacitor connected between TCNT and ground. A 10␣ nF capacitor allows the accurate acquisition of the midpoint voltage within half of the 16-bit DECT preamble. Once the midpoint voltage has been acquired, TCSET is then forced to a 0, and the time constant of the midpoint voltage tracking circuit is increased by a factor of 80. This effectively freezes the midpoint voltage from any variations due to normal data transitions, but still allows for some correction of frequency drifts during the data burst. D: 1897.344 MHz B: 1881.792 MHz The output of the data slicer (DATOP) is a CMOS-compatible bitstream. However, it is recommended that an external NPN amplifier stage be used to drive the CMOS baseband processor, in order to minimize the amount of ground and supply currents in the HPMX-5002 which might desensitize the chip. CERAMIC TX PA TX FILTER 0: 893.376 MHz Rx 896.832 MHz Tx 9: 885.600 MHz Rx 889.056 MHz Tx 10.368 MHz FRONT-END RF FILTER RX LNA CERAMIC IMAGE FILTER REFERENCE OSCILLATOR Tank X2 T/R φ ÷N Freq. ÷12 Det. 32/33 HPMX-5001 IF2 = 6.912 MHz IF1 = 110.592 MHz LC Filter SAW Channel Filter SYNTHESIZER N=1034 -1025 INCL. /32,33 Rx N=1038 -1029 INCL. /32,33 Tx PFD FREQ. = 864 kHz LC filter Quad. Data Network Filter Data Slicer ÷9 φ Freq. Det. Charge Pump RSSI ÷9 Lock Det. HPMX-5002 PFD FREQ. = 1.152 MHz RC filter Tank LO2 = 103.68 MHz TX Data Gaussian LPF All other connections go to Burst Mode Controller, power source, or ground. Figure 3. Typical HPMX-5002 Application with HPMX-5001 T/R Chip. 7-113 RX DATA Circuit in the IC Small Signal Equivalent Circuit (typical values) Vcc 330 Ω IFOP1 IFOP1 Pin 1 V 9 kΩ DMOD DMOD Pin 2 Vcc 330 Ω DMODOP DMODOP Pin 3 V Vcc >50 kΩ BUF1 BUF1 Pin 4 Vcc 650 Ω BUF2 BUF2 Pin 5 Figure 4. HPMX-5002 Internal and Equivalent Circuits, Pins 1-5. 7-114 V Circuit in the IC Small Signal Equivalent Circuit (typical values) Vcc Pin 8 DATAOP Vcc Vcc Pin 9 RSSI RSSI 30 kΩ Vcc RSSI Pin 11 Vcc VCOA V VCOB Pins 24, 25 Vcc 65 Ω OSCOP OSCOPS Pins 27, 28 V Figure 5. HPMX-5002 Internal and Equivalent Circuits, Pins 8, 9, 11, 24, 25, 27, and 28. 7-115 OSCOP OSCOPB Circuit in the IC Small Signal Equivalent Circuit (typical values) Vcc IP1 Pin 32 100 Ω IP1 Vcc IF1 Pin 35 Vcc V IFIP1 Pin 37 IFIP1 Figure 6. HPMX-5002 Internal and Equivalent Circuits, Pins 32, 35, and 37. 7-116 600 Ω Package Dimensions 48 Pin Thin Quad Flat Package All dimensions shown in mm. 9.0±0.25 7.0±0.1 9.0±0.25 7.0±0.1 0.22 typ. 0.5 1.4±0.05 0.05 min., 0.1 max. 0.6+0.15, -0.10 Part Number Ordering Information Part Number HPMX-5002-STR HPMX-5002-TR1 HPMX-5002-TY1 No. of Devices 10 1000 250 Container Strip Tape and Reel Tray 7-117 Tape Dimensions and Product Orientation for Outline TQFP-48 REEL CARRIER TAPE USER FEED DIRECTION COVER TAPE 2.0 (See Note 7) 0.30 ± 0.05 1.5+0.1/-0.0 DIA 4.0 (See Note 2) 1.75 R 0.5 (2) 6435 BO 5.0 019 K1 KO HPMX – 5002 9433 1.6 (2) 7.5 (See Note 7) 6.4 (2) AO 12.0 1.5 Min. Cover tape width = 13.3 ± 0.1 mm Cover tape thickness = 0.051 mm (0.002 inch) AO = 9.3 mm BO = 9.3 mm KO = 2.2 mm K1 = 1.6 mm NOTES: 1. Dimensions are in millimeters 2. 10 sprocket hole pitch cumulative tolerance ±0.2 3. Chamber not to exceed 1 mm in 100 mm 4. Material: black conductive Advantek™ polystyrene 5. AO and BO measured on a plane 0.3 mm above the bottom of the pocket. 6. KO measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 7. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. 7-118 16.0 ± 0.3