TB32301AFL TENTATIVE TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB32301AFL 2.4-GHz Radio Communication IC Features • Consumption current : 35 mA (typ.) (at reception) : 26 mA (typ.) (at transmission) • Operating power supply voltage : 2.7 V to 3.3 V (operating temperature range: -20°C to 70°C) • Ultra-compact package: 36-pin QON • On-chip LNA • On-chip VCO • On-chip PA Weight: 0.08 g (typ.) Marking: TB32301AFL Block Diagram GND GND GND VCC RX2 RX1 IF-IN2 IF-IN1 RX2 RX3 AF2 AF1 D-DATA 27 26 25 24 23 22 21 20 19 28 MIX OUT1 18 RSSI FM-DET 29 MIX FIL 30 VCCRFRX RX LPF 17 FLLC1 Tuning RSSI 16 VCCRX2 VCCRX2 15 FLLC2 31 RF IN 32 GNDRF1 14 BS TX Filter 33 GNDRF2 ×2 VCO1 PLL1 DATA SET 34 TXOUT 35 VCCRFTX 36 VCCRF 13 TXIN 12 STB 11 CLK 10 DATA 1 VCC Syn3 2 VCC Syn2 3 4 5 6 7 LD LOOP GND GND GND FIL1 Syn2 Syn3 Syn1 8 REF CLK 9 VCC Syn1 This product is sensitive to electrostatic discharge. When handling the product, ensure that the environment is protected against electrostatic discharge. 1 Dec./5th/2002 TB32301AFL Pin Functions (typical resistor and capacitor values) Pin No. Pin Name Function Equivalent Circuit 1 VCCSyn3 Power supply pin 2 VCCSyn2 Power supply pin VCCsyn VCO 3 LOOPFIL1 3 External pin for loop filter GNDsyn 4 GNDSyn2 Ground pin 5 GNDSyn3 Ground pin 6 GNDSyn1 Ground pin 7 7 LD 500 Ω PLL lock detector output pin GND2 8 REFCLK Reference clock input pin for PLL, TX filter and IF auto tuning 9 VCCSyn1 Power supply pin 10 DATA Serial data input pin 11 CLK Serial clock input pin 12 STB Serial strobe input pin 8 10 11 12 13 13 TXIN 100 kΩ 1 kΩ 1 kΩ Transmit signal input pin 2 Dec./5th/2002 TB32301AFL Pin No. Pin Name Function Equivalent Circuit 1 kΩ 14 Auto-tuning pin. External capacitor determines the time constant of auto-tuning circuit. 17 FLL detector VCCRX2 Power supply pin 18 RSSI This pin drives out DC voltage according to the RF input signal level. 18 45 kΩ 16 100 Ω FLLC1 15 Internal reference voltage 17 IF input stage internal BPF FLLC2 FSK detection filter 15, Battery-saving pin Receive LPF (next stage of demodulator) BS Internal filer for transmit data 14 500 Ω 19 DDATA Comparator output pin 20 AF1 Demodulation signal output pin 10 kΩ 19 20 3 Dec./5th/2002 TB32301AFL VCCRX1 Function Equivalent Circuit Power supply pin AF2 23 GNDRX2 24 GNDRX1 25 IFIN1 Comparator input pin 10 kΩ 22 10 kΩ 22 1 MΩ 21 Pin Name 100 kΩ Pin No. 360 Ω 2.9 kΩ Ground pin 25 26 IFIN2 27 GNDRF3 Ground pin 28 MIXOUT1 Mixer output pin 29 MIXFIL Mixer filter pin 30 VCCRF1 Power supply pin 360 Ω IF amplifier input pin 26 450 Ω 2 kΩ 28 29 4 kΩ 2 kΩ 31 RFIN 3 kΩ 31 RF signal input pin 50 µA 4 Dec./5th/2002 TB32301AFL Pin No. Pin Name 32 GNDRF1 33 GNDRF2 34 Function Equivalent Circuit Ground pin TXOUT RF signal output pin 35 VCCRF2 Power supply pin 36 VCCRF3 Power supply pin Note: The equivalent circuit diagrams above are intended as an aid for designing external circuits. They do not show the exact layout of the internal circuits. 5 Dec./5th/2002 TB32301AFL Power Supply Power Supply Name Pin No. Ground Relevant Pin Name Pin No. Block Name VCCSyn3 1 GND Syn3 5 VCO Doubler VCCSyn2 2 GND Syn2 2 VCO1 VCCSyn1 9 GND Syn1 6 PLL, DATA SET VCCRX2 16 GND RX3 23 Tuning (FLL), RX-AMP, RX-LPF, DATA COMP, FM-DET VCCRX1 21 GND RX2 24 TX-FILTER, PA, RSSI, IF-AMP, (IF-BPF) VCCRFRX 30 GND RF1 GND RF2 32 33 LNA VCCRX TX 35 GND RX1 GND RF1 GND RF2 27 32 33 PA VCCRF 36 GND RX1 GND RF1 GND RF2 27 32 33 PA, MIXER, LNA Supplementary: Pins as shown below are shorted together. (1) VCC RX TX (35 pin) − VCC Syn2 (2 pin) (2) VCC RF (36 pin) − VCC RFRX (30 pin) 6 Dec./5th/2002 TB32301AFL Functions and Operation 1. Serial data input timing chart • Data to control the TB32301AFL is serially applied to pins CLK, DATA and STB. • Data is loaded into shift registers with MSB first on the rising edge of the clock and latched on the rising edge of the STB signal. When the STB pin is high, the data stored in the shift register is retained even if clock is applied. When the STB pin is low, the data can be rewritten. • Input timings of the CLK, DATA and STB are shown below. > = 0.05 µs > = 0.02 µs CLK > = 0.02 µs DATA > = 0.01 µs > = 0.02 µs > = 0.02 µs STB > = 0.1 µs 2. Serial data control contents The TB32301F has five types of control contents. These types are determined by serial input 5-bit register address (group code). The control contents consist of PLL main counter setting, PLL reference counter setting, auto-tuning reference counter setting, transmit power amplifier gain setting and system control setting. These settings are controlled independently one another. 2.1 Register address setting table (group code) GC4 GC3 GC2 GC1 GC0 0 0 0 0 0 PLL main counter setting 0 0 0 0 1 PLL reference counter setting 0 0 0 1 0 Auto-tuning reference counter setting 2.2 Control Contents 0 0 0 1 1 Transmit power amplifier gain setting 0 0 1 0 0 System control register setting PLL main counter setting • The PLL main counter employs a swallow counter. • It consists of 6-bit swallow counter, 9-bit programmable counter and 1/64, 1/65 2-modulus prescaler. • The divide factor can be set in the range 4032 to 32767 by sending any data to the swallow counter and the programmable counter. MSB 1 0 1 0 0 0 0 0 Group code 0 N8 N7 N6 N5 N4 N3 N2 N1 N0 A5 A4 A3 A2 A1 A0 Programmable counter: N 0 Swallow counter: A A = A0 + A1 × 21 + A2 × 22 + --------- + A5 × 25 N = N0 + N1 × 21 + N2 × 22 + -------- + N8 × 28 (Divide factor) = 64N + A 4032 < = (Divide factor) < = 32767 7 Dec./5th/2002 TB32301AFL 2.3 PLL reference counter setting • The PLL reference counter generates phase comparison frequency0. • It consists of 9-bit reference counter. The divide factor can be set in the range 4 to 511 by sending any data to the reference counter. MSB 1 0 1 0 0 0 0 0 1 R8 R7 R6 R5 R4 R3 R2 R1 R0 Group code 0 0 0 0 0 0 0 Auto-tuning counter: F R = R0 + R1 × 21 + R2 × 22 + --------- + R8 × 28 (Divide factor) = R 4< = (Divide factor) < = 511 2.4 Auto-tuning reference counter setting • The TB32301AFL has an automatic tuning system to correct the fluctuation of center frequency in FM detector, which is caused by, for example, temperature change. To generate a reference clock to correct the fluctuation, set the divide factor of auto-tuning reference counter to the value to obtain 200-kHz frequency, according to external reference clock frequency. • The auto-tuning reference counter consists of 8 bits. • The divide factor can be set in the range 6 to 255 by sending any data to the reference counter. F = F0 + F1 × 21 + F2 × 22 + --------- + F7 × 27 (Divide factor) = F 6< = (Divide factor) < = 255 MSB 1 0 1 0 0 0 0 1 Group code Note 0 F7 F6 F5 F4 F3 F2 F1 Auto-tuning counter: F F0 0 0 0 0 0 0 0 0 Internal control bits (always 0) (Note) Internal control bits are used to control the PLL. Please clear the bits. Otherwise, the PLL may not operate properly. 8 Dec./5th/2002 TB32301AFL 2.5 Transmit power amplifier setting Applying data serially to pins CLK, DATA and STB changes the gain of the transmit power amplifier. The power control counter consists of 5 bits. MSB 1 0 1 0 0 0 0 1 Group code 1 P4 P3 P2 P1 P0 0 0 0 0 0 0 0 0 0 0 0 Power control counter: P (Control step number) = P0 + P1 × 21 + P2 × 22 + --------- + P4 × 24 9 Dec./5th/2002 TB32301AFL 2.6 System control register setting In the system control register, applying data serially to pins CLK, DATA and STB sets the optional functions as described below. MSB 1 0 1 0 0 0 1 0 0 Group code CP CP 2 1 0 MO PD PD PD (M1) (M2) (M3) (M4) 0 D 3 2 1 0 0 0 0 Charge Transmit Battery-saving Transmit modulation pump current modulation (power-down) control setting control control 0 (Note) 0 DC DC 2 1 Comparator control Note: Please clear the bits. • PLL charge pump current setting (CP1 and CP2 bits: 2.4 GHz) The TB32301AFL contains a constant current charge pump circuit. The output current of the circuit can be selected by setting the CP1 and CP2 bits. CP2 CP1 Charge Pump Current 0 0 4 mA 0 1 2 mA 1 0 1 mA • Transmit data timing setting (MOD bit) Clearing the MOD bit makes the VCO circuit oscillate at the center frequency, which is controlled by the PLL. The circuit is not controlled by received data. MOD Transmit Data Timing 0 Modulator OFF 1 Modulator ON • Battery-saving (power-down) mode setting (PD1, PD2 and PD3 bits) Setting the PD1, PD2 and PD3 bits controls the circuits in the reception and transmission blocks. The settings of the external BS control pin (14 pin) and the control bits are shown in the table below. BS Control Bits Reception Block FM-DET RX-LPF Transmission Block Common Block PA TX-LPF PLL, VCO Auto tuning PD3 PD2 PD1 LNA MIX IF-AMP L * * * OFF OFF OFF OFF OFF OFF OFF OFF OFF H 1 1 1 OFF OFF OFF OFF OFF OFF OFF OFF OFF H 1 0 0 OFF OFF OFF OFF OFF OFF OFF ON ON H 1 0 1 OFF OFF OFF OFF OFF ON ON ON ON H 0 0 1 OFF OFF OFF OFF OFF OFF ON ON ON H 0 0 0 ON ON ON ON ON OFF OFF ON ON H 0 1 1 OFF OFF OFF OFF OFF OFF OFF OFF ON • Transmit modulation control bits (M1 to M4 bits) M1 to M4 bits are cleared for normal operation, however, M2 to M4 bits can be set to high to control the transmit modulation as shown below. M1 M2 M3 M4 Transmit Modulation 0 0 0 0 Normal modulation 0 1 1 1 Normal modulation × 16/8 10 Dec./5th/2002 TB32301AFL • Rise time constant setting of comparator reference level (D1 and D2 bits) The rise time constant of data comparator reference level is determined by an external capacitance and an internal resistance. The internal resistance can be selected by applying data serially to pins CLK, DATA and STB. (Rise time constant) = (External capacitance: C) × (Internal resistance: R) DC2 DC1 Internal Resistance: R 0 0 10 kΩ 0 1 10 kΩ 1 0 100 kΩ 1 1 1000 kΩ 3. Image canceller mixer in reception block The TB32301AFL contains an image canceller mixer as the first stage of the reception block. The image canceller mixer is designed for upper local, therefore, please set the local signal frequency to f0 (desired reception frequency) + 11 MHz (IF frequency). 4. Lock detector function (LD pin: 7 pin) The TB32301AFL incorporates VCO lock detector function. When a phase error is detected in the phase comparator, 0 is driven out from the LD pin. When the VCO is locked or all the circuits are OFF, 1 is driven out from the pin. 5. VCO modulation polarity and demodulation data polarity • VCO modulation polarity Transmit Data VCO Frequency Deviation 1 Positive (+) polarity 0 Negative (−) polarity • Demodulation data polarity The polarity of the data, which is demodulated by the FM detector and the data comparator, is the same as that of transmit data. At Transmission At Reception Transmit Data FM Detector Data Comparator Output 1 Positive (+) polarity 1 0 Negative (−) polarity 0 11 Dec./5th/2002 TB32301AFL Electrical Characteristics Maximum Ratings Characteristics Symbol Rating Unit VCC_A, VCC_D 3.6 V Power dissipation PD 530 mW Input pin voltage CLK, DATA, STB, BS, LD,TXIN 3.6 V Tstg −50 to 150 °C Power supply voltage Storage temperature range Note 1: Maximum ratings are a set of specified parameter values which must not be exceeded during operation, even for an instant. Operating Ratings Symbol Test Circuit Operating voltage Vopr1 － Operating temperature Topr1 － Characteristics Test Condition Ta = 25°C, ground reference Rating Unit 2.7 to 3.3 V -20 to 70 °C Note 2: These ratings specify the ranges within which the device can operate its basic functions, even when fluctuations in its electrical characteristics occur. Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VCC = 3.0 V, f = 2450 MHz, Bit Rate = 100kHz, PA bit setting = 21, Dev = ± 160 kHz) Power Supply Symbol Test Circuit Test Condition Min Typ. Max Unit Current consumption 1 at no signal ICC1 1 At reception BS = H, PD1 = 0, PD2 = 0, PD3 = 0 (Note 3) 28.0 35.1 42.0 mA Current consumption 2 at no signal ICC2 1 At transmission BS = H, PD1 = 1, PD2 = 0, PD3 = 1 (Note 3) 19 25.6 42 mA ICCQ1 1 In battery-saving mode BS = L, PD1 = 1, PD2 = 1 PD3 = 1 (Note 3) 0 10 µA High-level input voltage VIH － CLK, DATA, STB, BS, TXIN VCC × 0.8 VCC VCC + 0.2 V Low-level input voltage VIL － CLK, DATA, STB, BS, TXIN −0.2 0 VCC × 0.2 V Min Typ. Max Unit Characteristics Supply current at no signal Note 3: Please refer to Section 2.6 “System control register setting”. Integrated Characteristics Characteristics Minimum input level Demodulation output level Symbol Test Circuit VIN(min) 1 S/N = 20dB - 20.4 − dBµV Vod － Vin (LNA) = 70dBµV − 450 − mVp-p Test Condition 12 Dec./5th/2002 TB32301AFL Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VCC = 3.0 V, f = 2450 MHz, Bit Rate = 100kHz, PA = 21 setting, Dev = ± 160 kHz) LNA and Mixer Blocks IRR 1 20 33 dB Output impedance R-OUT (MIX) － 470 Ω Output capacitance C-OUT (MIX) － 2 pF Operating frequency range (LNA and mixer) Fopr (LNA + MIX) 1 2400 2500 MHz Intercept point 1 output (LNA and mixer) OIP3-1 (LNA + MIX) － f1 (UD1) = 2453 MHz, UD1: No modulation f2 (UD2) = 2456 MHz, UD2: No modulation 85 dBµV Mixer image rejection ratio IF Amplifier, DET and RX-LPF Blocks RSSI output voltage 1 V (RSSI-1) 1 Vin (IF) = 41dBµV, No modulation 0.36 0.54 0.72 V RSSI output voltage 2 V (RSSI-2) 1 Vin (IF) = 91dBµV, No modulation (1.25) (1.75) (2.25) V IF amplifier input impedance R-IN (IF) － 720 Ω IF amplifier input capacitance C-IN (IF) － 2 pF COMP (duty) 1 Open-drain output Internal time constant setting 1 (10 kΩ) 40 50 60 % I (COMP-LEAK) 1 Open-drain output 0 5 µA R (COMP-L) － IL = 100 µA 1 kΩ t-lock 1 Phase comparison frequency: 500 kHz Charge pump output current = 4 mA 150 µs Reference clock operating frequency range fxin 1 4 20 MHz Reference clock input level range vxin 1 92 100 112 dBµV Clock (serial data) input frequency fclk 1 20 MHz Charge pump output current 1 Icp (1) 1 Vcp = 1/2VCC 350 500 650 µA Charge pump output current 2 Icp (2) 1 Vcp = 1/2VCC 0.7 1 1.3 mA Charge pump output current 3 Icp (3) 1 Vcp = 1/2VCC 1.4 2 2.6 mA Charge pump output current 4 Icp (4) 1 Vcp = 1/2VCC 2.8 4 5.2 mA LD-off-LEAK 1 Open-drain output 0 5 µA R(LD-on) 1 Open-drain output 1 kΩ f (VCO) 1 2400 2500 MHz Kv － 120 MHz/V pn1 － @500 kHz 107 dBc/Hz pn2 － @2 MHz 119 dBc/Hz Comparator Duty ratio High-level leakage current Output ON resistance PLL Block Lock-up time LD OFF leakage current LD ON resistance VCO Block VCO Oscillation frequency range (× 2) VCO gain (× 2) VCO phase noise (× 2) 13 Dec./5th/2002 TB32301AFL Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VCC = 3.0 V, f = 2450 MHz, Bit Rate = 100kHz, PA = 21 setting, Dev = ± 160 kHz) Transmission Block Tx data input level VCC × 0.8 VCC VCC + 0.2 Ｖ Test frequency: 1.225 GHz −30 −20 dBm 1 On loop, fBB=100kHz (CW) (140) (190) (230) KHz PA-OUT (nom.) 1 DATA21 set for PA output (−9) (−3) dBm PA-OUT (min.) 1 DATA3 set for PA output (−30) (−25) dBm Z-OUT (PA) 1 50 Ω Vtx － Local leakage spurious SPRlo 1 Maximum frequency deviation dev (tx) Nominal output signal level Minimum output signal level PA Block Output impedance 14 Dec./5th/2002 TB32301AFL Test Circuit 1 ICC1, ICC2, ICCQ VIN (min) VOD A V C211 1000 pF C212 0.1 µF VCC = 3.0 V R201 1 kΩ C201 0.1 µF R281 200 Ω 28 C29A 0.01 µF VCCRFRX 29 MIX OUT 27 R191 10 kΩ C202 300 pF C271 1000 pF BER GND RX1 26 IF-IN2 25 IF-IN1 24 23 GND RX2 22 GND RX3 AF2 21 VCC RX2 20 AF1 19 D-DATA 18 SG fin = 2450 MHz L311 4.7 nH C311 22 pF IF BPF RX LPF FM-DET 30 VCCRFRX 31 RSSI BS 34 ×2 12 PLL1 DATA SET VCO1 35 VCCRFTX LD 6 7 R71 10 kΩ REF CLK 8 VCC Syn1 C91 10 pF 5 GND Syn1 STB 11 CLK 10 DATA R101 100 kΩ R101 100 kΩ R101 100 kΩ R101 100 kΩ 9 C92 100 pF 4 GND Syn3 C81 100 pF 3 GND Syn2 C32 R31 10 nF 2.7 kΩ 2 LOOP FIL1 C31 4.3 nF VCC Syn2 C21 10 pF 36 VCCRF VCC Syn3 1 C11 10 pF C361 1000 pF C362 10 pF 13 TXIN TXOUT 4.7 nH C341 10 pF C352 1000 pF C351 10 pF TX LPF 33 GNDRF2 C22 100 pF L341 C12 100 pF C342 10 pF PA - OUT V C171 0.01 µF 16 C162 1 µF C15A C161 0.01 µF 15 0.01 µF FLLC2 R71 10 kΩ 14 VCC RX3 Tuning (FLL) RF IN V 17 FLLC1 32 GNDRF1 C343 1000 pF C181 1000 pF RSSI MIX FL C302 1000 pF C301 10 pF V (RSSI-1) V (RSSI-2) SG fin = 13 MHz, 100 mVrms (1) Detailed test condition of minimum input level in the integrated characteristics • Detector LPF: C202 = 300 pF, R201 = 1 kΩ and fT = 530 kHz • Total bits: 1.6 Mbits • Data comparator output: Monitors using a probe. • Input/output: LNA input, data comparator output • Transmission modulation (DEV): 157.5 kHz • Data: PRBS9 (1MBPS) • BT = 0.5 gaussian filter • IF filter used. (Note) • Tested using a Toshiba’s mounting board Note: Ceramic filter manufacturer and product no. SFSCB11M0WF manufactured by Murata Manufacturing Co., Ltd. (2) Detailed test condition in the transmission block • Tested using a Toshiba’s mounting board (3) Detailed test condition of output level in the PA block • Tested using a Toshiba’s mounting board 15 Dec./5th/2002 TB32301AFL Package Dimensions Weight: 0.08 g (typ.) 16 Dec./5th/2002 TB32301AFL RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 17 Dec./5th/2002