DS25MB100 2.5 Gb/s 1:2 Mux/Buffer with Input Equalization and Output De-Emphasis General Description Features The DS25MB100 is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy or cable driving applications. Signal conditioning features include input equalization and programmable output de-emphasis that enable data communication in FR4 backplane up to 2.5 Gbps. Each input stage has a fixed equalizer to reduce ISI distortion from board traces. All output drivers have four selectable levels of de-emphasis to compensate for transmission losses from long FR4 backplane or cable attenuation reducing deterministic jitter. The de-emphasis levels can be independently controlled for the line-side and switch-side drivers. The internal loopback paths from switch-side input to switch-side output enable at-speed system testing. All receiver inputs and driver outputs are internally terminated with 100Ω differential terminating resistors. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2:1 multiplexer and 1:2 buffer 0.25–2.5 Gbps fully differential data paths Fixed input equalization Programmable output de-emphasis Independent de-emphasis controls Programmable loopback modes On-chip terminations HBM ESD rating 5.5 kV on all pins +3.3V supply Low power, 0.45 W typical Lead-less LLP-36 package −40°C to +85°C operating temperature range Applications ■ ■ ■ ■ ■ Backplane driver or cable driver Redundancy and signal conditioning applications PCI Express Serial ATA CPRI/OBSAI Functional Block Diagram 20208901 © 2007 National Semiconductor Corporation 202089 www.national.com DS25MB100 2.5 Gb/s 1:2 Mux/Buffer with Input Equalization and Output De-Emphasis March 2007 DS25MB100 Simplified Block Diagram 20208902 www.national.com 2 DS25MB100 Connection Diagram 20208903 Order Number DS25MB100TSQ See NS Package Number SQA36A 3 www.national.com DS25MB100 Pin Descriptions Pin Name Pin Number I/O Description LINE SIDE HIGH SPEED DIFFERENTIAL IO's IN+ IN− 33 34 I Inverting and non-inverting differential inputs at the line side. IN+ and IN− have an internal 50Ω connected to an internal reference voltage. OUT+ OUT− 30 31 O Inverting and non-inverting differential outputs at the line side. OUT+ and OUT− have an internal 50Ω connected to VCC. SWITCH SIDE HIGH SPEED DIFFERENTIAL IO's OUT0+ OUT0− 3 4 O Inverting and non-inverting differential outputs of mux0 at the switch side. OUT0+ and OUT0− have an internal 50Ω connected to VCC. OUT1+ OUT1− 22 21 O Inverting and non-inverting differential outputs of mux1 at the switch side. OUT1+ and OUT1− have an internal 50Ω connected to VCC. IN0+ IN0− 6 7 I Inverting and non-inverting differential inputs to the mux at the switch side. IN0+ and IN0− have an internal 50Ω connected to an internal reference voltage. IN1+ IN1− 25 24 I Inverting and non-inverting differential inputs to the mux at the switch side. IN1+ and IN1− have an internal 50Ω connected to an internal reference voltage. CONTROL (3.3V LVCMOS) MUX 19 I A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default state for mux_0 is switch A. EQL 11 I A logic low enables the EQ. EQL is internally pulled high. Default is with EQ disabled. EQS 36 I A logic low enables the EQ. EQS is internally pulled high. Default is with EQ disabled. DEL_0 DEL_1 18 27 I DEL_0 and DEL_1 select the output de-emphasis of the line side drivers (OUT±). DEL_0 and DEL_1 are internally pulled high. DES_0 DES_1 10 1 I DES_0 and DES_1 select the output de-emphasis of the switch side drivers (OUT0±, OUT1±). DES_0 and DES_1 are internally pulled high. LB0 28 LB1 26 I A logic low at LB1 enables the internal loopback path from IN1± to OUT1±. LB1 is internally pulled high. RSV 17 I Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND through an external pull-down resistor. 5, 13, 15, 23, 32 P VCC = 3.3V ± 5%. The maximum current consumption under worst voltage, temperature, and process variation conditions does not exceed 170mA. Each VCC pin should be connected to the VCC plane through a low inductance path, typically with a via located as close as possible to the landing pad of the VCC pin. A logic low at LB0 enables the internal loopback path from IN0± to OUT0±. LB0 is internally pulled high. POWER VCC It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin to ground plane. GND 2, 8, 9, 12, 14, 16, 20, 29, 35 P Ground reference. Each ground pin should be connected to the ground plane through a low inductance path, typically with a via located as close as possible to the landing pad of the GND pin. GND DAP P DAP is the metal contact at the bottom side, located at the center of the LLP package. It should be connected to the GND plane with at least 16 via to lower the ground impedance and improve the thermal performance of the package. Note: I=Input, O=Output, P=Power www.national.com 4 The DS25MB100 is a signal conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy up to 2.5 Gbps. Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB of transmission loss from a short backplane trace (about 10 inches backplane). The output driver has de-emphasis (driver-side equalization) to compensate the transmission loss of the backplane that it is driving. The driver conditions the output signal such that the lower frequency and higher frequency pulses reach approximately the same amplitude at the end of the backplane, and minimize the deterministic jitter caused by the amplitude disparity. The DS25MB100 provides four steps of user-selectable de-emphasis ranging from 0, -3, -6 and –9 dB to handle different lengths of backplane. Figure 1 shows a driver de-emphasis waveform. The de-emphasis duration is 188ps nominal, corresponds to 0.47 bit-width at 2.5 Gbps. The deemphasis levels of switch-side and line-side can be individually programmed. The high speed inputs are self-biased to about 1.3V and are designed for AC coupling. The inputs are compatible to most TABLE 1. Logic Table For Multiplex Controls MUX_S0 Mux Function 0 MUX select switch input, IN1±. 1 (default) MUX select switch input, IN0±. TABLE 2. Logic Table For Loopback Controls LB0 Loopback Function 0 Enable loopback from IN0± to OUT0±. 1 Normal mode. Loopback disabled. (default) LB1 Loopback Function 0 Enable loopback from IN1± to OUT1±. 1 Normal mode. Loopback disabled. (default) TABLE 3. Line-Side De-Emphasis Controls De-Emphasis Level in mVPP (VODB) DEL_[1:0] De-Emphasis Level in mVPP (VODPE) De-Emphasis in dB (VODPE/VODB) Typical FR4 Board Trace 00 1300 1300 0 10 inches 01 1300 920 −3 20 inches 10 1300 650 −6 30 inches 1 1 (default) 1300 461 −9 40 inches TABLE 4. Switch-Side De-Emphasis Controls De-Emphasis Level in mVPP (VODB) DES_[1:0] De-Emphasis Level in mVPP (VODPE) De-Emphasis in dB (VODPE/VODB) Typical FR4 Board Trace 00 1300 1300 0 10 inches 01 1300 920 −3 20 inches 10 1300 650 −6 30 inches 1 1 (default) 1300 461 −9 40 inches TABLE 5. EQ Controls For Line And Switch Sides EQL/EQS Loopback Function 0 Enable equalization. 1 (default) Normal mode. Equalization disabled. 5 www.national.com DS25MB100 AC coupling differential signals such as LVDS, LVPECL and CML. Functional Description DS25MB100 20208904 FIGURE 1. Driver De-Emphasis Differential Waveform (Showing All 4 De-Emphasis Steps) www.national.com 6 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) CMOS/TTL Input Voltage CML Input/Output Voltage Junction Temperature Storage Temperature Lead Temperature Soldering, 4 seconds −0.3V to 4V −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) +150°C −65°C to +150°C Supply Voltage (VCC-GND) Min Typ Max Units 3.13 3.3 5 3.465 V 100 mVPP 85 °C 100 °C Supply Noise Amplitude 10 Hz to 2 GHz 26.2°C/W Thermal Resistance, θJC-top 6 kV 1.25 kV 350V Recommended Operating Ratings +260°C Thermal Resistance, θJA (Note 8) 11.1°C/W Ambient Temperature 3.3°C/W –40 Case Temperature Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ (Note 2) Max Units 2.0 VCC +0.3 V −0.3 0.8 V 10 µA 124 µA LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage VIL Low Level Input Voltage IIH High Level Input Current VIN = VCC −10 IIL Low Level Input Current VIN = GND 75 RPU Pull-High Resistance 94 35 kΩ RECEIVER SPECIFICATIONS VID Differential Input Voltage AC Coupled Differential Signal Range (Note 9) Below 1.25 Gbps Above 1.25 Gbps This parameter is not tested at production VICM Common Mode Voltage at Measured at receiver inputs reference to ground Receiver Inputs RITD Input Differential Termination (Note 3) RITSE Input Termination (single- On-chip termination IN+ or IN− to GND for frequency end) > 100 MHz On-chip differential termination between IN+ or IN− 100 100 1750 1560 1.3 84 100 mVP-P mVP-P V 116 Ω Ω 50 DRIVER SPECIFICATIONS VODB VDE Output Differential Voltage Swing withoutdDe-Emphasis (Note 4) RL = 100Ω ±1% DES_1=DES_0=0 DEL_1=DEL_0=0 Driver De-emphasis disabled Running K28.7 pattern at 2.5 Gbps See Figure 5 for test circuit. Output De-Emphasis Voltage Ratio 20*log(VDODPE/VODB) RL = 100Ω ±1% Running K28.7 pattern at 2.5 Gbps DEx_[1:0]=00 DEx_[1:0]=01 PREx_[1:0]=10 DEx_[1:0]=11 x=S for switch side de-emphasis control x=L for line side de-emphasis control See Figure 1 on waveform. See Figure 5 for test circuit. 7 1100 1300 1500 mVP-P 0 −3 −6 −9 dB dB dB dB www.national.com DS25MB100 Thermal Resistance, ΦJB ESD Rating (Note 10) HBM, 1.5 kΩ, 100 pF CDM MM Absolute Maximum Ratings (Note 1) DS25MB100 Min Typ (Note 2) Max Units Tested at −9 dB de-emphasis level, DEx[1:0]=11 x=S for switch side de-emphasis control x=L for line side de-emphasis control See Figure 4 on measurement condition. 125 188 250 ps ROTSE Output Termination (Note On-chip termination from OUT+ or OUT− to VCC 3) 42 50 58 Ω ROTD Output Differential Termination On-chip differential termination between OUT+ and OUT− ΔROTSE Mis-Match in Output Termination Resistors Mis-match in output terminations at OUT+ and OUT− VOCM Output Common Mode Voltage Symbol TDE Parameter De-Emphasis Width Conditions Ω 100 5 % 2.7 V 0.45 W 100 ps 100 ps POWER DISSIPATION PD Power Dissipation VDD = 3.3V @ 25°C All outputs terminated by 100Ω ±1%. DEL_[1:0]=0, DES_[1:0]=0 Running PRBS 27-1 pattern at 2.5 Gbps AC CHARACTERISTICS tR Differential Low to High Transition Time tF Differential High to Low Transition Time Measured with a clock-like pattern at 2.5 Gbps, between 20% and 80% of the differential output voltage. de-emphasis disabled Transition time is measured with fixture as shown in Figure 5, adjusted to reflect the transition time at the output pins tPLH Differential Low to High Propagation Delay Measured at 50% differential voltage from input to output tPHL Differential High to Low Propagation Delay tSKP Pulse Skew tSKO tSKPP 1 ns 1 ns |tPHL–tPLH| 20 ps Output Skew (Note 7) Difference in propagation delay between two outputs in the same device 100 ps Part-to-Part Skew Difference in propagation delay between the same output from devices operating under identical conditions 100 ps 6 ns 2 2 2 psrms psrms psrms 35 Pspp 2.5 Gbps tSM Mux Switch Time Measured from VIH or VIL of the mux-control or loopback control to 50% of the valid differential output RJ Device Random Jitter (Note 5) See Figure 5 for test circuit. Alternating-1-0 pattern EQ and de-emphasis disabled. At 0.25 Gbps At 1.25 Gbps At 2.5 Gbps DJ DR 1.8 Device Deterministic Jitter See Figure 5 for test circuit. (Note 6) EQ and de-emphasis disabled Between 0.25 and 2.5 Gbps with PRBS7 pattern for DS25MB100 @ –40°C to 85°C Data Rate (Note 9) Tested with alternating-1-0 pattern 0.25 Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. Note 2: Typical parameters measured at VCC = 3.3V, TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed. Note 3: IN+ and IN− are generic names refer to one of the many pairs of complimentary inputs of the DS25MB100. OUT+ and OUT− are generic names refer to one of the many pairs of the complimentary outputs of the DS25MB100. Differential input voltage VID is defined as |IN+–IN−|. Differential output voltage VOD is defined as |OUT+–OUT−|. www.national.com 8 K28.5 pattern is a 20-bit repeating pattern of +K28.5 and −K28.5 code groups {110000 0101 001111 1010} Note 5: Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt(RJOUT2– RJIN2), where RJOUT is the total random jitter measured at the output of the device in psrms, RJIN is the random jitter of the pattern generator driving the device. Note 6: Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJOUT–DJIN), where DJOUT is the total peak-to-peak deterministic jitter measured at the output of the device in pspp, DJIN is the peak-to-peak deterministic jitter of the pattern generator driving the device. Note 7: tSKO is the magnitude difference in the propagation delays among data paths between switch A and switch B of the same port and similar data paths between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1 ±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to SOB_0±, LI_1± to SOA_1± and LI_1± to SOB_1±. tSKO also refers to the delay skew of the loopback paths of the same port and between similar data paths between port 0 and port 1. An example is the output skew among data paths SIA_0± to SOA_0±, SIB_0± to SOB_0±, SIA_1± to SOA_1± and SIB_1± to SOB_1±. Note 8: Thermal resistances are based on having 16 thermal relief vias on the DAP pad under the 0 airflow condition. Note 9: This parameter is guaranteed by design and/or characterization. It is not tested in production. Note 10: ESD tests conform to the following standards: Human Body Model applicable standard: MIL-STD-883, Method 3015.7 Machine Model applicable standard: JESD22-A115-A (ESD MM standard of JEDEC) Field-induced Charge Device Model: Applicable standard JESD22-C101-C (ESD FICDM standard of JEDEC) 9 www.national.com DS25MB100 Note 4: K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000} DS25MB100 Timing Diagrams 20208905 FIGURE 2. Driver Output Transition Time 20208906 FIGURE 3. Propagation Delay from Input to Output 20208907 FIGURE 4. Test Condition for Output Pre-Emphasis Duration www.national.com 10 DS25MB100 20208908 FIGURE 5. AC Test Circuit 11 www.national.com DS25MB100 Application Information 20208909 FIGURE 6. Application Diagram www.national.com 12 DS25MB100 20208910 FIGURE 7. Chassis Based Network Switch System With Redundancy 13 www.national.com DS25MB100 Physical Dimensions inches (millimeters) unless otherwise noted LLP-36 Package Order Number DS25MB100TSQ NS Package Number SQA36A www.national.com 14 DS25MB100 Notes 15 www.national.com DS25MB100 2.5 Gb/s 1:2 Mux/Buffer with Input Equalization and Output De-Emphasis Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. 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