DS100MB201
DS100MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization
Literature Number: SNLS333
DS100MB201
Dual Lane 2:1/1:2 Mux/Buffer with Equalization
General Description
Features
The DS100MB201 is a dual lane 2:1 multiplexer and 1:2
switch or fan-out buffer with signal conditioning suitable for
10GE, Fibre Channel, Infiniband, SATA/SAS and other highspeed bus applications up to 10.31215 Gbps. The device
performs receive equalization allowing maximum flexibility of
physical placement within a system. The receiver's continuous time linear equalizer (CTLE) provides a boost to compensate for 10” of 4 mil FR4 stripline at 10.3125 Gbps. The
DS100MB201 is capable of opening an input eye that is completely closed due to inter-symbol interference (ISI) induced
by the interconnect medium. The transmitter features a programmable amplitude voltage levels to be selected from 600
mVp-p to 800 mVp-p. The signal conditioning settings are
programmable with register control.
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With a typical power consumption of 100 mW/channel at
10.3125 Gbps, and SMBus register control to turn-off unused
lanes, the DS100MB201 is part of National's PowerWise family of energy efficient devices.
Applications
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Up to 10.3125 Gbps
Dual Lane 2:1 mux, 1.2 switch or fanout
Adjustable transmit Differential Output Voltage (VOD)
<0.3 UI of residual DJ at 10.3125 Gbps with 10” FR4 trace
Adjustable electrical IDLE detect threshold
Signal conditioning programmable through SMBus I/F
Single 2.5V supply operation
>6 kV HBM ESD Rating
3.3V tolerant SMBus interface
High speed signal flow–thru pinout
Package: 54-pin LLP (10 mm x 5.5 mm)
XAUI (3.125 Gbps), RXAUI (6.25 Gbps)
sRIO – Serial Rapid I/O
Fibre Channel (8.5 Gbps)
10GBase-CX4, InfiniBand (QDR, SDR & DDR)
FR4 backplane traces
Typical Application
30131405
© 2011 National Semiconductor Corporation
301314
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DS100MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization
April 14, 2011
DS100MB201
Pin Diagram
30131401
DS100MB201 Pin Diagram 54L LLP
Ordering Information
NSID
Qty
Spec
Package
DS100MB201SQ
Tape & Reel Supplied As 2,000 Units
NOPB
SQA54A
DS100MB201SQE
Tape & Reel Supplied As 250 Units
NOPB
SQA54A
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2
Pin Name
Pin Number
I/O, Type
Pin Description
Differential High Speed I/O's
SIA0+, SIA0-,
SIA1+, SIA1-
45, 44,
40, 39
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated
on-chip 50Ω termination resistor connects SIA_n+ to VDD and SIA_n- to VDD
when enabled.
SOA0+, SOA0-,
SOA1+, SOA1-
35, 34,
31, 30
O
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
SIB0+, SIB0-,
SIB1+, SIB1-
43, 42,
38, 37
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated
on-chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
SOB0+, SOB0-,
SOB1+, SOB1-
33, 32,
29, 28
O
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
DIN0+, DIN0-,
DIN1+, DIN1-
10, 11,
15, 16
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated
on-chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
O
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
DOUT0+, DOUT0-, 3, 4,
DOUT1+, DOUT1- 7, 8
Control Pins — (LVCMOS)
ENSMB
48
I, LVCMOS w/ System Management Bus (SMBus) enable pin.
internal pull- LOW = Reserved
down
HIGH = Register Access: Provides access to internal digital registers to
control such functions as equalization, VOD, channel powerdown, and idle
detection threshold.
Please refer to System Management Bus (SMBus) and Configuration
Registers for detailed information.
SDA
49
I, LVCMOS
The SMBus bi-directional SDA pin. Data input or open drain output. External
pull-up resistor is required. Refer to Rterm in the SMBus specification.
SCL
50
I, LVCMOS
SMBUS clock input pin. External pull-up resistor maybe needed. Refer to
Rterm in the SMBus specification.
AD[3:0]
46, 47, 53, 54 I, LVCMOS w/ SMBus Slave Address Inputs. These pins set the SMBus address.
internal pulldown
3
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DS100MB201
Pin Descriptions
DS100MB201
Pin Name
Pin Number
I/O, Type
Pin Description
Control Pins — (LVCMOS)
RATE
21
I, Float,
LVCMOS
LOW = Reserved
HIGH = 10.3125 Gbps operation
TXIDLEDO
24
I, Float,
LVCMOS
TXIDLEDO, 3–level input controls the driver output.
LOW = disable the signal detect/squelch function for DOUT.
FLOAT = enable the signal auto detect/squelch function for DOUT and the
signal detect voltage threshold level can be adjusted using the SD_TH pin.
HIGH = force the DOUT to be muted (electrical idle). See Table 1
TXIDLESO
25
I, Float,
LVCMOS
TXIDLESO, 3–level input controls the driver output.
LOW = disable the signal detect/squelch function for SOUT.
FLOAT = enable the signal auto detect/squelch function for SOUT and the
signal detect voltage threshold level can be adjusted using the SD_TH pin.
HIGH = force the SOUT to be muted (electrical idle). See Table 1
FANOUT
26
I, LVCMOS w/ LOW = disable one of the outputs depending on the SEL0, SEL1 pin.
internal pull- HIGH = enable both A/B outputs for broadcast mode.
down
FANOUT = 0 See Table 3
SEL0, SEL1
19, 20
I, LVCMOS w/ SEL0 is for lane 0, SEL1 is for lane 1
internal pull- SEL0, SEL1 = 0 selects B input and B output.
down
SEL0, SEL1 = 1 selects A input and A output. See Table 3
Reserved
52
I, LVCMOS
Tie to GND
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for default
130 mVp-p (differential).
See Table 2
VDD
9, 14, 36, 41,
51
Power
2.5V Power supply pins.
GND
DAP
Power
DAP is the large metal contact at the bottom side, located at the center of the
54 pin LLP package. It should be connected to the GND plane with at least 4
via to lower the ground impedance and improve the thermal performance of
the package.
Reserved
1, 2, 5, 6, 12,
13, 17, 18, 22,
23
Analog
SD_TH
Power
No Connect — Leave pin open
1 = HIGH, 0 = LOW, FLOAT = 3rd input state.
FLOAT condition; Do not drive pin; pin is internally biased to mid level with 50 kΩ pull-up/pull-down.
Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
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4
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
LVCMOS Input/Output Voltage
Differential Input Voltage
Differential Output Voltage
Analog (SD_TH)
Junction Temperature
Storage Temperature
Supply Voltage
VDD to GND
Ambient Temperature
(Note 4)
LVCMOS
SMBus (SDA, SCL)
CML Differential Input
Voltage
Supply Noise Tolerance
up to 50 MHz, (Note 5)
-0.5V to +3.0V
-0.5V to +4.0V
-0.5V to (VDD+0.5V)
-0.5V to (VDD+0.5V)
-0.5V to (VDD+0.5V)
+105°C
-40°C to +125°C
Maximum Package Power Dissipation at 25°C
SQA54A Package
4.21 W
Derate SQA54A Package
52.6mW/°C above +25°C
ESD Rating
HBM, STD - JESD22-A114C
≥±6 kV
MM, STD - JESD22-A115-A
CDM, STD - JESD22-C101-C
Min
Typ
Max
Units
2.375
-40
2.5
25
2.625
+85
V
°C
2.625
3.6
2.0
V
V
Vp-p
0
0
0
100
mVP-P
For soldering specifications: see product folder at
www.national.com www.national.com/ms/MS/MSSOLDERING. pdf
≥±250 V
≥±1250 V
Thermal Resistance
θJC
11.5°C/W
θJA, No Airflow, 4 layer JEDEC
19.1°C/W
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified. (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
900
1000
mW
11
mW
POWER
PD
Power Dissipation
2.5V Operation
EQx = 0,
K28.5 pattern,
VOD = 700 mV p-p
Channel powerdown (Note 7)
LVCMOS / LVTTL DC SPECIFICATIONS
VIH
High Level Input
Voltage
2.0
2.75
V
VIL
Low Level Input
Voltage
0
0.8
V
IIH
Input High Current
VIN = 2.5 V
-15
+15
μA
IIL
Input Low Current
VIN = 0V
-15
+15
μA
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLRX-DIFF
RLRX-CM
Rx Differential Return
Loss (SDD11),
(Note 2)
150 MHz – 1.5 GHz
-20
150 MHz – 3.0 GHz
-13.5
150 MHz – 6.0 GHz
-8
Rx Common Mode
Input Return Loss
(SCC11)
150 MHz – 3.0 GHz, (Note 2)
RRX-IB
Rx Impedance Balance 150 MHz – 3.0 GHz, (Note 2)
(SCL11)
IIN
Maximum current
allowed at IN+ or INinput pin.
RIN
Input Resistance
-10
dB
-27
dB
−30
Single ended to VDD, (Note 2)
5
dB
+30
50
mA
Ω
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DS100MB201
Absolute Maximum Ratings (Note 1)
DS100MB201
Symbol
RITD
Parameter
Conditions
Input Differential
Impedance between
IN+ and IN-
(Note 2)
RITIB
Input Differential
Impedance Imbalance
(Note 2)
RICM
Input Common Mode
Impedance
(Note 2)
VRX-DIFF
Differential Rx peak to
peak voltage
DC voltage,
SD_TH = 20 kΩ to GND
VRX-SD_TH
Electrical Idle detect
threshold (differential)
SD_TH = Float, (Note 8), Figure 5
Min
Typ
Max
Units
85
100
115
Ω
5
Ω
40
Ω
0.1
1.2
V
40
175
mVp-p
700
mVP-P
20
25
DIFFERENTIAL OUTPUTS (OUT_n+, OUT_n-)
VOD
VOCM
TTX-RF
Output Differential
Voltage Swing
RL = 50 Ω ±1% to GND (AC
coupled with 10 nF), 6.4 Gbps,
(Note 6)
VOD1–0 = 00
500
Output Common-Mode Single-ended measurement DCVoltage
Coupled with 50Ω termination,
(Note 2)
600
VDD – 1.4
V
Transmitter Rise/ Fall
Time
20% to 80% of differential output
voltage, measured within 1” from
output pins, (Note 2, Note 6),
Figure 1
TRF-DELTA
Tx rise/fall mismatch
20% to 80% of differential output
voltage, (Note 2, Note 6)
RLTX-DIFF
Tx Differential Return
Loss (SDD22),
(Note 2)
Repeating 1100b (D24.3) pattern,
VOD = 0.8 Vp-p,
150 MHz – 1.5 GHz
-11
1.5 GHz – 3.0 GHz
-10
3 GHz – 6.0 GHz
-5
Repeating 1100b (D24.3) pattern,
VOD = 0.8 Vp-p, (Note 2)
50 MHz – 3.0 GHz
-10
dB
Tx Impedance Balance Repeating 1100b (D24.3) pattern,
(SCL22)
VOD = 0.8 Vp-p, (Note 2)
50 MHz – 3.0 GHz
-30
dB
RLTX-CM
RTX-IB
Tx Common Mode
Return Loss
(SCC22)
ITX-SHORT
Tx Output Short Circuit
Current Limit
ROTD
Output Differential
Impedance between
OUT+ and OUT-
(Note 2)
ROTIB
Output Differential
Impedance Imbalance
(Note 2)
ROCM
Output Common Mode (Note 2)
Impedance
VTX-CM-DELTA
Common Mode
Voltage Delta between
active burst and
electrical Idle of an
OOB signal
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65
20
6
ps
0.1
UI
dB
85
Minimum Temperature for OOB
signal pass-through is -10C.
VIN = 800 mVp-p, at 3 Gbps,
(Note 9)
85
100
25
90
mA
125
Ω
5
Ω
35
Ω
±40
mV
TPD
Parameter
Conditions
Min
Typ
Max
Units
Differential
Propagation Delay
(Low to High and High
to Low Edge
Propagation delay measure at
midpoint crossing between input to
output
150
200
250
ps
120
170
EQx[1:0] = 11Figure 2
220
ps
TLSK
Lane to Lane Skew in a VDD = 2.5V, TA = 25°C
Single Part
EQz[1:0] = OFF
27
ps
TPPSK
Part to Part
Propagation Delay
Skew
VDD = 2.5V, TA = 25°C
35
ps
Switch/Mux Time
Time to switch/mux between A and
B input/output signals
150
ns
TSM
EQUALIZATION
DJ1
DJ2
RJ
Residual Deterministic Tx Launch Amplitude = 0.8 to
Jitter at 8.5 Gbps
1.2 Vp–p, 10” 4–mil FR4 trace,
VOD = 0.8 Vp-p, K28.5, SD_TH =
float
0.1
0.25
UIP-P
Residual Deterministic Tx Launch Amplitude = 0.8 to
Jitter at 10.3125 Gbps 1.2 Vp–p, 10” 4–mil FR4 trace,
VOD = 0.8 Vp-p, K28.5, SD_TH =
float
0.1
0.3
UIP-P
Random Jitter
Tx Launch Amplitude = 1.2 Vp–p,
Repeating 1100b (D24.3) pattern
0.5
psrms
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: OOB signal pass-through limited to a minimum ambient temperature of -10°C.
Note 5: Allowed supply noise (mVP-P sine wave) under typical conditions.
Note 6: Measured with clock-like {11111 00000} pattern.
Note 7: Measured with ENSMB = 1, all channels disabled using SMBus registers 0x01 and 0x02, and EQ in bypass (Default).
Note 8: Measured at package pins of receiver. Less than 65 mVp-p is IDLE, greater than 175 mVp-p is ACTIVE. SD_TH pin connected with resistor to GND
overrides this default setting.
Note 9: Common-mode voltage (VCM) is expressed mathematically as the average of the two signal voltages with respect to local ground.
VCM = (A + B) / 2, A = OUT+, B = OUT-.
7
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DS100MB201
Symbol
DS100MB201
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
3.6
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SCL
RTERM
External Termination Resistance VDD3.3,
pull to VDD = 2.5V ± 5% OR 3.3V ± (Note 10, Note 11, Note 12)
10%
VDD2.5,
(Note 10, Note 11, Note 12)
2.1
(Note 10)
4
mA
2.375
3.6
V
-200
+200
µA
-15
(Note 10, Note 11)
µA
10
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 4
FSMB
Bus Operating Frequency
TBUF
Bus Free Time Between Stop and
Start Condition
(Note 13)
10
4.7
µs
THD:STA
Hold time after (Repeated) Start
At IPULLUP, Max
Condition. After this period, the first
clock is generated.
4.0
µs
TSU:STA
Repeated Start Condition Setup
Time
4.7
µs
TSU:STO
Stop Condition Setup Time
4.0
µs
THD:DAT
Data Hold Time
300
ns
TSU:DAT
Data Setup Time
250
TTIMEOUT
Detect Clock Low Timeout
TLOW
Clock Low Period
THIGH
Clock High Period
(Note 13)
TLOW:SEXT
Cumulative Clock Low Extend
Time (Slave Device)
(Note 13)
tF
Clock/Data Fall Time
tR
Clock/Data Rise Time
tPOR
Time in which a device must be
operational after power-on reset
(Note 13)
(Note 13)
25
100
ns
35
4.7
4.0
kHz
ms
µs
50
µs
2
ms
(Note 13)
300
ns
(Note 13)
1000
ns
500
ms
Note 10: Recommended value. Parameter not tested in production.
Note 11: Recommended maximum capacitance load per bus segment is 400pF.
Note 12: Maximum termination voltage should be identical to the device supply voltage.
Note 13: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
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8
DS100MB201
Timing Diagrams
30131402
FIGURE 1. Output Transition Times
30131403
FIGURE 2. Propagation Delay Timing Diagram
30131404
FIGURE 3. Idle Timing Diagram
30131407
FIGURE 4. SMBus Timing Parameters
9
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DS100MB201
Functional Description
Pin Control Mode
The DS100MB201 is a 2–lane signal conditioning 2:1 multiplexer and 1:2 switch or fan-out buffer optimized for PCB FR4
trace up to 10.3125 Gbps data rate. The DS100MB201 has
direct register access through the SMBus. The ENSMB pin
must be tied high to enable proper operation of the
DS100MB201.
The RATE pin must be forced HIGH to enable 10.3125 Gbps
operation. The receiver electrical idle detect threshold is also
programmable via an optional external resistor on the SD_TH
pin.
SMBUS Register Programming
In SMBus mode the VOD amplitude level and equalization are
all programmable on a individual lane basis. On power-up and
when ENSMB is driven low all registers are reset to their default state.
TABLE 1. Idle Control (3–Level Input)
TXIDLEDO/SO
Function
0
This state is for lossy media, dedicated Idle threshold detect circuit disabled, output follows input based
on EQ settings. Idle state not guaranteed.
Float
Float enables automatic idle detection. Idle on the input is passed to the output. Internal 50KΩ resistors
hold TXIDLEDO/SO pin at a mid level - don't connect this pin if the automatic idle detect function is desired.
This is the default state. Output in Idle if differential input signal less than value set by SD_TH pin.
1
Manual override, output in electrical Idle. Differential inputs are ignored.
TABLE 2. Receiver Electrical Idle Detect Threshold Adjust
SD_TH resistor value (Ω)
Receiver Electrical Idle Detect Threshold (DIFF p-p)
Float (no resistor required)
130 mV (default condition)
0
225 mV
80k
20 mV
SD_TH resistor value can be set from 0 through 80k ohms to achieve desired idle detect threshold, see Figure 5
30131406
FIGURE 5. Typical Idle Threshold vs. SD_TH resistor value
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10
The lanes of the DS100MB201 can be configured either as a
2:1 multiplexer, 1:2 switch or fan-out buffer. The controller
TABLE 3. Logic Table of Switch and Mux Control
FANOUT
SEL0
SEL1
0
0
0
Function — connection path
DOUT0 connects to SIB0.
DOUT1 connects to SIB1.
DIN0 connects to SOB0. SOA0 is in idle (output muted).
DIN1 connects to SOB1. SOA1 is in idle (output muted).
0
0
1
DOUT0 connects to SIB0.
DOUT1 connects to SIA1.
DIN0 connects to SOB0. SOA0 is in idle (output muted).
DIN1 connects to SOA1. SOB1 is in idle (output muted).
0
1
0
DOUT0 connects to SIA0.
DOUT1 connects to SIB1.
DIN0 connects to SOA0. SOB0 is in idle (output muted).
DIN1 connects to SOB1. SOA1 is in idle (output muted).
0
1
1
DOUT0 connects to SIA0.
DOUT1 connects to SIA1.
DIN0 connects to SOA0. SOB0 is in idle (output muted).
DIN1 connects to SOA1. SOB1 is in idle (output muted).
1
0
0
DOUT0 connects to SIB0.
DOUT1 connects to SIB1.
DIN0 connects to SOB0 and SOA0.
DIN1 connects to SOB1 and SOA1.
1
0
1
DOUT0 connects to SIB0.
DOUT1 connects to SIA1.
DIN0 connects to SOB0 and SOA0.
DIN1 connects to SOA1 and SOB1.
1
1
0
DOUT0 connects to SIA0.
DOUT1 connects to SIB1.
DIN0 connects to SOA0 and SOB0.
DIN1 connects to SOB1 and SOA1.
1
1
1
DOUT0 connects to SIA0.
DOUT1 connects to SIA1.
DIN0 connects to SOA0 and SOB0.
DIN1 connects to SOA1 and SOB1.
11
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DS100MB201
side is muxed to the disk drive side. The below table shows
the logic for the multiplexer and switch functions.
Device Connection Paths
DS100MB201
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
System Management Bus (SMBus)
and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be pulled
high to enable SMBus mode and allow access to the configuration registers.
The DS100MB201 has the AD[3:0] inputs in SMBus mode.
These pins set the SMBus slave address inputs. The AD[3:0]
pins have internal pull-down. When left floating or pulled low
the AD[3:0] = 0000'b, the device default address byte is A0'h.
Based on the SMBus 2.0 specification, the DS100MB201 has
a 7-bit slave address of 1010000'b. The LSB is set to 0'b (for
a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The
bold bits indicate the AD[3:0] pin map to the slave address
bits [4:1]. The device address byte can be set with the use of
the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant.
External pull-up resistor is required on the SDA. The resistor
value can be from 1 kΩ to 5 kΩ depending on the voltage,
loading and speed. The SCL may also require an external
pull-up resistor and it depends on the Host that drives the bus.
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1” indicating end of the
READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
TRANSFER OF DATA VIA THE SMBUS
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High
indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
RECOMMENDED SMBUS REGISTER SETTINGS
Upon power-up, the default register settings are not configured to an appropriate level. Below is the recommended
settings to configure the EQ and VOD to a medium level that
supports interconnect length of 10 inches FR4 trace. Please
refer to Table 4, Table 5 for additional information and recommended settings.
1. Reset the SMBus registers to default values:
Write 01'h to 0x00.
2. Set output voltage for all lanes:
Write 01'h to 0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43.
3. Set equalization ~6 dB at 5GHz for all lanes:
Write 30'h to 0x0F, 0x16, 0x1D, 0x24, 0x2C, 0x3A.
4. Set VOD = 0.8 Vp-p for all lanes:
Write 07'h to 0x17, 0x25, 0x2D, 0x34, 0x3B, 0x42.
SMBUS TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
When SMBus is enabled, all outputs of the DS100MB201
must write VOD2 register to 0x01 (hex). See Table 4 for
more information. Each channel must be set to the value of
0x01 (hex) through each register (0x18, 0x26, 0x2E, 0x35,
0x3C, 0x43) to ensure a proper output waveform. The driver
Vout voltage is set on a per lane basis using 6 different registers. Each register (0x17, 0x25, 0x2D, 0x34, 0x3B, 0x43)
controls the VOD to 600 mV and 800 mV.
TABLE 4. Output Driver Register Settings (must write when in SMBus mode)
Output Value
1V dB
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VOD Control 1
Register Setting
(800 mV)
0x07
VOD Control 2
10.3125 Gbps Operation
Register Setting (must set)
0x01
12
10” trace
DS100MB201
TABLE 5. SMBus Register Map
Address Register Name
Bit (s) Field
Type Default
Description
0x00
7:1
Reserved
R/W
Set bits to 0.
0
Reset
Reset
0x00
SMBus Reset
1: Reset registers to default value
0x01
PWDN lanes
7:0
PWDN CHx
R/W
0x00
Power Down per lane
[7]: NC — SOB1
[6]: DIN1 — SOA1
[5]: NC — SOB0
[4]: DIN0 — SOA0
[3]: SIB1 — DOUT1
[2]: SIA1 — NC
[1]: SIB0 — DOUT0
[0]: SIA0 — NC
00'h = all lanes enabled
FF'h = all lanes disabled
0x02
PWDN Control
7:1
Reserved
R/W
0x00
Set bits to 0.
0
PWDN Control
7:3
Reserved
2
SEL1
0: Selects B input and output
1: Selects A input and output
1
SEL0
0: Selects B input and output
1: Selects A input and output
0
FANOUT
0: Enable only A or B output depends on SEL1 and
SEL0
1: Enable both A and B output
0x03
0x08
SEL / FANOUT
Control
Pin Control Override 7:5
Reserved
0: Normal operation
1: Enable PWDN control in Register 0x01
R/W
R/W
0x00
0x00
Set bits to 0.
Set bits to 0.
4
Override IDLE
0: Allow IDLE pin control
1: Block IDLE pin control
3
Reserved
Set bit to 0.
2
Reserved
Set bit to 0.
1
Override SEL
0: Allow SEL pin control
1: Block SEL pin control
0
Override
FANOUT
0: Allow FANOUT pin control
1: Block FANOUT pin control
13
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DS100MB201
0x0F
0x12
0x15
0x16
0x17
0x18
SIA0
EQ Control
7:6
Reserved
5:0
SIA0 EQ
SIA0
IDLE Threshold
7:4
Reserved
3:0
IDLE threshold
DOUT0
IDLE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:0
Reserved
SIB0
EQ Control
7:6
Reserved
5:0
SIB0 EQ
DOUT0
VOD Control 1
7
Reserved
6:0
DOUT0 VOD 1
DOUT0
VOD Control 2
7:0
DOUT0 VOD 2
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R/W
0x20
Set bits to 0.
SIA0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x00
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x00
Set bits to 0.
Set bits to 0.
R/W
0x20
Set bits to 0.
SIB0 Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
DOUT0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
R/W
14
0x03
DOUT0 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x1D
0x20
0x23
0x24
0x25
SIB0
IDLE Threshold
7:4
Reserved
3:0
IDLE threshold
SIA1
EQ Control
7:6
Reserved
5:0
SIA1 EQ
SIA1
IDLE Threshold
7:4
Reserved
3:0
IDLE threshold
DOUT1
IDLE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:0
Reserved
SIB1
EQ Control
7:6
Reserved
5:0
SIB1 EQ
DOUT1
VOD Control 1
7
Reserved
6:0
DOUT1 VOD 1
R/W
0x00
DS100MB201
0x19
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x20
Set bits to 0.
SIA1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x00
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x00
Set bits to 0.
Set bits to 0.
R/W
0x20
Set bits to 0.
SIB1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
DOUT1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
15
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DS100MB201
0x26
DOUT1
VOD Control 2
7:0
DOUT1 VOD 2
R/W
0x03
DOUT1 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x27
SIB1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SOA0
IDLE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
0x2B
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x00
Set bits to 0.
3:0
Reserved
DIN0
EQ Control
7:6
Reserved
5:0
DIN0 EQ
SOA0
VOD Control 1
7
Reserved
6:0
SOA0 VOD 1
0x2E
SOA0
VOD Control 2
7:0
SOA0 VOD 2
R/W
0x03
SOA0 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x2F
DIN0
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SOB0
IDLE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:0
Reserved
Set bits to 0.
0x2C
0x2D
0x32
www.national.com
Set bits to 0.
R/W
0x20
Set bits to 0.
DIN0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
SOA0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = TBD mV
3F'h = TBD mV
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
16
0x00
Set bits to 0.
SOB0
VOD Control 1
7
Reserved
6:0
SOB0 VOD 1
0x35
SOB0
VOD Control 2
7:0
SOB0 VOD 2
R/W
0x03
SOB0 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x39
SOA1
IDLE Select
7:6
Reserve
R/W
0x00
Set bits to 0.
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:0
Reserved
Set bits to 0.
DIN1
EQ Control
7:6
Reserved
5:0
DIN1 EQ
SOA1
VOD Control 1
7
Reserved
6:0
SOA1 VOD 1
0x3C
SOA1
VOD Control 2
7:0
SOA1 VOD 2
R/W
0x03
SOA1 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x3D
DIN1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SOB1
IDLE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:0
Reserved
Set bits to 0.
7
Reserved
6:0
SOB1 VOD
0x3A
0x3B
0x40
0x42
SOB1
VOD Control
R/W
0x03
Set bit to 0.
SOB0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
R/W
0x20
Set bits to 0.
DIN1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
SOA1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x03
Set bits to 0.
Set bit to 0.
SOB1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
17
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DS100MB201
0x34
DS100MB201
0x43
SOB1
VOD Control 2
7:0
SOB1 VOD 2
R/W
0x03
DOUT0 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x47
Global VOD Adjust
7:2
Reserved
R/W
0x02
Set bits to 0.
1:0
VOD Adjust
00 = -25.0%
01 = -12.5%
10 = +0.0% (Default)
11 = +12.5%
Applications Information
board. See AN-1187 for additional information on LLP packages.
GENERAL RECOMMENDATIONS
The DS100MB201 is a high performance circuit capable of
delivering excellent performance. Careful attention must be
paid to the details associated with high-speed design as well
as providing a clean power supply. Refer to the LVDS
Owner's Manual for more detailed information on high speed
design tips to address signal integrity design issues.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS100MB201 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01 μF bypass capacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the DS100MB201.
Smaller body size capacitors can help facilitate proper component placement. Additionally, three capacitors with capacitance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and CML compatible outputs must have a
controlled differential impedance of 100Ω. It is preferable to
route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be
avoided if possible. If vias must be used, they should be used
sparingly and must be placed symmetrically for each side of
a given differential pair. Route the differential signals away
from other signals and noise sources on the printed circuit
www.national.com
18
DS100MB201
Physical Dimensions inches (millimeters) unless otherwise noted
54-pin LLP Package (5.5 mm x 10 mm x 0.8 mm, 0.5 mm pitch)
Package Number: SQA54A
19
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DS100MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization
Notes
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