NSC SCAN90004TVS

SCAN90004
4-Channel LVDS Buffer/Repeater
with Pre-Emphasis and IEEE 1149.6
General Description
Features
The SCAN90004 is a four channel 1.5 Gbps LVDS buffer/
repeater. High speed data paths and flow-through pinout
minimize internal device jitter and simplify board layout,
while configurable pre-emphasis overcomes ISI jitter effects
from lossy backplanes and cables. The differential inputs
interface to LVDS, and Bus LVDS signals such as those on
National’s 10-, 16-, and 18- bit Bus LVDS SerDes, as well as
CML and LVPECL. The differential inputs and outputs are
internally terminated with a 100Ω resistor to improve performance and minimize board space. The repeater function is
especially useful for boosting signals for longer distance
transmission over lossy cables and backplanes.
Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports
testability of both single-ended LVTTL/CMOS and highspeed differential LVDS interconnects. The 3.3V supply,
CMOS process, and LVDS I/O ensure stable high performance at low power over the entire industrial -40 to +85˚C
temperature range.
n 1.5 Gbps data rate per channel
n Configurable pre-emphasis drives lossy backplanes and
cables
n Low output skew and jitter
n Hot plug protection
n LVDS/CML/LVPECL compatible input, LVDS output
n On-chip 100Ω input and output termination
n 15 kV ESD protection on LVDS inputs and outputs
n IEEE 1149.1 and 1149.6 compliant
n Fault Insertion
n Single 3.3V supply
n Very low power consumption
n Industrial -40 to +85˚C temperature range
n Small TQFP Package Footprint
n Evaluation Kit Available
n See DS90LV004 for non-JTAG version
20113002
Pinout - Top View
20113001
SCAN90004 Block Diagram
© 2005 National Semiconductor Corporation
DS201130
www.national.com
SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis and IEEE 1149.6
November 2005
SCAN90004
Pin Descriptions
Pin
Name
TQFP Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS
IN0+
IN0−
13
14
I, LVDS
Channel 0 inverting and non-inverting differential inputs.
IN1+
IN1−
15
16
I, LVDS
Channel 1 inverting and non-inverting differential inputs.
IN2+
IN2−
19
20
I, LVDS
Channel 2 inverting and non-inverting differential inputs.
IN3+
IN3−
21
22
I, LVDS
Channel 3 inverting and non-inverting differential inputs.
DIFFERENTIAL OUTPUTS
OUT0+
OUT0−
48
47
O, LVDS
Channel 0 inverting and non-inverting differential outputs. (Note 1)
OUT1+
OUT1−
46
45
O, LVDS
Channel 1 inverting and non-inverting differential outputs. (Note 1)
OUT2+
OUT2−
42
41
O, LVDS
Channel 2 inverting and non-inverting differential outputs. (Note 1)
OUT3+
OUT3-
40
39
O, LVDS
Channel 3 inverting and non-inverting differential outputs. (Note 1)
DIGITAL CONTROL INTERFACE
PWDN
12
I, LVTTL
A logic low at PWDN activates the hardware power down mode.
PEM0
PEM1
1
2
I, LVTTL
Pre-emphasis Control Inputs (affects all Channels)
TDI
34
I, LVTTL
Test Data Input to support IEEE 1149.1 features
TDO
35
O, LVTTL
Test Data Output to support IEEE 1149.1 features
TMS
27
I, LVTTL
Test Mode Select to support IEEE 1149.1 features
TCK
26
I, LVTTL
Test Clock to support IEEE 1149.1 features
TRST
25
I, LVTTL
Test Reset to support IEEE 1149.1 features
VDD
3, 4, 5, 7, 10, 11,
28, 29, 32, 33
I, Power
VDD = 3.3V, ± 5%
GND
8, 9, 17, 18, 23,
24, 37, 38, 43,
44
I, Power
Ground
N/C
6, 30, 31, 36
POWER
No Connect
Note 1: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90004 device have been optimized for
point-to-point backplane and cable applications.
www.national.com
2
Supply Voltage (VDD)
EIAJ, 0Ω, 200pF
250V
−0.3V to +4.0V
CMOS Input Voltage
-0.3V to (VDD+0.3V)
LVDS Receiver Input Voltage
-0.3V to (VDD+0.3V)
LVDS Driver Output Voltage
-0.3V to (VDD+0.3V)
LVDS Output Short Circuit
Current
+40 mA
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature (Solder, 4sec)
260˚C
Max Pkg Power Capacity @ 25˚C
1.64W
Thermal Resistance (θJA)
Recommended Operating
Conditions
Supply Voltage (VCC)
0V to VCC
Industrial
−40˚C to +85˚C
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of products outside of recommended operation conditions.
13.2mW/˚C
ESD Last Passing Voltage
HBM, 1.5kΩ, 100pF
0V to VCC
Output Voltage (VO)
Operating Temperature (TA)
76˚C/W
Package Derating above +25˚C
3.15V to 3.45V
Input Voltage (VI) (Note 3)
Note 3: VID max < 2.4V
15kV
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(Note 4)
Max
Units
LVTTL DC SPECIFICATIONS (PWDN, PEM0, PEM1, TDI, TDO, TCK, TMS, TRST)
VIH
High Level Input Voltage
2.0
VDD
V
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = VDD = VDDMAX
−10
+10
µA
IIL
Low Level Input Current
VIN = VSS, VDD = VDDMAX
−10
+10
µA
IILR
Low Level Input Current
TDI, TMS, TRST
-40
-200
µA
CIN1
Input Capacitance
Any Digital Input Pin to VSS
COUT1
Output Capacitance
Any Digital Output Pin to VSS
VCL
Input Clamp Voltage
ICL = −18 mA
−1.5
VOH
High Level Output Voltage
(TDO)
IOH = −12 mA, VDD = 3.15 V
2.4
V
IOH = −100 µA, VDD = 3.15 V
VDD-0.2
V
VOL
3.5
pF
5.5
pF
−0.8
V
Low Level Output Voltage
(TDO)
IOL = 12 mA, VDD = 3.15 V
0.5
IOL = 100 µA, VDD = 3.15 V
0.2
V
V
IOS
Output Short Circuit Current
TDO
−15
−125
mA
IOZ
Output TRI-STATE Current
TDO
−10
+10
µA
100
mV
LVDS INPUT DC SPECIFICATIONS (INn ± )
VTH
Differential Input High
Threshold (Note 5)
VCM = 0.8V to 3.4V,
VDD = 3.45V
VTL
Differential Input Low
Threshold (Note 5)
VCM = 0.8V to 3.4V,
VDD = 3.45V
VCM = 0.8V to 3.4V, VDD = 3.45V
0
−100
0
mV
VID
Differential Input Voltage
VCMR
Common Mode Voltage Range VID = 150 mV, VDD = 3.45V
CIN2
Input Capacitance
IN+ or IN− to VSS
IIN
Input Current
VIN = 3.45V, VDD = VDDMAX
−10
+10
µA
VIN = 0V, VDD = VDDMAX
−10
+10
µA
100
2400
0.05
3.40
3.5
3
mV
V
pF
www.national.com
SCAN90004
Absolute Maximum Ratings (Note 2)
SCAN90004
Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(Note 4)
Max
Units
250
500
600
mV
35
mV
1.475
V
35
mV
−90
mA
LVDS OUTPUT DC SPECIFICATIONS (OUTn ± )
VOD
Differential Output Voltage,
0% Pre-emphasis (Note 5)
∆VOD
Change in VOD between
Complementary States
-35
RL = 100Ω between OUT+ and OUT−
VOS
Offset Voltage (Note 6)
1.05
∆VOS
Change in VOS between
Complementary States
1.18
-35
IOS
Output Short Circuit Current
OUT+ or OUT− Short to GND
−60
COUT2
Output Capacitance
OUT+ or OUT− to GND when TRI-STATE
5.5
All inputs and outputs enabled and active,
terminated with differential load of 100Ω
between OUT+ and OUT-.
117
140
mA
2.7
6
mA
210
300
ps
210
300
ps
2.0
3.2
ns
2.0
3.2
ns
pF
SUPPLY CURRENT (Static)
ICC
ICCZ
Supply Current
Supply Current - Power Down
Mode
PWDN = L
SWITCHING CHARACTERISTICS — LVDS OUTPUTS
tLHT
Differential Low to High
Transition Time
tHLT
Differential High to Low
Transition Time
tPLHD
Differential Low to High
Propagation Delay
tPHLD
Differential High to Low
Propagation Delay
tSKD1
Pulse Skew
|tPLHD–tPHLD|
25
80
ps
tSKCC
Output Channel to Channel
Skew
Difference in propagation delay (tPLHD or tPHLD)
among all output channels.
50
125
ps
tJIT
Jitter (0% Pre-emphasis)
(Note 7)
RJ - Alternating 1 and 0 at 750 MHz (Note 8)
1.1
1.5
psrms
DJ - K28.5 Pattern, 1.5 Gbps (Note 9)
43
62
psp-p
TJ - PRBS 223-1 Pattern, 1.5 Gbps (Note 10)
35
85
psp-p
Use an alternating 1 and 0 pattern at 200 Mb/s,
measure between 20% and 80% of VOD.
Use an alternating 1 and 0 pattern at 200 Mb/s,
measure at 50% VOD between input to output.
tON
LVDS Output Enable Time
Time from PWDN to OUT ± change from
TRI-STATE to active.
300
ns
tOFF
LVDS Output Disable Time
Time from PWDN to OUT ± change from active
to TRI-STATE.
12
ns
www.national.com
4
(Continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
RL = 500Ω,
CL = 35 pF
25.0
Typ
(Note 4)
Max
Units
SWITCHING CHARACTERISTICS — SCAN FEATURES
fMAX
Maximum TCK Clock
Frequency
tS
TDI to TCK, H or L
3.0
ns
tH
TDI to TCK, H or L
0.5
ns
tS
TMS to TCK, H or L
2.5
ns
tH
TMS to TCK, H or L
0.5
ns
tW
TCK Pulse Width, H or L
10.0
ns
tW
TRST Pulse Width, L
2.5
ns
tREC
Recovery Time, TRST to TCK
1.0
ns
MHz
Note 4: Typical parameters are measured at VDD = 3.3V, TA = 25˚C. They are for reference purposes, and are not production-tested.
Note 5: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
Note 6: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 7: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 8: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at
750MHz, tr = tf = 50ps (20% to 80%).
Note 9: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps,
tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 10: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage
= VID = 500mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%).
5
www.national.com
SCAN90004
Electrical Characteristics
SCAN90004
Feature Descriptions
Design-for-Test (DfT) Features
OUTPUT CHARACTERISTICS
IEEE 1149.1 (JTAG) SUPPORT
The output characteristics of the SCAN90004 have been
optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling.
The SCAN90004 supports a fully compliant IEEE 1149.1
interface. The Test Access Port (TAP) provides access to
boundary scan cells at each LVTTL I/O on the device for
interconnect testing. Differential pins are included in the
same boundary scan chain but instead contain IEEE1149.6
cells. IEEE1149.6 is the improved IEEE standard for testing
high-speed differential signals.
Refer to the BSDL file located on National’s website for the
details of the SCAN90004 IEEE 1149.1 implementation.
POWERDOWN MODE
The PWDN input activates a hardware powerdown mode.
When the powerdown mode is active (PWDN=L), all input
and output buffers and internal bias circuitry are powered off
and disabled. Outputs are tri-stated in powerdown mode.
JTAG Circuitry is active per the IEEE standard, but does not
switch unless TCK is toggling. When exiting powerdown
mode, there is a delay associated with turning on bandgap
references and input/output buffer circuits as indicated in the
LVDS Output Switching Characteristics
IEEE 1149.6 SUPPORT
AC-coupled differential interconnections on very high speed
(1+ Gbps) data paths are not testable using traditional IEEE
1149.1 techniques. The IEEE 1149.1 structures and methods are intended to test static (DC-coupled), single ended
networks. IEEE1149.6 is specifically designed for testing
high-speed differential, including AC coupled networks.
PRE-EMPHASIS
Pre-emphasis dramatically reduces ISI jitter from long or
lossy transmission media. Two pins are used to select the
pre-emphasis level for all outputs: off, low, medium, or high.
The SCAN90004 is intended for high-speed signalling up to
1.5 Gbps and includes IEEE1149.6 on all differential inputs
and outputs.
FAULT INSERTION
Fault Insertion is a technique used to assist in the verification
and debug of diagnostic software. During system testing
faults are "injected" to simulate hardware failure and thus
help verify the monitoring software can detect and diagnose
these faults. In the SCAN90004 an IEEE1149.1 "stuck-at"
instruction can create a stuck-at condition, either high or low,
on any pin or combination of pins. A more detailed description of the stuck-at feature can be found in NSC Applications
note AN-1313.
Pre-emphasis Control Selection Table
PEM1
PEM0
Pre-Emphasis
0
0
Off
0
1
Low
1
0
Medium
1
1
High
INPUT FAILSAFE BIASING
External pull up and pull down resistors may be used to
provide enough of an offset to enable an input failsafe under
open-circuit conditions. This configuration ties the positive
LVDS input pin to VDD thru a pull up resistor and the negative
LVDS input pin is tied to GND by a pull down resistor. The
pull up and pull down resistors should be in the 5kΩ to 15kΩ
range to minimize loading and waveform distortion to the
driver. The common-mode bias point ideally should be set to
approximately 1.2V (less than 1.75V) to be compatible with
the internal circuitry. Please refer to application note AN1194 “Failsafe Biasing of LVDS Interfaces” for more information.
www.national.com
6
SCAN90004
Typical Performance Characteristics
Power Supply Current vs. Bit Data Rate
Total Jitter (TJ) vs. Bit Data Rate
20113041
20113042
Total Jitter measured at 0V differential while running a PRBS 223-1 pattern
with a single channel active. VCC = 3.3V, TA = +25˚C, VID = 0.5V, 0%
Pre-emphasis
Dynamic power supply current was measured while running a clock or PRBS
223-1 pattern with all 4 channels active. VCC = 3.3V, TA = +25˚C, VID = 0.5V,
VCM = 1.2V
Total Jitter (TJ) vs. Temperature
Positive Edge Transition vs. Pre-emphasis Level
20113044
20113043
Total Jitter measured at 0V differential while running a PRBS 223-1 pattern
with a single channel active. VCC = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps
data rate, 0% Pre-emphasis
FIGURE 1. Typical Performance Characteristics of the SCAN90004
7
www.national.com
SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis and IEEE 1149.6
Physical Dimensions
inches (millimeters) unless otherwise noted
48-TQFP
NS Package Number VBC48a
Order Number SCAN90004TVS (250 piece Tray)
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
National Semiconductor
Americas Customer
Support Center
Email: [email protected]
Tel: 1-800-272-9959
www.national.com
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
National Semiconductor
Asia Pacific Customer
Support Center
Email: [email protected]
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: [email protected]
Tel: 81-3-5639-7560