Freescale Semiconductor Engineering Bulletin EB659 Rev. 1, 11/2006 MPC5500 Family Overview by: Randy Dees 32-bit Automotive Applications Ray Marshall TSPG Powertrain Systems 1 Introduction The MPC5554 microcontroller (MCU) was the first member of the MPC5500 family of next generation microcontrollers based on Power Architecture ™ technology initially designed for next generation automotive powertrain applications. More devices in the family have been introduced, including the MPC5533, MPC5534, MPC5553, MPC5561, MPC5565, MPC5566, and MPC5567 (all included in this document). The host processor core of the MPC5500 family devices is compatible with the Power Architecture technology. It is 100 percent user-mode compatible (with floating point library) with the PowerPC ISA. This core has instructions beyond the classic PowerPC ISA, including digital signal processing (DSP) instructions. The MPC553x and MPC556x devices include the variable length encoding (VLE) option for improved code density. © Freescale Semiconductor, Inc., 2006. All rights reserved. Table of Contents 1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MPC5500 Roadmap. . . . . . . . . . . . . . . . . . . . . . 2 MPC5533 Block Diagram . . . . . . . . . . . . . . . . . 3 MPC5534 Block Diagram . . . . . . . . . . . . . . . . . 4 MPC5553 Block Diagram . . . . . . . . . . . . . . . . . 5 MPC5554 Block Diagram . . . . . . . . . . . . . . . . . 6 MPC5551 Block Diagram . . . . . . . . . . . . . . . . . 7 MPC5565 Block Diagram . . . . . . . . . . . . . . . . . 8 MPC5566 Block Diagram . . . . . . . . . . . . . . . . . 9 MPC5567 Block Diagram . . . . . . . . . . . . . . . . 10 MPC5500 Family Comparison . . . . . . . . . . . . . . 11 MPC5500 Family Memory Map . . . . . . . . . . . . . 12 Package Options. . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 416 PBGA Ball Maps . . . . . . . . . . . . . . . . . . 17 4.2 324 PBGA Ball Maps . . . . . . . . . . . . . . . . . . 20 4.3 208 MAP BGA Ball Map . . . . . . . . . . . . . . . 21 Appendix A: Revision History Introduction MPC557x MPC5500 Family MPC5566 MPC5567 MPC5554 Performance/Integration MPC5565 MPC5553 MPC5561 MPC5534 MPC5533 MPC5510 Family MPC500 Family MPC565 MPC563 MPC555 MPC561 1999 • • • • • • • 2005 2006 • • • • • • • Availability Figure 1. MPC5500 Roadmap MPC5500 Family Overview, Rev. 1 2 Freescale Semiconductor Introduction e200z3 Core 1.5V Regulator Control FMPLL Nexus Interface MPC5533 Signal Processing Engine 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Integer Execution Unit Special Purpose Registers Exception Handler Multiply Unit Instruction Unit Variable Length Encoded Instruction JTAG Branch Prediction Unit Load/Store Unit Nexus Interrupt Controller Memory Management Unit Calibration Bus eDMA 32 Channels Master External Master Interface Master Master External Bus Interface Master Crossbar Switch (XBAR) Peripheral Bridge B (PBRIDGE_B) DSPI 2.5-Kb Data RAM 12-Kb Code RAM DSPI Peripheral Bridge A (PBRIDGE_A) eTPU (32 Ch) Boot Assist Module SRAM 48-Kb Slave FlexCAN Slave FlexCAN System/Bus Integration eSCI Flash 768-Kb Slave Slave Slave eQADC ADCi ADC AMUX LEGEND MPC5500 Device Module Acronyms e200z3 Core Component Acronyms CAN DSPI eDMA eQADC eSCI eTPU FMPLL SRAM DEC FIT TB WDT – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM – Decrementer – Fixed interval timer – Time base – Watchdog timer Figure 2. MPC5533 Block Diagram MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 3 Introduction e200z3 Core 1.5V Regulator Control FMPLL Nexus Interface MPC5534 Signal Processing Engine 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Integer Execution Unit Special Purpose Registers Exception Handler Multiply Unit Instruction Unit Variable Length Encoded Instruction JTAG Branch Prediction Unit Load/Store Unit Nexus Interrupt Controller Memory Management Unit Calibration Bus eDMA 32 Channels Master External Master Interface Master Master External Bus Interface Master Crossbar Switch (XBAR) Slave Slave FlexCAN DSPI 12-Kb Code RAM eMIOS (24 Ch) DSPI 2.5-Kb Data RAM Peripheral Bridge B (PBRIDGE_B) DSPI Peripheral Bridge A (PBRIDGE_A) eTPU (32 Ch) Boot Assist Module SRAM 64-Kb Slave FlexCAN Slave eSCI System/Bus Integration eSCI Flash 1-Mb Slave eQADC ADCi ADC ADC AMUX LEGEND MPC5500 Device Module Acronyms e200z3 Core Component Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM DEC FIT TB WDT – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM – Decrementer – Fixed interval timer – Time base – Watchdog timer Figure 3. MPC5534 Block Diagram MPC5500 Family Overview, Rev. 1 4 Freescale Semiconductor Introduction e200z6 Core 1.5V Regulator Control FMPLL Nexus Interface Signal Processing Engine 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Integer Execution Unit Special Purpose Registers Exception Handler Multiply Unit Instruction Unit Unified 8-Kb Cache JTAG Branch Prediction Unit Nexus Load/Store Unit eDMA 32 Channels Interrupt Controller Memory Management Unit Fast Ethernet Controller Master MPC5553 External Master Interface Master External Bus Interface Master Master Crossbar Switch (XBAR) Slave Slave FlexCAN DSPI 12-Kb Code RAM eMIOS (24 Ch) DSPI 2.5-Kb Data RAM Peripheral Bridge B (PBRIDGE_B) DSPI Peripheral Bridge A (PBRIDGE_A) eTPU (32 Ch) Boot Assist Module SRAM 64-Kb Slave FlexCAN Slave eSCI System/Bus Integration eSCI Flash 1.5-Mb Slave eQADC ADCi ADC ADC AMUX LEGEND MPC5500 Device Module Acronyms e200z6 Core Component Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM DEC FIT TB WDT – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM – Decrementer – Fixed interval timer – Time base – Watchdog timer Figure 4. MPC5553 Block Diagram MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 5 Introduction e200z6 Core 1.5V Regulator Control FMPLL Nexus Interface Signal Processing Engine 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Integer Execution Unit Special Purpose Registers Exception Handler Multiply Unit Instruction Unit Unified 32-Kb Cache JTAG Branch Prediction Unit Load/Store Unit Nexus MPC5554 Interrupt Controller Memory Management Unit eDMA 64 Channels External Master Interface Master Master External Bus Interface Master Crossbar Switch (XBAR) FlexCAN FlexCAN DSPI eMIOS (24 Ch) DSPI 16-Kb Code RAM eTPU (32 Ch) DSPI 3-Kb Data RAM Peripheral Bridge B (PBRIDGE_B) DSPI Peripheral Bridge A (PBRIDGE_A) eTPU (32 Ch) Boot Assist Module SRAM 64-Kb Slave FlexCAN Slave eSCI System/Bus Integration eSCI Flash 2-Mb Slave Slave Slave eQADC ADCi ADC ADC AMUX LEGEND MPC5500 Device Module Acronyms e200z6 Core Component Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM DEC FIT TB WDT – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM – Decrementer – Fixed interval timer – Time base – Watchdog timer Figure 5. MPC5554 Block Diagram MPC5500 Family Overview, Rev. 1 6 Freescale Semiconductor Introduction e200z6 Core 1.5V Regulator Control FMPLL Nexus Interface Signal Processing Engine 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Integer Execution Unit Special Purpose Registers Exception Handler Multiply Unit Instruction Unit Variable Length Encoded Instruction JTAG Branch Prediction Unit Unified 32-Kb Cache Nexus Load/Store Unit Memory Management Unit MPC5561 Interrupt Controller Calibration Bus eDMA 32 Channels Master External Master Interface FlexRay Master Master External Bus Interface Master Crossbar Switch (XBAR) Slave Slave Slave Slave FlexCAN FlexCAN eSCI eSCI PDI DSPI Peripheral Bridge B (PBRIDGE_B) DSPI Peripheral Bridge A (PBRIDGE_A) eMIOS (24 Ch) Boot Assist Module SRAM 192-Kb Slave eSCI System/Bus Integration eSCI Flash 1-Mb Slave eQADC ADCi ADC ADC AMUX LEGEND MPC5500 Device Module Acronyms e200z6 Core Component Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM DEC FIT TB WDT – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM – Decrementer – Fixed interval timer – Time base – Watchdog timer Figure 6. MPC5561 Block Diagram MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 7 Introduction e200z6 Core 1.5V Regulator Control FMPLL Nexus Interface MPC5565 Signal Processing Engine 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Integer Execution Unit Special Purpose Registers Exception Handler Multiply Unit Instruction Unit Variable Length Encoded Instruction JTAG Branch Prediction Unit Unified 8-Kb Cache Nexus Load/Store Unit Memory Management Unit Interrupt Controller Calibration Bus eDMA 32 Channels External Master Interface Master Master External Bus Interface Master Crossbar Switch (XBAR) Slave Slave FlexCAN FlexCAN DSPI 12-Kb Code RAM eMIOS (24 Ch) DSPI 2.5-Kb Data RAM Peripheral Bridge B (PBRIDGE_B) DSPI Peripheral Bridge A (PBRIDGE_A) eTPU (32 Ch) Boot Assist Module SRAM 64-Kb Slave FlexCAN Slave eSCI System/Bus Integration eSCI Flash 2-Mb Slave eQADC ADCi ADC ADC AMUX LEGEND MPC5500 Device Module Acronyms e200z6 Core Component Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM DEC FIT TB WDT – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM – Decrementer – Fixed interval timer – Time base – Watchdog timer Figure 7. MPC5565 Block Diagram MPC5500 Family Overview, Rev. 1 8 Freescale Semiconductor Introduction e200z6 Core 1.5V Regulator Control FMPLL Nexus Interface Signal Processing Engine 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Integer Execution Unit Special Purpose Registers Exception Handler Multiply Unit Instruction Unit Variable Length Encoded Instruction JTAG Branch Prediction Unit Unified 32-Kb Cache Nexus Load/Store Unit Memory Management Unit MPC5566 Interrupt Controller Calibration Bus Fast Ethernet Controller eDMA 64 Channels Master External Master Interface Master Master External Bus Interface Master Crossbar Switch (XBAR) Slave Slave FlexCAN FlexCAN FlexCAN DSPI eMIOS (24 Ch) DSPI 20-Kb Code RAM eTPU (32 Ch) DSPI 4-Kb Data RAM Peripheral Bridge B (PBRIDGE_B) DSPI Peripheral Bridge A (PBRIDGE_A) eTPU (32 Ch) Boot Assist Module SRAM 128-Kb Slave FlexCAN Slave eSCI System/Bus Integration eSCI Flash 3-Mb Slave eQADC ADCi ADC ADC AMUX LEGEND MPC5500 Device Module Acronyms e200z6 Core Component Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM DEC FIT TB WDT – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM – Decrementer – Fixed interval timer – Time base – Watchdog timer Figure 8. MPC5566 Block Diagram MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 9 Introduction e200z6 Core 1.5V Regulator Control FMPLL Nexus Interface MPC5567 Signal Processing Engine 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Integer Execution Unit Special Purpose Registers Exception Handler Multiply Unit Instruction Unit Variable Length Encoded Instruction JTAG Branch Prediction Unit Unified 8-Kb Cache Nexus Load/Store Unit Memory Management Unit Interrupt Controller Calibration Bus eDMA 32 Channels Fast Ethernet Controller Master Master External Master Interface FlexRay Master Master External Bus Interface Master Crossbar Switch (XBAR) Slave Slave FlexCAN FlexCAN FlexCAN FlexCAN DSPI 12-Kb Code RAM eMIOS (24 Ch) DSPI 2.5-Kb Data RAM Peripheral Bridge B (PBRIDGE_B) DSPI Peripheral Bridge A (PBRIDGE_A) eTPU (32 Ch) Boot Assist Module SRAM 64-Kb Slave FlexCAN Slave eSCI System/Bus Integration eSCI Flash 2-Mb Slave eQADC ADCi ADC ADC AMUX LEGEND MPC5500 Device Module Acronyms e200z6 Core Component Acronyms CAN DSPI eDMA eMIOS eQADC eSCI eTPU FMPLL SRAM DEC FIT TB WDT – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM – Decrementer – Fixed interval timer – Time base – Watchdog timer Figure 9. MPC5567 Block Diagram MPC5500 Family Overview, Rev. 1 10 Freescale Semiconductor MPC5500 Family Comparison 2 MPC5500 Family Comparison Table 1. MPC5500 Family Members MPC5500 Device Power Core Variable Length Instruction Support Cache Memory Management Unit (MMU) MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 MPC5567 e200z3 e200z3 e200z6 e200z6 e200z6 e200z6 e200z6 e200z6 Yes Yes No No Yes Yes Yes Yes None None 8 Kbyte Unified1 32 Kbyte Unified2 32 Kbyte Unified3 8 Kbyte Unified1 32 Kbyte Unified3 8 Kbyte Unified1 16 entry 16 entry 32 entry 32 entry 32 entry 32 entry 32 entry 32 entry 4 4x5 4x5 4x5 3x5 4x6 3 x5 4x5 5x5 Core Nexus Class 3+ (NZ3C3) Class 3+ (NZ3C3) Class 3+ (NZ6C3) Class 3+ (NZ6C3) Class 3+ (NZ6C3) Class 3+ (NZ6C3) Class 3+ (NZ6C3) Class 3+ (NZ6C3) SRAM 48 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 192 Kbyte 64 Kbyte 128 Kbyte 80 Kbyte Crossbar Flash External Bus (EBI) 768 Kbyte5 Shadow Block 1 Kbyte Data Bus 1.5 Mbyte6 2 Mbyte6 1 Mbyte6 2 Mbyte6 3 Mbyte6 2 Mbyte6 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte bit7 bit7 bit7 32-bit7 32-bit7 32-bit7 32-bit7 1 Main Array 7 Mbyte5 16 16-bit 32 32 24 24 24 24 268 268 268 268 Yes Yes Partial No Yes Yes Yes Yes 32 channel 32 channel 32 channel 64 channel 32 channel 32 channel 64 channel 32 channel None None Class 3 Class 3 Class 3 Class 3 Class 3 Class 3 1 2 2 2 4 2 2 2 eSCI_A Yes Yes Yes Yes Yes Yes Yes Yes eSCI_B No Yes Yes Yes Yes Yes Yes Yes eSCI_C No No No No Yes No No No eSCI_D No No No No Yes No No No 49 59 Address Bus Calibration Bus Direct Memory Access (DMA) DMA Nexus Serial Controller Area Network (CAN) CAN_A 9 2 2 2 3 3 39 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf CAN_B No No No 64 buf No 64 buf 64 buf 64 buf CAN_C 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf CAN_D No No No No No No 64 buf 64 buf CAN_E No No No No No No No 64 buf 2 3 3 4 3 3 4 3 DSPI_A No No No Yes No No Yes No DSPI_B No Yes Yes Yes Yes Yes Yes Yes DSPI_C Yes Yes Yes Yes Yes Yes Yes Yes DSPI_D Yes Yes Yes Yes No Yes Yes Yes 0 channel 24 channel 24 channel 24 channel 24 channel 24 channel 24 channel 24 channel SPI eMIOS MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 11 MPC5500 Family Memory Map Table 1. MPC5500 Family Members (continued) MPC5500 Device MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 MPC5567 eTPU eTPU_A eTPU_B 32 channel 32 channel 32 channel 64 channel 0 channel 32 channel 64 channel 32 channel Yes Yes Yes Yes No Yes Yes Yes No No No Yes No No Yes No Code Memory 12 Kbyte 12 Kbyte 12 Kbyte 16 Kbyte 0 Kbyte 12 Kbyte 20 Kbyte 12 Kbyte Parameter RAM 2.5 Kbyte 2.5 Kbyte 2.5 Kbyte 3 Kbyte 0 Kbyte 2.5 Kbyte 4 Kbyte 2.5 Kbyte Nexus Class 3 Class 3 Class 3 Class 3 No Class 3 Class 3 Class 3 Interrupt Controller 178 channel 210 channel 210 channel 300 channel 231 channel 231 channel 329 channel 281 channel Analog to Digital Converter (eQADC) 40 channel 40 channel 40 channel 40 channel 40 channel 40 channel 40 channel 40 channel ADC_0 Yes Yes Yes Yes Yes Yes Yes Yes ADC_1 No Yes Yes Yes Yes Yes Yes Yes Yes11 10 Fast Ethernet Controller (FEC) No No Yes FlexRay No No No No No No Yes10 No Yes No No Yes FlexRay Nexus No No No No Class 3 No No Class 3 Phase Lock Loop (PLL) FM FM FM FM FM FM FM FM 80 MHz 80 MHz 132 MHz 132 MHz 132 MHz 132 MHz 132 MHz 132 MHz 12 Maximum System Frequency Crystal Range Voltage Regulator Controller (VRC) 8–20 MHz 8–20 MHz 8–20 MHz 8–20 MHz 8–40 MHz 8–20 MHz 8–20 MHz 8–40 MHz Yes Yes Yes Yes Yes Yes Yes Yes NOTES: 1 2-way associative 2 8-way associative 3 4-way or 8-way associative 4 The actual crossbar is implemented as a 5x5 crossbar with two unused ports 5 16-byte flash page size for programming 6 32-byte flash page size for programming 7 May not be externally available in some package configurations 8 Either ADDR[8:31] or ADDR[6:29] can be selected. 9 Updated FlexCAN module with optional individual receive filters 10 The FEC signals are shared with data bus pins DATA[16:31] 11 The FEC signals are shared with the calibration bus 12 Initial automotive temperature range qualification 3 MPC5500 Family Memory Map This section describes the memory map for the MPC5500 devices discussed in this document. All addresses in the device, including those that are reserved, are identified in the tables. The addresses represent the physical addresses assigned to each IP module. Logical addresses are translated by the memory management unit (MMU) into physical addresses. Under software control of the MMU, the logical addresses allocated to IP blocks may be changed on a minimum of a 4-Kbyte boundary. Peripheral blocks may be redundantly mapped. The customer must use the MMU to prevent corruption. MPC5500 Family Overview, Rev. 1 12 Freescale Semiconductor MPC5500 Family Memory Map Table 2 shows a detailed memory map. √ 0x0010_0000–0x0017_FFFF 512 Kbyte 512 Kbyte Flash Array 0x0018_0000–0x001F_FFFF 512 Kbyte 512 Kbyte MPC5567 Flash Array MPC5566 256 Kbyte 256 Kbyte MPC5565 0x000C_0000–0x000F_FFFF MPC5561 √ Use MPC5554 Flash Array Used Size MPC5553 768 Kbyte 768 Kbyte Allocated Size MPC5534 0x0000_0000–0x000B_FFFF Address Range1 MPC5533 MPC5532 Table 2. Detailed MPC5500 Family Memory Map √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Flash Array √ 0x0020_0000–0x002F_FFFF 1 Mbyte 1 Mbyte Flash Array 0x0030_0000–0x00FF_FBFF ~13 Mbyte N/A Reserved 0x00FF_FC00–0x00FF_FFFF 1024 bytes 1024 bytes Flash Shadow Block √ √ √ √ √ √ √ √ √ 0x0100_0000–0x1FFF_FFFF 496 Mbyte 2 Mbyte Emulation Mapping of Flash Array √ √ √ √ √ √ √ √ √ 0x2000_0000–0x3FFF_FFFF 512 Mbyte N/A External Memory √ √ √ √ √ √ √ √ √ 0x4000_0000–0x4000_7FFF 32 Kbyte 32 Kbyte SRAM Array, Standby Powered √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 0x4000_8000–0x4000_BFFF 16 Kbyte 16 Kbyte SRAM Array 0x4000_C000–0x4000_FFFF 16 Kbyte 16 Kbyte SRAM Array 0x4001_0000–0x4001_3FFF 16 Kbyte 16 Kbyte SRAM Array √ √ 0x4001_4000–0x4001_FFFF 48 Kbyte 48 Kbyte SRAM Array √ √ √ 0x4002_0000–0x4002_FFFF 64 Kbyte 64 Kbyte SRAM Array 0x4003_0000–0x9FFF_FFFF (<15 Gb) N/A Reserved 0xA000_0000–0xBFFF_FFFF 512 Mbyte 256 Mbyte Parallel Digital Interface 0xC000_0000–0xC3EF_FFFF 63 Mbyte N/A Reserved 0xC3F0_0000–0xC3F0_3FFF 16 kbyte 16 kbyte Bridge A Registers 0xC3F0_4000–0xC3F7_FFFF 496 Kbyte N/A Reserved 0xC3F8_0000–0xC3F8_3FFF 16 Kbyte 20 kbyte 0xC3F8_4000–0xC3F8_7FFF 16 Kbyte 48 Kbyte 0xC3F8_8000–0xC3F8_BFFF 16 Kbyte 28 Kbyte Flash Configuration 0xC3F8_C000–0xC3F8_FFFF 16 Kbyte N/A Reserved 0xC3F9_0000–0xC3F9_3FFF 16 Kbyte 2.5 Kb System Integration Unit (SIU) 0xC3F9_4000–0xC3F9_FFFF 48 Kbyte N/A Reserved 0xC3FA_0000–0xC3FA_3FFF 16 Kbyte 1056 Modular Timer System (eMIOS) √ Bridge A Peripherals √ √ √ √ √ √ √ √ √ FMPLL √ √ √ √ √ √ √ √ √ External Bus Interface (EBI) Configuration √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 0xC3FA_4000–0xC3FA_7FFF 16 Kbyte 1056 Modular Timer System (eMIOS_B) 0xC3FA_8000–0xC3FB_FFFF 96 Kbyte N/A Reserved 0xC3FC_0000–0xC3FC_3FFF 16 Kbyte 3 Kbyte Enhanced Time Processing Unit (eTPU) Registers 0xC3FC_4000–0xC3FC_7FFF 16 Kbyte N/A Reserved √ 3 √ √ MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 13 MPC5500 Family Memory Map 0xC3FC_8A00–0xC3FC_8BFF 0.5 Kbyte 0xC3FC_8C00–0xC3FC_8FFF 1 Kbyte 0xC3FC_9000–0xC3FC_BFFF √ √ √ √ MPC5567 √ MPC5566 eTPU Shared Data Memory (Parameter RAM) MPC5565 2.5 Kbyte MPC5561 16 Kbyte MPC5554 0xC3FC_8000–0xC3FC_09FF Use MPC5553 Used Size MPC5534 Allocated Size MPC5533 Address Range1 MPC5532 Table 2. Detailed MPC5500 Family Memory Map (continued) √ √ √ √ √ √ eTPU Parameter RAM Reserved 0xC3FC_C000–0xC3FC_FFFF 16 Kbyte 3 Kbyte eTPU Shared Data Memory (Parameter RAM) mirror √ √ √ √ √ √ √ √ 0xC3FD_0000–0xC3FD_2FFF 20 Kbyte 12 Kbyte eTPU Shared Code RAM (12K,16K, or 20K) √ √ √ √ √ √ √ √ 0xC3FD_3000–0xC3FD_3FFF 4 Kbyte 0xC3FD_4000–0xC3FD_4FFF 4 Kbyte √ √ 0xC3FD_5000–0xC3FF_7FFF 156 Kbyte N/A Reserved 0xC3FF_8000–0xC3FF_BFFF 16 Kbyte N/A Reserved 0xC3FF_C000–0xC3FF_FFFF 16 Kbyte N/A Reserved N/A Reserved 0xC400_0000–0xDFFF_FFFF (448 Mbyte) √ Bridge B Peripherals 0xE000_0000–0xFBFF_FFFF (448 Mbyte) N/A Reserved 0xFC00_0000–0xFFEF_FFFF 63 Mbyte N/A Reserved 0xFFF0_0000–0xFFF0_3FFF 16 Kbyte N/A Bridge B Registers √ √ √ √ √ √ √ √ √ 0xFFF0_4000–0xFFF0_7FFF 16 Kbyte N/A Crossbar (XBAR) √ √ √ √ √ √ √ √ √ 0xFFF0_8000–0xFFF0_FFFF 32 Kbyte N/A Reserved 0xFFF1_0000–0xFFF3_FFFF 192 Kbyte N/A Reserved 0xFFF4_0000–0xFFF4_3FFF 16 Kbyte N/A ECSM √ √ √ √ √ √ √ √ √ 0xFFF4_4000–0xFFF4_7FFF 16 Kbyte N/A DMA Controller 2 (eDMA) √ √ √ √ √ √ √ √ √ 0xFFF4_8000–0xFFF4_BFFF 16 Kbyte N/A Interrupt Controller (INTC) √ √ √ √ √ √ √ √ √ √ √ √ √ √ 2 0xFFF4_C000–0xFFF4_C3FF 1 Kbyte N/A Fast Ethernet Controller (FEC) 0xFFF4_C400–0xFFF4_FFFF 15 Kbyte N/A Reserved 0xFFF5_0000–0xFFF7_FFFF 192 Kbyte N/A Reserved 0xFFF8_0000–0xFFF8_3FFF 16 Kbyte 164 Enhanced Queued Analog-to-Digital Converter (eQADC) 0xFFF8_4000–0xFFF8_7FFF 16 Kbyte 164 Enhanced Queued Analog-to-Digital Converter (eQADC_B)3 0xFFF8_8000–0xFFF8_FFFF 32 Kbyte N/A Reserved 0xFFF9_0000–0xFFF9_3FFF 16 Kbyte 200 Deserial Serial Peripheral Interface (DSPI_A) 0xFFF9_4000–0xFFF9_7FFF 16 Kbyte 200 Deserial Serial Peripheral Interface (DSPI_B) 0xFFF9_8000–0xFFF9_BFFF 16 Kbyte 200 Deserial Serial Peripheral Interface (DSPI_C) √ 0xFFF9_C000–0xFFF9_FFFF 16 Kbyte 200 Deserial Serial Peripheral Interface (DSPI_D) √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ MPC5500 Family Overview, Rev. 1 14 Freescale Semiconductor MPC5500 Family Memory Map MPC5561 MPC5565 MPC5566 MPC5567 16 Kbyte 200 Deserial Serial Peripheral Interface (DSPI_E)3 0xFFFA_4000–0xFFFA_7FFF 16 Kbyte 200 Deserial Serial Peripheral Interface (DSPI_F)3 0xFFFA_8000–0xFFFA_FFFF 32 Kbyte N/A Reserved 0xFFFB_0000–0xFFFB_3FFF 16 Kbyte 44 Serial Communications Interface (SCI_A) √ 0xFFFB_4000–0xFFFB_7FFF 16 Kbyte 44 Serial Communications Interface (SCI_B) √ 0xFFFB_8000–0xFFFB_BFFF 16 Kbyte 44 Serial Communications Interface (SCI_C) √ 0xFFFB_C000–0xFFFC_FFFF 16 Kbyte 44 Serial Communications Interface (SCI_D) √ 0xFFFC_0000–0xFFFC_3FFF 16 Kbyte 1152 Controller Area Network (FlexCAN_A) 0xFFFC_4000–0xFFFC_7FFF 16 Kbyte 1152 Controller Area Network (FlexCAN_B) 0xFFFC_8000–0xFFFC_BFFF 16 Kbyte 1152 Controller Area Network (FlexCAN_C) 0xFFFC_C000–0xFFFC_FFFF 16 Kbyte 1152 Controller Area Network (FlexCAN_D) 0xFFFD_0000–0xFFFD_3FFF 16 Kbyte 1152 Controller Area Network (FlexCAN_E) 0xFFFD_4000–0xFFFD_FFFF 48 Kbyte N/A Reserved 0xFFFE_0000–0xFFFE_3FFF 16 Kbyte 2 kbyte FlexRay 0xFFFE4000–0xFFFE_7FFF 16 Kbyte Reserved 0xFFFE_8000–0xFFFE_BFFF 16 Kbyte Parallel Digital Interface 0xFFFF_C000–0xFFFF_FFFF4 16 Kbyte Boot Assist Module (BAM) MPC5554 0xFFFA_0000–0xFFFA_3FFF 16 Kbyte MPC5553 Used Size √ MPC5534 Allocated Size Use MPC5533 Address Range1 MPC5532 Table 2. Detailed MPC5500 Family Memory Map (continued) √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ NOTES: 1 If allocated size is greater than used size, the base address for the module is the lowest address of the listed address range, unless noted otherwise. 2 The fast Ethernet controller (FEC) uses different pins on the MPC5553/MPC5566 and the MPC5567. 3 Reserved for future compatibility. No device is currently defined that uses these regions. 4 BAM address range is configured so that 4 kbytes BAM occupies 0xFFFF_F000-0xFFFF_FFFF. MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 15 Package Options 4 Package Options The members of the MPC5500 family are all pin-compatible, but the different devices are available in a range of packages. Not all features are available in the smaller packages or on all devices. Table 3. Device Package Options Device 208 MAPBGA1 324 PBGA 416 PBGA 496 CSP2 Calibration Bus MPC5533 Yes3,4 No7 No Yes Yes MPC5534 3,4 3 Yes No Yes Yes Yes MPC5553 Yes4 Yes3 Yes5 Yes Partial6 MPC5554 No No Yes3 Yes No MPC5561 No Yes No No No MPC5565 No7 Yes3,4 No4,7 Yes Yes MPC5566 No No Yes3 Yes Yes MPC5567 No7 Yes4 Yes3,5 Yes Yes 4 or 12-bit MDO 4 or 12-bit MDO Nexus port availability 4-bit MDO Only 4 or 12-bit MDO Bus availability None (OE and CS0 available for GPIO) 16-bit data / 20-bit address 4 chip selects8 Calibration bus availability None None None 16-bit data / 21/19-bit address 1/3 chip selects 34 40 40 40 No No Yes — Analog channels Ethernet available 9 32-bit data / 32-bit data / 24/26-bit address 24/26-bit address 4 chip selects 4 chip selects NOTES: 1 The 208 MAPBGA package is not available through distribution. If demand warrants, consult factory on availability. 2 The VertiCal CSP package is a 496 ball device mounted on a sub-assembly to fit into the 208, 324, or 416 ball footprint. It is not available as a standalone packaged device. 3 Predominate package. Though all packages may be available, the predominate package is the package in which most of the volume deliveries are expected. 4 Not available to distribution customers. 5 Predominate package for Ethernet use. 6 The MPC5553 lose use of 16 data bus signals in the 416 ball sub-assembly for the calibration data bus. The address bus is shared between the calibration bus and the normal system bus. Note: the fast Ethernet controller (FEC) requires these same 16 data bus signals on this devices. On the MPC5567, the FEC is shared with the calibration bus. 7 Depending on demand, consult factory for availability, 8 Up to 24 bits of address with zero chip selects can optionally be selected. 9 On devices that include Ethernet only. MPC5500 Family Overview, Rev. 1 16 Freescale Semiconductor Package Options 4.1 416 PBGA Ball Maps 4.1.1 MPC5554/MPC5566 Figure 10 is a pinout for the MPC5554/MPC5566 416 PBGA package, Revision A. NOTE: On the MPC5554, Ball J23 is VDDEH6. On the MPC5566, ball J23 is VDDEH10. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A VSS VSTBY AN37 AN11 VDDA1 AN16 AN1 AN5 VRH AN23 AN27 AN28 AN35 VSSA0 AN15 ETRIG ETPUB ETPUB ETPUB ETPUB 1 18 20 24 27 B VDD VSS AN36 AN39 AN19 AN20 AN0 AN4 REF BYPC AN22 AN26 AN31 AN32 VSSA0 AN14 ETRIG ETPUB ETPUB ETPUB ETPUB MDO10 MDO7 0 21 25 28 31 MDO4 VDD VSS AN8 AN17 VSSA1 AN21 AN3 AN7 VRL AN25 AN30 AN33 VDDA0 AN13 ETPUB ETPUB ETPUB ETPUB MDO9 19 22 26 30 MDO6 AN29 AN34 VDDEH AN12 9 ETPUB ETPUB ETPUB ETPUB MDO5 16 17 23 29 MDO2 VDDEH 8 C VDD33 ETPUA ETPUA D 30 31 E VDD ETPUA ETPUA VDDEH 28 29 1 VSS AN38 AN9 AN10 AN18 AN2 AN6 AN24 16 17 18 19 20 21 GPIO 205 22 23 24 25 26 VDD VDD33 VSS MDO0 VSS MDO1 VSS VDDE7 VDD C VSS VDDE7 TCK TDI D VDDE7 TMS TDO TEST E MDO11 MDO8 MDO3 VDD A VDDE7 B ETPUA ETPUA ETPUA VDDEH F 24 27 26 1 MSEO0 JCOMP EVTI EVTO F G ETPUA ETPUA ETPUA ETPUA 23 22 25 21 MSEO1 MCKO GPIO 204 ETPUB G 15 H ETPUA ETPUA ETPUA ETPUA 20 19 18 17 Version 1.3p – 29 May 2004 RDY K ETPUA ETPUA ETPUA ETPUA 12 11 10 9 VSS VSS VSS VSS L ETPUA ETPUA ETPUA ETPUA 8 7 6 5 VSS VSS VSS VSS VSS VSS VDDE7 ETPUB ETPUB ETPUB ETPUB L 6 4 3 2 VSS VDDE7 TCRCLK ETPUB ETPUB B 1 0 VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 N VSS PCSA3 PCSB4 SCKB PCSB2 P VSS VDDE2 VDDE2 VSS VSS VSS VSS ETPUA TCRCLK 0 A VDDE2 VDDE2 VSS VSS VSS VSS VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS VSS VSS VSS BDIP TEA P CS3 CS2 CS1 CS0 R WE3 WE2 WE1 WE0 VDDE2 VDDE2 VDDE2 T VDDE2 TSIZ0 RD_WR VDDE2 U ADDR 16 V ADDR 18 ADDR W 20 ADDR 22 ADDR 21 ADDR VDDE2 11 ADDR AA 24 ADDR 23 ADDR 13 ADDR 12 AB VDDE2 ADDR 25 ADDR 15 ADDR 14 ADDR 26 ADDR 27 ADDR 31 VSS VDD DATA 26 DATA 28 VDDE2 ADDR AD 28 ADDR 30 DATA 25 DATA 27 Y AC TSIZ1 TA VDD33 ADDR 17 TS ADDR 8 ADDR 19 ADDR 9 ADDR 10 ETPUB ETPUB H 14 13 VSS ETPUB ETPUB ETPUB ETPUB K 10 8 7 5 VDDE7 VDDE7 VDDE7 VDDE7 ETPUA ETPUA ETPUA ETPUA M 4 3 2 1 N GPIO 203 VDDEH ETPUB ETPUB ETPUB J 12 11 9 6/10* ETPUA ETPUA ETPUA ETPUA J 16 15 14 13 M VSS VSS PCSB5 SOUTA VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U VSS SINA SINB SCKA R VPP CNTXC RXDA RSTOUT RST CFG T V RXDB CNRXC TXDB RESET W Note: NC WKP CFG No connect. AC22 & AD23 reserved BOOT CFG1 VDDEH PLL 6 CFG1 DATA 30 DATA 31 DATA 8 DATA 10 VDDE2 DATA 12 DATA 29 DATA 9 DATA 11 DATA 13 DATA 15 DATA 14 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 2 8 12 21 4 NC EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 6 10 15 17 22 3 VRC VSS VSS SYN Y BOOT EXTAL AA CFG0 VDD VRC CTL PLL CFG0 XTAL AB VSS VDD VRC33 VDD SYN AC NC VSS VDD VSS VDD DATA 24 VDD33 GPIO 207 AE ADDR 29 VSS VDD DATA 17 DATA 19 DATA 21 DATA 23 DATA 0 DATA 2 DATA 4 DATA 6 OE BR BG EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 5 9 13 16 19 23 1 VDD AE AF VSS VDD DATA 16 DATA 18 VDDE2 DATA 20 DATA 22 GPIO 206 DATA 1 DATA 3 VDDE2 DATA 5 DATA 7 BB EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 4 7 11 14 18 20 0 ENG CLK VSS AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 25 26 15 16 17 18 19 20 21 22 23 24 VDD33 AD Figure 10. MPC5554/MPC5566 416 PBGA Ball Map Diagram MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 17 Package Options 4.1.2 MPC5553 Figure 11 is a pinout for the MPC5553 416 PBGA package. The MPC5553 and the MPC5554/MPC5565/MPC5566 are pin-compatible; however, the MPC5553 ball map is shown here to highlight the balls not connected to any signal on the MCP5553 (the eTPUB[0:31] and TSIZ[0:1]). The alternate Ethernet signals that are multiplexed with the data bus are not shown for the MPC5553. NOTE Some pins have names that include functions unavailable on all family members. For example, ball R25 of the 416 BGA package is named ‘SINA’, but the MPC5553 does not have a DSPI_A module. In this case, the SINA pin can only be used for its alternate functions of GPIO94 or PCSC2. See the specific device reference manual for functions available on each device in the family. If the MPC5534 were available in the 416 PBGA package, then it would also be missing the following signals: WE2, WE3, ADDR[8:11], and TEA. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A VSS VSTBY AN37 AN11 VDDA1 AN16 AN1 AN5 VRH AN23 AN27 AN28 AN35 VSSA0 AN15 ETRIG 1 NC_1 NC_2 NC_3 NC_4 GPIO 205 B VDD VSS AN36 AN39 AN19 AN20 AN0 AN4 REF BYPC AN22 AN26 AN31 AN32 VSSA0 AN14 ETRIG 0 NC_5 NC_6 NC_7 NC_8 MDO10 MDO7 VDD VSS AN8 AN17 VSSA1 AN21 AN3 AN7 VRL AN25 AN30 AN33 VDDA0 AN13 NC_9 NC_10 NC_11 NC_12 MDO9 AN29 AN34 VDDEH AN12 9 C VDD33 ETPUA ETPUA D 30 31 VDD VSS E ETPUA ETPUA VDDEH 28 29 1 F ETPUA ETPUA ETPUA VDDEH 24 27 26 1 G ETPUA ETPUA ETPUA ETPUA 23 22 25 21 AN38 AN9 AN10 AN18 AN2 AN6 AN24 MDO3 MDO2 VDDEH 8 VDD Version 2.1 – 13 July 2004 ETPUA ETPUA ETPUA ETPUA H 20 19 18 17 J NC_13 NC_14 NC_15 NC_16 MDO5 MDO6 22 23 24 25 26 VDD VDD33 VSS MDO4 MDO0 VSS MDO1 VSS VDDE7 VSS VDDE7 VDDE7 TMS MSEO0 JCOMP EVTI EVTO F MSEO1 MCKO GPIO 204 NC_17 G MDO11 MDO8 RDY ETPUA ETPUA ETPUA ETPUA 16 15 14 13 GPIO 203 A VDDE7 B VDD C TCK TDI D TDO TEST E NC_18 NC_19 H VDDEH NC_20 NC_21 NC_22 J 10 ETPUA ETPUA ETPUA ETPUA K 12 11 10 9 VSS VSS VSS VSS L ETPUA ETPUA ETPUA ETPUA 8 7 6 5 VSS VSS VSS VSS VSS VSS VSS VDDE7 NC_27 NC_28 NC_29 NC_30 L M ETPUA ETPUA ETPUA ETPUA 4 3 2 1 VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 NC_31 NC_32 NC_33 N BDIP TEA ETPUA TCRCLK 0 A VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 N P CS3 CS2 CS1 CS0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 P R WE3 WE2 WE1 WE0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSB5 SOUTA VDDE2 T VDDE2 NC_34 RD_WR VDDE2 U ADDR NC_35 16 V TA ADDR 18 ADDR 17 TS ADDR 8 ADDR W 20 ADDR 19 ADDR 9 ADDR 10 ADDR 22 ADDR 21 ADDR VDDE2 11 Y ADDR 24 ADDR 23 ADDR 13 ADDR 12 AB VDDE2 ADDR 25 ADDR 15 ADDR 14 ADDR AC 26 ADDR 27 ADDR 31 VSS AD ADDR 28 ADDR 30 VSS AE ADDR 29 VSS VSS 1 AA AF VSS VDD33 VSS NC_23 NC_24 NC_25 NC_26 K VDDE7 VDDE7 VDDE7 VDDE7 SINA SINB SCKA R VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U VPP CNTXC RXDA RSTOUT RST CFG Note: WKP CFG VDD DATA 28 VDD DATA 24 DATA 25 VDD DATA 17 DATA 19 VDD DATA 16 DATA 18 2 3 4 NC_37 No connect. AC22 & AD23 reserved VDDE2 DATA 30 DATA 31 DATA 8 DATA 10 VDDE2 DATA 12 DATA 27 DATA 29 VDD33 GPIO 207 DATA 9 DATA 11 DATA 13 DATA 15 DATA 21 DATA 23 DATA 0 DATA 2 DATA 4 DATA 6 OE BR BG VDDE2 DATA 20 DATA 22 GPIO 206 DATA 1 DATA 3 VDDE2 DATA 5 DATA 7 5 6 7 8 9 10 11 12 13 DATA 14 BOOT CFG1 VDDEH PLL 6 CFG1 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36 2 8 12 21 4 VRC VSS 17 18 19 20 21 22 Y BOOT EXTAL AA CFG0 PLL CFG0 XTAL AB VSS VDD VRC33 VDD SYN AC VSS VDD EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 5 9 13 16 1 19 23 16 VSS SYN VRC CTL EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37 6 10 15 17 3 22 15 V VDD NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 4 7 11 14 0 18 20 14 T RXDB CNRXC TXDB RESET W No connects (x = 1 to 38) NC_X NC_36 DATA 26 M 23 24 VDD33 AD VDD AE ENG CLK VSS AF 25 26 Figure 11. MPC5553 416 PBGA Ball Map Diagram MPC5500 Family Overview, Rev. 1 18 Freescale Semiconductor Package Options 4.1.3 MPC5567 Figure 11 is a pinout for the MPC5567 416 PBGA package. The MPC5567 and the MPC5553/MPC5554 are pin-compatible; however, the MPC5567 ball map is shown here to highlight the balls not connected to any signals and the balls used for Ethernet. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A VSS VSTBY AN37 AN11 VDDA1 AN16 AN1 AN5 VRH AN23 AN27 AN28 AN35 VSSA0 AN15 ETRIG 1 NC VDDE FEC_ FEC_ 13 TX_CLK TX_ER B VDD VSS AN36 AN39 AN19 AN20 AN0 AN4 REF BYPC AN22 AN26 AN31 AN32 VSSA0 AN14 ETRIG 0 NC FEC_ TXD2 VDD VSS AN8 AN17 VSSA1 AN21 AN3 AN7 VRL AN25 AN30 AN33 VDDA0 AN13 NC NC AN29 AN34 VDDEH AN12 9 NC FEC_ COL C VDD33 ETPUA ETPUA D 30 31 E VDD ETPUA ETPUA VDDEH 28 29 1 VSS AN38 AN9 AN10 AN18 AN2 AN6 AN24 18 19 20 21 GPIO 205 22 23 MDO11 MDO8 24 25 26 VDD VDD33 VSS A FEC_ TXD1 FEC_ MDO10 MDO7 TXD0 MDO4 MDO0 VSS FEC_ TX_EN FEC_ TXD3 MDO9 MDO6 MDO1 VSS VDDE7 VDD C FEC_ CRS VDDE 13 MDO5 MDO2 VDDEH 8 VSS VDDE7 TCK TDI D VDDE7 TMS TDO TEST E MDO3 VDD VDDE7 B ETPUA ETPUA ETPUA VDDEH F 24 27 26 1 MSEO0 JCOMP EVTI EVTO F G ETPUA ETPUA ETPUA ETPUA 23 22 25 21 MSEO1 MCKO GPIO 204 FEC_ RX_ER G H ETPUA ETPUA ETPUA ETPUA 20 19 18 17 Version 1.2 – 11 July 2005 ETPUA ETPUA ETPUA ETPUA K 12 11 10 9 VSS VSS VSS VSS ETPUA ETPUA ETPUA ETPUA 8 7 6 5 VSS VSS VSS VSS VSS VSS VSS L FEC_ RXD1 FEC_ RXD0 K VDDE7 FEC_ MDIO NC NC NC L NC NC NC SINB M VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS VSS VDDE7 ETPUA TCRCLK 0 A VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 TEA P CS3 CS2 R WE3 WE2 T VDDE2 NC U ADDR 16 NC V ADDR 18 ADDR W 20 CS1 WE1 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 P WE0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSB5 SOUTA VDDE2 RD_WR VDDE2 VSS VSS SINA SCKA R VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U VDD33 ADDR 17 TS ADDR 8 ADDR 19 ADDR 9 ADDR 10 ADDR 22 ADDR 21 ADDR VDDE2 11 ADDR AA 24 ADDR 23 ADDR 13 ADDR 12 AB VDDE2 ADDR 25 ADDR 15 ADDR 14 ADDR 26 ADDR 27 ADDR 31 VSS VDD DATA 26 DATA 28 VDDE2 DATA 30 DATA 31 DATA 8 DATA 10 VDDE2 DATA 12 ADDR AD 28 ADDR 30 DATA 25 DATA 27 DATA 29 VDD33 GPIO 207 DATA 9 DATA 11 DATA 13 DATA 15 AC SOUTB PCSB3 PCSB0 PCSB1 N CS0 TA Y FEC_ FEC_ RXD3 RX_CLK J FEC_ RXD2 VDDE2 VDDE2 BDIP FEC_ VDDE H RX_DV 12 VDDE 12 ETPUA ETPUA ETPUA ETPUA M 4 3 2 1 N GPIO 203 VDDEH FEC_ 10 MDC RDY ETPUA ETPUA ETPUA ETPUA J 16 15 14 13 VPP CNTXC RXDA RSTOUT RST CFG Note: WKP CFG NC_1 NC_2 V RXDB CNRXC TXDB RESET W No connect NC T No connect. AC22 & AD23 reserved DATA 14 BOOT CFG1 VDDEH PLL 6 CFG1 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 2 8 12 21 4 NC_1 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 6 10 15 17 22 3 PLL CFG2 VSS SYN Y BOOT EXTAL AA CFG0 VDD VRC CTL PLL CFG0 XTAL AB VSS VDD VRC33 VDD SYN AC NC_2 VSS VDD VSS VDD DATA 24 AE ADDR 29 VSS VDD DATA 17 DATA 19 DATA 21 DATA 23 DATA 0 DATA 2 DATA 4 DATA 6 OE BR BG EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 5 9 13 16 19 23 1 VDD AE AF VSS VDD DATA 16 DATA 18 VDDE2 DATA 20 DATA 22 GPIO 206 DATA 1 DATA 3 VDDE2 DATA 5 DATA 7 NC EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 4 7 11 14 18 20 0 ENG CLK VSS AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 25 26 15 16 17 18 19 20 21 22 23 24 VDD33 AD Figure 12. MPC5567 416 PBGA Ball Map Diagram NOTE Ball Y25 changes from VRCVSS on all other MPC5500 devices (currently defined) to PLLCFG2 on the MPC5567. PLLCFG2 is required to support a 40-MHz clock option for the FlexRay. MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 19 Package Options 4.2 324 PBGA Ball Maps 4.2.1 MPC5533/MPC5534/MPC5553/MPC5561/MPC5565 Figure 13 is a pinout for the MPC5533/MPC5534/MPC5553/MPC5561/MPC5565 324 PBGA package. A 1 2 3 4 5 VSS VDD VSTBY AN37 AN11 VSS VDD AN36 AN39 AN19 VSS VDD AN8 AN17 B VDD33 C ETPUA ETPUA 30 31 ETPUA ETPUA ETPUA D 26 28 29 E VSS 6 VDD 7 8 9 10 11 12 13 14 15 16 AN1 AN5 VRH VRL AN27 AN28 AN35 VSSA0 AN12 MDO11 MDO10 MDO8 AN16 AN0 AN4 REF BYPC AN23 AN26 AN31 AN32 VSSA0 AN13 MDO9 MDO7 AN20 AN21 AN3 AN7 AN22 AN25 AN30 AN33 VDDA0 AN14 MDO5 AN29 AN34 VDDEH AN15 9 MDO6 VDDA1 VSSA1 AN38 AN9 AN10 AN18 AN2 AN6 AN24 17 18 20 21 22 VDD VDD33 VSS MDO4 MDO0 VSS MDO2 MDO1 VSS VDDE7 VDD C MDO3 VSS VDDE7 TCK TDI D VDDE7 TMS TDO TEST E EVTI EVTO F ETPUA ETPUA ETPUA ETPUA 21 24 27 25 ETPUA ETPUA ETPUA ETPUA F 18 23 22 17 G ETPUA ETPUA ETPUA ETPUA 20 19 14 13 H ETPUA ETPUA ETPUA VDDEH 16 15 10 1 19 VDDE7 JCOMP RDY Version 2.2p – 13 July 2004 A VDDE7 B MCKO MSEO0 MSEO1 G VDDEH GPIO 10 203 GPIO 204 SINB H ETPUA ETPUA ETPUA ETPUA J 12 11 9 6 VSS VSS VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 J K ETPUA ETPUA ETPUA ETPUA 8 7 2 5 VSS VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 K L ETPUA ETPUA ETPUA ETPUA 4 3 0 1 VSS VSS VSS VSS VSS VSS PCSB5 SOUTA M TCRCLK BDIP A CS1 CS0 N CS3 WE1 WE0 P ADDR 16 CS2 VDDE2 VDDE2 ADDR RD_WR VDD33 17 VSS VSS VSS VSS PCSA1 PCSA0 PCSA2 VSS VDDE2 VSS VSS VSS PCSA4 TXDA PCSA5 VFLASH N VSS VSS VDDE2 VSS VSS VSS CNTXC RXDA RSTOUT RST CFG TA WKP CFG ADDR 20 ADDR 21 ADDR 12 TS RXDB U ADDR 22 ADDR 23 ADDR 13 ADDR 14 V ADDR 24 ADDR 25 ADDR 15 ADDR 31 T ADDR ADDR W VDDE2 26 30 Note: NC No connect. Reserved (W18 & Y19 are shorted to each other) DATA 11 DATA 12 DATA 14 EMIOS EMIOS VDDEH EMIOS EMIOS VDDE5 21 2 4 12 8 DATA 10 GPIO 207 DATA 13 DATA 15 EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 22 6 10 15 17 VDDE2 VDD33 VDDE2 VSS VDD VDDE2 DATA 8 DATA 9 Y ADDR 28 ADDR 27 VSS VDD AA ADDR 29 VSS VDD VDDE2 DATA 1 VDDE2 GPIO 206 DATA 5 DATA 7 DATA 2 DATA 3 DATA 4 DATA 6 OE 5 6 7 8 9 AB VSS VDD VDDE2 DATA 0 1 2 3 4 SCKA L VSS ADDR VDDE2 19 ADDR R 18 SINA NC VPP M P CNRXC TXDB RESET R BOOT CFG1 VDDEH PLL 6 CFG1 VRC VSS VSS SYN T BOOT EXTAL U CFG0 VDD VRC CTL PLL CFG0 XTAL V VSS VDD VRC33 VDD SYN W NC VSS VDD VDD33 Y VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 23 19 16 3 5 9 13 VDD AA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 20 18 14 0 1 4 7 11 ENG CLK VSS AB 21 22 10 11 12 13 14 15 16 17 18 19 20 Figure 13. MPC5533/MPC5534/MPC5553/MPC5565 324 PBGA Ball Map Diagram On the MPC5561 and MPC5567 ball T21 is PLLCFG2 instead of VRCVSS. PLLCFG2 is required to support a 40 MHz clock option for the FlexRay. MPC5500 Family Overview, Rev. 1 20 Freescale Semiconductor Package Options 4.3 4.3.1 208 MAP BGA Ball Map MPC5533/MPC5534/MPC5553/MPC5565/MPC5566/MPC5567 Figure 14 is a pinout for the MPC5533/MPC5534/MPC5553/MPC5565/MPC5567 208 MAP PBGA package. NOTE VDDEH10 and VDDEH6 are connected internally on the 208-ball package and are listed as VDDEH6. 1 2 3 A VSS AN9 AN11 B VDD VSS AN38 AN21 VDD VSS AN17 C VSTBY D VDD33 AN39 4 VDD VSS AN37 VDD E ETPUA ETPUA 30 31 F ETPUA ETPUA ETPUA 28 29 26 5 6 7 8 9 10 11 12 13 AN1 AN5 VRH VRL AN27 VSSA0 AN12 MDO2 MDO0 VDD33 VSS A AN0 AN4 REF BYPC AN22 AN25 AN28 VDDA0 AN13 MDO3 MDO1 VSS VDD B AN34 AN16 AN3 AN7 AN23 AN32 AN33 AN14 AN15 VSS MSEO0 TCK C AN31 AN35 VDDEH 9 TEST D VDDA1 VSSA1 AN18 AN6 AN2 AN36 AN24 AN30 8 June 2005p 14 15 VSS TMS EVTO VDDE7 TDI EVTI VDDEH 6 TDO 16 MSEO1 E MCKO JCOMP F ETPUA ETPUA ETPUA ETPUA G 24 27 25 21 VSS VSS VSS VSS SOUTB PCSB3 H ETPUA ETPUA ETPUA ETPUA 23 22 17 18 VSS VSS VSS VSS PCSA3 PCSB4 PCSB2 PCSB1 H J ETPUA ETPUA ETPUA ETPUA 14 20 19 13 VSS VSS VSS VSS PCSB5 TXDA PCSA2 SCKB J ETPUA ETPUA ETPUA VDDEH K 16 15 7 1 VSS VSS VSS VSS CNTXC RXDA RSTOUT VPP L ETPUA ETPUA ETPUA TCRCLK 12 11 6 A M ETPUA ETPUA ETPUA ETPUA 10 9 1 5 R T ETPUA ETPUA 3 2 CS0 VSS Note: No connect. R1 reserved for CS0 CS0 BOOT CFG1 VSS VRC CTL PLL CFG1 EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA 16 17 6 8 22 VDD VSS VRC33 XTAL P EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA CNRXB 14 19 23 4 3 9 11 VDD VSS VDD SYN R EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB VDDE5 15 18 20 0 1 5 7 13 ENG CLK VDD VSS T 14 15 16 VSS VDD VDD GPIO 207 VDDE2 VDD GPIO 206 VDD OE 1 2 3 K RESET L PLL CFG0 VSS VSS WKP CFG PCSB0 G RXDB VDD33 EMIOS EMIOS VDDEH EMIOS EMIOS VDD33 4 12 2 10 21 ETPUA ETPUA ETPUA N 8 4 0 P TXDB CNRXC SINB 4 5 6 7 8 9 10 11 12 13 VSS SYN M EXTAL N Figure 14. MPC5534/MPC5553/MPC5565/MPC5567 208 PBGA Ball Map Diagram MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 21 Package Options Appendix A: Revision History Table 4 is a revision history for this document. Table 4. Revision History Revision Number 0 Substantive Changes Initial release. A.1 • Added Section 11, “MPC5554 Evaluation Board Availability.” (now removed) • Changed TCRCLKB(IRQ6) to TCRCLKA(IRQ) in Table 16.(now removed) • Changed NC to eTPUB24 and NC to TCRCLKB in Table 17.(now removed) A.4 • First Confidential release for customers. A.5 • Added MPC5566. Corrected memory map for MPC5565 and MPC5567 showing flash size and eTPU shared RAM size. • Corrected MPC5565 and MPC5567 block diagrams - only 1 eTPU each. • Re-ordered the block diagrams and tables to put into devices into numeric order, instead of introduction order. • Added place holder for MPC557x future devices in the device roadmap. • Added MPC5533 block diagram. • L2 SRAM renamed just SRAM. • Corrected SINA ball number in Section 4.1.2. • Modified ordering of device introduction schedules in Figure 1 MPC5500 roadmap figure. • Added cache associativity to Table 1 • Renamed all pinout diagrams to ball map diagrams for consistency. • Removed eMIOS on MPC5533. Corrected eDMA channels on MPC5533, MPC5534, MPC5565, MPC5567. Corrected number of interrupt channels in Table 1. • Corrected FlexCAN memory map for MPC5533, MPC5534, and MPC5553 in Table 2. • MPC5567 ball map updated for VDDE13. • Cache associativity added to feature table. • Review comment - MPC5566 has 64 eTPU channels. • Updated introduction paragraph to reference all parts covered in this document. • Changed MPC5567 SRAM size to 80K from 64K for revision A of the MPC5567. MPC5500 Family Overview, Rev. 1 22 Freescale Semiconductor Package Options Table 4. Revision History (continued) Revision Number Substantive Changes A.6 • Changed MPC5565 416 BPGA package to consult factory—tooling based on forecasted demand. Notes added to 208 MAPBGA and some other configurations that they will not be available through the distribution channel. A.6.1 • Reviewed by BB, LW, and VG. Editorial and formatting edits by AE. Figures redrawn. 0 • First Public Release 1 • Removed second ADC from MPC5533 block diagram (Figure 2). • Updated package availability for family. On package options that were previously as Yes (available) with the footnotes 4 (Not available to distribution customers) or 7 (Depending on demand, consult factory) changed to “No - consult factory for availability”. • Corrected Ball J23 (VDDEH10) on 416 MPC5553, MPC5566, and MPC5567 Ball Map. • Corrected VDDEH10 on 324 (H19) ball maps. • Corrected eTPUA6 (ball L3) in the 208 MAPBGA (Figure 14). • Added MPC5561 to family comparison (Table 1) and memory map (Table 2). Added MPC5561 block diagram. • Added note on MPC5565 crossbar size in comparison table (Table 1) to indicate that there are 5 ports with 2 unused. • Updated references from PowerPC to Power. • Added reference for PLLCFG2 for the 324 Ball Map for the MPC5567 and MPC5561. • Updated roadmap timing, including the MPC5561 part number, added MPC5510 Family. • Deleted 324 package options for MPC5533. Small editorial and formatting edits by SF. MPC5500 Family Overview, Rev. 1 Freescale Semiconductor 23 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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