DC Motor with Dead-Time Correction - XOR version TPU Function Set

Freescale Semiconductor, Inc.
Application Note
AN2527/D
Rev. 0, 5/2003
DC Motor with Dead-Time
Correction – XOR version
TPU Function Set
(DCmDtXor)
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By Milan Brejl, Ph.D.
Functional Overview
The DC Motor with Dead-Time Correction – XOR version (DCmDtXor) TPU
function is a version of the DC Motor with Dead-Time Correction (DCmDt)
function that uses two TPU channels to generate one PWM output channel.
The TPU channel outputs are connected to an XOR gate whos output is the
required PWM signal. See Figure 1. An advantage of this solution is that the
full range (0% to 100%) of PWM duty-cycle ratios is available. There is no MPW
(minimum pulse width) parameter to limit the edge duty-cycle ratios in this
version, unlike in the DCmDt. A disadvantage is that the number of assigned
TPU channels is doubled.
Positive current
50% PWM
PWM period
PWM period
center-time
center-time
DT
DT
SW1_1
XOR
SW1
XOR
SW2
XOR
SW3
XOR
SW4
Negative current
DT
DT
SW1_2
SW2_1
SW2_2
DT
SW3_1
DT
DT
DT
SW3_2
SW4_1
SW4_2
motor
voltage
Figure 1. Functionality of XOR version – illustration
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The dead-time correction technique requires knowledge the instantaneous
direction of the motor current. In case of positive motor current, the SW1 hightime and SW4 low-time are equal to the calculated high-times, and the SW2
and SW3 channels control the dead-time. In the case of negative motor current,
the SW2 low-time and SW3 high-time are equal to the calculated high-times,
and the SW1 and SW4 channels control the dead-time. See Figure 2.
Positive current
(Q2)
- 50% PWM
Positive current
(Q1)
50% PWM
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PWM period
PWM period
center-time
DT
center-time
DT
DT
DT
SW1
SW1
SW2
SW2
DT
DT
DT
SW3
SW3
SW4
SW4
motor
voltage
motor
voltage
Negative current
(Q3)
Negative current
(Q4)
- 50% PWM
50% PWM
PWM period
PWM period
center-time
center-time
DT
DT
DT
SW1
SW1
SW2
SW2
DT
SW3
SW4
motor
voltage
DT
DT
DT
DT
DT
SW3
SW4
motor
voltage
Figure 2. Dead-Time Correction Technique
2
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Function Set Configuration
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The function set consists of 5 TPU functions:
•
DC Motor with Dead-Time Correction – XOR version – C channels
(DCmDtXor_C)
•
DC Motor with Dead-Time Correction – XOR version – T channels
(DCmDtXor_T)
•
Synchronization Signal for DC Motor with Dead-Time Correction – XOR
version (DCmDtXor_sync)
•
Resolver Reference Signal for DC Motor with Dead-Time Correction –
XOR version (DCmDtXor_res)
•
Fault Input for DC Motor with Dead-Time Correction – XOR version
(DCmDtXor_fault)
The DCmDtXor TPU function set drives a DC Motor, independently of the CPU.
The CPU is required only to set a duty-cycle (dc) parameter in the range (–1,1).
This determines both the speed and the direction. The function generates
unipolar-switched center-aligned PWM signals.
The DCmDtXor_C and DCmDtXor_T TPU functions work together to generate
4 pairs of XOR gate inputs. The XOR gate outputs then produce a 4-channel
2-phase center-aligned PWM signal with dead-time between the top and
bottom channels. The Synchronization Signal for the DCmDtXor function can
be used to generate one or more adjustable signals for a wide range of uses.
These are synchronized to the PWM, and track changes in the PWM period.
The Resolver Reference Signal for the DCmDtXor function can be used to
generate one or more 50% duty-cycle adjustable signals that are also
synchronized to the PWM.The Fault Input for the DCmDtXor function is a TPU
input function that sets all PWM outputs low when the input signal goes low.
Function Set Configuration
None of the TPU functions in the DC Motor with Dead-Time Correction – XOR
version TPU function set can be used separately. The DCmDtXor_C and
DCmDtXor_T functions have to be used together. The DCmDtXor_C runs on
pins SW1_1 and SW3_1 – see Figure 1. The DCmDtXor_T runs on the other
pins. One or more channels running Synchronization Signal for DCmDtXor as
well as Resolver Reference Signals for DCmDtXor functions can be added.
They can run with different settings on each channel. The function Fault Input
for DCmDtXor can also be added. It is recommended to use it on channel 15,
and to set the hardware option that disables all TPU output pins when the
channel 15 input signal is low (DTPU bit = 1). This ensures that the hardware
reacts quickly to a pin fault state. Note that it is not only the PWM channels, but
all TPU output channels, including the synchronization signals, that are
disabled in this configuration.
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Table 1 shows the configuration options and restrictions.
Table 1. DCmDtXor TPU function set configuration options and
restrictions
DCmDtXor_C
DCmDtXor_T
DCmDtXor_sync
DCmDtXor_res
Optional/
Mandatory
mandatory
mandatory
optional
optional
How many
channels
2
6
1 or more
1 or more
DCmDtXor_fault
optional
1
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TPU function
Assignable channels
any 2 channels
any 6 channels
any channels
any channels
any, recommended is 15 and DTPU
bit set
Table 2 shows an example of configuration.
Table 2. Example of configuration
Channel
0
1
2
3
4
5
6
7
10
11
15
TPU function
DCmDtXor_C
DCmDtXor_T
DCmDtXor_T
DCmDtXor_T
DCmDtXor_C
DCmDtXor_T
DCmDtXor_T
DCmDtXor_T
DCmDtXor_sync
DCmDtXor_res
DCmDtXor_fault
Priority
high
high
high
high
high
high
high
high
low
low
high
Table 3 shows the TPU function code sizes.
Table 3. TPU function code sizes
TPU function
DCmDtXor_C
DCmDtXor_T
DCmDtXor_sync
DCmDtXor_res
DCmDtXor_fault
4
Code size
139µ instructions + 8 entries = 147 long words
3 µ instructions + 8 entries = 11 long words
26 µ instructions + 8 entries = 34 long words
38 µ instructions + 8 entries = 46 long words
9 µ instructions + 8 entries = 17 long words
DC Motor with Dead-Time Correction – XOR version TPU Function Set (DCmDtXor)
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Function Set Configuration
Configuration Order
The CPU configures the TPU as follows.
1. Disables the channels by clearing the two channel priority bits on each
channel used (not necessary after reset).
2. Selects the channel functions on all used channels by writing the
function numbers to the channel function select bits.
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3. Initializes function parameters. The parameters T, DT and
sync_presc_addr must be set before initialization. If a DCmDtXor_sync
channel or a DCmDtXor_res channel is used, then its parameters must
also be set before initialization.
4. Issues an HSR (Host Service Request) type %10 to one of the
DCmDtXor_C channels to initialize all DCmDtXor_C and DCmDtXor_T
channels. Issues an HSR type %10 to the DCmDtXor_sync channels,
DCmDtXor_res channels and DCmDtXor_fault channel, if used.
5. Enables servicing by assigning high, middle or low priority to the channel
priority bits. All DCmDtXor_C and DCmDtXor_T channels must be
assigned the same priority to ensure correct operation. The CPU must
ensure that the DCmDtXor_sync or DCmDtXor_res function is initialized
after the initialization of DCmDtXor:
–
–
–
NOTE:
assign a priority to the DCmDtXor_C and DCmDtXor_T channels to
enable their initialization
if a Synchronization Signal or a Resolver Reference Signal channel
is used, wait until the HSR bits are cleared to indicate that
initialization of the DCmDtXor_C and DCmDtXor_T channels has
completed and
assign a priority to the DCmDtXor_sync or DCmDtXor_res channel
to enable its initialization
A CPU routine that configures the TPU can be generated automatically using
the MPC500_Quick_Start Graphical Configuration Tool.
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Detailed Function Description
DC Motor with DeadTime Correction –
XOR version – C
channels
(DCmDtXor_C) and
DC Motor with DeadTime Correction –
XOR version – T
channels
(DCmDtXor_T)
The DCmDtXor_C and DCmDtXor_T TPU functions work together to generate
4 pairs of XOR gate inputs. The XOR gate outputs then produce a 4-channel
2-phase center-aligned PWM signal with dead-time between the top and
bottom channels. In order to charge the bootstrap transistors, the PWM signals
start to run 1.6ms after their initialization (at 20MHz TCR1 clock). The functions
generate signals corresponding to a value 0 in duty-cycle ratio dc until the first
dc value is processed, or for at least one PWM period.
The CPU controls the PWM output by setting the TPU parameters. The dutycycle ratio dc, PWM period T and current can be adjusted during run time.
Conversely, dead-time (DT) is not supposed to be changed during run time.
The duty-cycle ratio dc can gain a value in the range (–1, 1). The sign controls
the motion system direction, while the absolute value controls the amplitude of
the applied voltage.
The following figures show the input dc value and corresponding XOR gate
outputs (valid for positive motor current):
dc = - 0.5
dc = 0
dc = 0.5
PWM period
PWM period
PWM period
center-time
center-time
DT
DT
DT
center-time
DT
DT
DT
SW1
SW2
DT
DT
DT
DT
DT
SW3
SW4
motor
voltage
Figure 3. Unipolar switching
6
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DT
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Detailed Function Description
The following equations describe how the PWM signal transition times
SW1_1T, SW1_2T, SW2_1T, SW2_2T, SW3_1T, SW3_2T, SW4_1T and
SW4_2T are calculated:
Tdc = T ⋅ dc
T + Tdc
2
T − Tdc
Y =
2
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X=
Positive current (current = 0)
X
2
X
B=
+ DT
2
Y
C =
2
Y
D =
+ DT
2
A=
Negative current (current = 1)
X
− DT
2
X
B=
2
Y
C =
− DT
2
Y
D =
2
A=
SW1_1 T = center _ time − A
SW1_2 T = center _ time + A
SW2_1 T = center _ time − B
SW2_2 T = center _ time + B
SW3_1 T = center _ time − C
SW3_2 T = center _ time + C
SW4_1 T = center _ time − D
SW4_2 T = center _ time + D
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Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 4. DCmDtXor_C Control Bits
Name
3
2
1
0
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Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
Options
DCmDtXor_C function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Stop
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
0
Table 5. DCmDtXor_T Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
0
Host Sequence Bits (HSQ)
8
Options
DCmDtXor_T function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Not used
11 – Not used
xx – Not used
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Detailed Function Description
Table 5. DCmDtXor_T Control Bits
Name
Options
0
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
Table 6. DCmDtXor_C and DCmDtXor_T Parameter RAM
SW2_1
SW1_2
SW1_1
Channel
SW2_2
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0
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
XY_X
1
SW13_2_ch_SW1
SW24_1_ch_SW1
2
SW24_2_ch_SW1
3
4
dc
T
5
other_ch_SW1
6
7
fault_pinstate
0
Ttime_SW1_2
T_copy
1
2
L
center_time
3
DT
4
5
CPU14
6
7
0
Ttime_SW2_1
1
2
3
4
current
5
sync_presc_addr
6
7
0
Ttime_SW2_2
1
2
3
4
5
6
7
4
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3
2
1
0
9
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Table 6. DCmDtXor_C and DCmDtXor_T Parameter RAM
SW4_2
SW4_1
SW3_2
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SW3_1
Channel
10
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
XY_Y
SW13_2_ch_SW3
1
2
SW24_1_ch_SW3
SW24_2_ch_SW3
3
4
5
6
other_ch_SW3
7
0
Ttime_SW3_2
1
2
3
4
5
6
7
0
Ttime_SW4_1
1
2
3
4
5
6
7
0
Ttime_SW4_2
1
2
3
4
5
6
7
4
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3
2
1
0
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Detailed Function Description
Table 7. DCmDtXor_C and DCmDtXor_T parameter description
Parameter
Format
Description
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Parameters written by CPU
dc
16-bit fractional
duty-cycle ratio in the range
<–1,1)
current
0 or 1
0 ... positive motor current
1 ... negative motor current
T
16-bit unsigned integer
PWM period in number of TCR1
TPU cycles
DT
16-bit unsigned integer
Dead-time in number of TCR1
TPU cycles
CPU14
16-bit unsigned integer
Time of 14 IMB clocks in TCR1
clocks.
8-bit unsigned integer
address of synchronization
channel prescaler parameter:
$X4,
where X is synchronization
channel number.
$0 if no synchronization channel
is used.
sync_presc_addr
Parameters written by TPU
fault_pinstate
0 or 1
If fault channel is used, state of
fault pin:
0 ... low
1 ... high
Other parameters are just for TPU function inner use.
Performance
Table 8. DCmDtXor_T State Statistics
State
ST
SF
Max IMB Clock Cycles
2
2
RAM Accesses by TPU
1
0
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Table 9. DCmDtXor_C State Statistics
State
INIT
STOP
C1
C2
Max IMB Clock Cycles
90
100
76
34
RAM Accesses by TPU
16
1
13
10
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Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
C1
SW1_1
dc < 0%
T
T
center-time
center-time
C2
C2
ST
SF
SW1_2
SW2_1
dc > 0%
SF
SF
SF
ST
SF
C2
SW3_1
C1
SF
SW3_2
SF
SW4_1
ST
ST
C2
SF
SF
ST
SF
SW4_2
ST
ST
SF
SW2_2
ST
ST
ST
ST
SF
flag0 = 1
link
Figure 4. DCmDtXor_C and DCmDtXor_T timing
12
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ST
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Detailed Function Description
SF
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SF
ST
ST
ST
SF
ST
flag0 = 1
link
Figure 5. DCmDtXor_T state diagram and 3 cases of timing
NOTE:
The timing of the link determines which case accurs
INIT
C1
HSR = 10
STOP
HSR = 11
C2
Figure 6. DCmDtXor_C state diagram
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Synchronization
signal for DC Motor
with Dead-Time
Correction – XOR
version
(DCmDtXor_sync)
The DCmDtXor_sync TPU function uses information obtained from
DCmDtXor_C and DCmDtXor_T functions, the actual PWM center times and
the PWM periods. This allows a signal to be generated, that tracks the changes
in the PWM period and is always synchronized with the PWM. The
synchronization signal is a positive pulse generated repeatedly after the
prescaler or presc_copy PWM periods (see next paragraph). The low to high
transition of the pulse can be adjusted by a parameter, either negative or
positive, to go before or after the PWM period center time of a number of TCR1
TPU cycles. The pulse width pw is another synchronization signal parameter.
move > 0
prescaler = 1
pw
|move|
center_time
center_time
T
T
move < 0
prescaler = 2
pw
|move|
center_time
center_time
center_time
T
T
T
Figure 7. Synchronization signal adjustment examples
Synchronized Change
of PWM Prescaler
And Synchronization
Signal Prescaler
14
The DCmDtXor_sync TPU function actually uses the presc_copy parameter
instead of the prescaler parameter. The prescaler parameter holds the
prescaler value that is copied to the presc_copy by the DCmDtXor_bottom
function at the time of the PWM parameters reload. This ensures that new
prescaler values for the PWM signals, as well as the synchronization signal, are
applied at the same time. Write the synchronization signals prescaler
parameter address to the sync_presc_addr parameter to enable this
mechanism. Write 0 to disable it, and remember to set the synchronization
signal presc_copy parameter instead of the prescaler parameter in this case.
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Detailed Function Description
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 10. DCmDtXor_sync Control Bits
Name
3
2
1
0
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
0
TPU function DCmDtXor_sync generates an interrupt after each low to high
transition.
Table 11. DCmDtXor_sync Parameter RAM
Channel
Synchronization channel
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Channel Function Select
Options
DCmDtXor_sync function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
Parameter 15 14 13 12 11 10 9 8 7 6
0
move
1
pw
prescaler
2
presc_copy
3
4
time
dec
5
T_copy
6
5
4
3
2
1
0
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Table 12. DCmDtXor_sync parameter description
Parameter
Format
Description
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Parameters written by CPU
move
16-bit signed integer
The number of TCR1 TPU cycles
to forego (negative) or come after
(positive) the PWM period center
time
pw
16-bit unsigned integer
Synchronization pulse width in
number of TCR1 TPU cycles.
16-bit unsigned integer
The number of PWM periods per
synchronization pulse
– use in case of synchronized
prescalers change
16-bit unsigned integer
The number of PWM periods per
synchronization pulse
– use in case of asynchronized
prescalers change
prescaler
presc_copy
Parameters written by TPU
Other parameters are just for TPU function inner use.
Performance
There is one limitation. The absolute value of parameter move has to be less
then a quarter of the PWM period T.
move <
T
4
Table 13. DCmDtXor_sync State Statistics
State
INIT
S1
S2
S3
NOTE:
16
Max IMB Clock Cycles
12
12
8
16
RAM Accesses by TPU
5
6
3
7
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
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Detailed Function Description
S2
S1
S3
S1
center_time
center_time
center_time
T
T
T
S2
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Figure 8. DCmDtXor_sync timing
HSR = 10
INIT
S1
S2
S3
Figure 9. DCmDtXor_sync state diagram
Resolver Reference
Signal for DC Motor
with Dead-Time
Correction – XOR
version
(DCmDtXor_res)
The DCmDtXor_res TPU function uses information read from the
DCmDtXor_C and DCmDtXor_T functions, the actual PWM center times and
the PWM periods. This allows a signal to be generated, which tracks the
changes of the PWM period and is always synchronized with the PWM. The
resolver reference signal is a 50% duty-cycle signal with a period equal to
prescaler or synchronization channel presc_copy PWM periods (see next
paragraph). The low to high transition of the pulse can be adjusted by a
parameter, either negative or positive, to go before or after the PWM period
center time of a number of TCR1 TPU cycles.
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move > 0
prescaler = 1
|move|
center_time
center_time
T
T
center_time
center_time
center_time
T
T
T
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move < 0
prescaler = 2
|move|
Figure 10. Resolver reference signal adjustment examples
Synchronized Change
of PWM Prescaler
And Resolver
Reference Signals
Prescaler
The DCmDtXor_res TPU function can inherit the Synchronization Signal
prescaler that is synchronously changed with PWM prescaler. Write the
synchronization signals presc_copy parameter address to the presc_addr
parameter to enable this mechanism. Write 0 to disable it, and in this case set
prescaler parameter to directly specify prescaler value.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 14. DCmDtXor_res Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
18
Options
DCmDtXor_res function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
DC Motor with Dead-Time Correction – XOR version TPU Function Set (DCmDtXor)
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Table 14. DCmDtXor_res Control Bits
Name
1
Options
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
Table 15. DCmDtXor_res Parameter RAM
Channel
Resolver
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0
Parameter 15 14 13 12 11 10 9 8 7 6
0
move
1
2
presc_addr
prescaler
3
time
4
5
dec
T_copy
6
7
5
4
3
2
1
0
Table 16. DCmDtXor_res parameter description
Parameter
Format
Description
Parameters written by CPU
move
presc_addr
16-bit signed integer
16-bit unsigned integer
The number of TCR1 TPU cycles
to forego (negative) or come after
(positive) the PWM period center
time
$00X6, where X is a number of
Synchronization Signal channel,
to inherit Sync. channel prescaler
or
$0000 to enable direct specification
of prescaler value in prescaler
parameter
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Table 16. DCmDtXor_res parameter description
Parameter
prescaler
Format
Description
The number of PWM periods per
synchronization pulse
– use when apresc_addr = 0
1, 2, 4, 6, 8, 10, 12, 14, ...
Parameters written by TPU
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Other parameters are just for TPU function inner use.
Performance
There is one limitation. The absolute value of parameter move has to be less
than a quarter of the PWM period T.
move <
T
4
Table 17. DCmDtXor_res State Statistics
State
INIT
S1
S3
NOTE:
S1
Max IMB Clock Cycles
12
26
16
RAM Accesses by TPU
5
9
7
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
S3
S1
center_time
center_time
center_time
T
T
T
Figure 11. DCmDtXor_res timing
20
DC Motor with Dead-Time Correction – XOR version TPU Function Set (DCmDtXor)
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HSR = 10
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INIT
S1
S3
Figure 12. DCmDtXor_res state diagram
Fault Input for DC
Motor with DeadTime Correction –
XOR version
(DCmDtXor_fault)
The DCmDtXor_fault is an input TPU function that monitors the pin, and if a
high to low transition occurs, immediately sets all PWM channels low and
cancels all further transitions on them. The PWM channels, as well as the
synchronization and resolver reference signal channels (if used), have to be
initialized again to start them running.
The function returns the actual pinstate as a value of 0 (low) or 1 (high) in the
parameter fault_pinstate. The parameter is placed on the SW1_1 channel to
keep the fault channel parameter space free.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 18. DCmDtXor_fault Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
Options
DCmDtXor_fault function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
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Table 18. DCmDtXor_fault Control Bits
Name
1
Options
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
0
Host Service Bits (HSR)
1
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
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0
0
TPU function DCmDtXor_fault generates an interrupt when a high to low
transition appears.
Table 19. DCmDtXor_fault Parameter RAM
Fault input
Channel
Parameter 15 14 13 12 11 10 9
0
1
2
3
4
5
6
7
8
7
6
5
4
3
Table 20. DCmDtXor_fault parameter description
Parameter
Format
Description
–
fault_pinstate
22
0 or 1
State of fault pin:
0 ... low
1 ... high
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1
0
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Detailed Function Description
Performance
Table 21. DCmDtXor_fault State Statistics
State
INIT
FAULT
NO_FAULT
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NOTE:
Max IMB Clock Cycles
8
106
4
RAM Accesses by TPU
2
2
1
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
NO_FAULT
FAULT
Figure 13. DCmDtXor_fault timing
HSR = 10
INIT
FAULT
NO_FAULT
Figure 14. DCmDtXor_fault state diagram
DC Motor with Dead-Time Correction – XOR version TPU Function Set (DCmDtXor)
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AN2527/D
Rev. 0
5/2003
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